CN111950222B

CN111950222B - Method for generating circuit layout by using simulation software

Info

Publication number: CN111950222B
Application number: CN201910357312.0A
Authority: CN
Inventors: 刘建成; 刘时志; 张云智; 高淑怡
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2019-04-29
Filing date: 2019-04-29
Publication date: 2024-05-24
Anticipated expiration: 2039-04-29
Also published as: CN111950222A

Abstract

A method for generating a circuit layout using simulation software, comprising the steps of: (A) Programming a plurality of blocks on a circuit board, wherein each block comprises: an operation space and a reserved space; (B) Determining the size of the reserved space in the block according to at least one specific condition; (C) Determining whether to adjust the size of the reserved space in the block determined in the step (B) according to at least one judging condition; and (D) when the step (C) judges that adjustment is not needed, generating the circuit layout according to the size of the reserved space in the block determined in the step (B).

Description

Method for generating circuit layout by using simulation software

Technical Field

The present disclosure relates to Power Integrity (PI) applications, and more particularly, to a method for determining circuit layout properly to solve the problem of circuit failure.

Background

Circuit layouts, such as printed circuit board layout (PCB layout), take into account voltage degradation (also known as IR Drop), often leave room between components to place capacitors (also known as DCAP) as a solution to circuit operation anomalies. The voltage decay is divided into a static voltage decay and a dynamic voltage decay, wherein the static voltage decay is mainly related to the structure and the connection details of the power supply network, so that the static voltage decay mainly considers the resistance effect and only needs to analyze the influence of the resistance. Dynamic voltage decay is the voltage drop caused by current fluctuations of the power supply when the circuit switch is switched. This phenomenon occurs at the trigger edge of the clock, and often generates a large current over the whole chip in a short time, and this instantaneous large current causes a voltage decay phenomenon. Meanwhile, the larger the number of transistors of the switch is, the easier the dynamic voltage decay phenomenon is triggered.

However, the prior art lacks a proper mechanism to determine how much space is reserved between the devices to place the capacitors, for example, the prior art does not consider the toggle rate of the circuit, and only simply find out the space available for placing the capacitors from the existing space as much as possible. Referring to fig. 1, fig. 1 is a schematic circuit layout diagram of a prior art reserved DCAP space, which is not efficient for reducing voltage degradation because the prior art method belongs to a random reserved space or is guessed empirically. For example, if some blocks are already placed very fully (space usage is high), there is not enough space to place DCAP with higher capacitance (capacitance is proportional to volume) to suppress dynamic voltage decay, and the binary thixotropic rate of biased such higher density blocks is usually higher, such as hot spot blocks (like the circled locations in the figure) near the processing Chip (CPU), display chip (GPU) and memory (DDR). In contrast, there is a very plenty of space for DCAP placement in open areas where the device placement density is not high, but such areas typically do not have a very high binary thixotropic rate.

In summary, the circuit layout efficiency of the prior art for voltage decay prevention is very poor, which also results in a reduction in performance and a significant increase in cost.

Disclosure of Invention

In view of the fact that the conventional circuit design method does not consider the influence of the toggle rate (toggle rate) on the circuit layout, the present invention proposes a method for determining the reserved DCAP space based on the degree of the toggle rate, and analyzes the information by software to properly determine the DCAP space scheme, so as to achieve the purpose of reducing the dynamic voltage and optimize the circuit configuration.

An embodiment of the present invention provides a method for generating a circuit layout using simulation software, comprising the steps of: (A) Programming a plurality of blocks on a circuit board, wherein each block comprises: an operation space and a reserved space; (B) Determining the size of the reserved space in the block according to at least one specific condition; (C) Determining whether to adjust the size of the reserved space in the block determined in the step (B) according to at least one judging condition; and (D) when the step (C) judges that adjustment is not needed, generating the circuit layout according to the size of the reserved space in the block determined in the step (B).

Drawings

Fig. 1 is a circuit layout diagram of a prior art reserved DCAP space.

Fig. 2 is a block diagram of a circuit layout for generating the present invention.

FIG. 3 is a table of block classifications generated according to the magnitude of the bin's binary thixotropic rate.

Fig. 4 is a schematic diagram of a circuit layout obtained using the architecture shown in fig. 2.

FIG. 5 is a method of generating a circuit layout using simulation software according to an embodiment of the present invention.

Symbol description

202-212, 502-508 Steps

FFG 1-FFG 8 block group

Cell (n) -Cell (n-31) block

Capacitance placement space reserved by DCAP 2-DCAP 16

Detailed Description

Referring to fig. 2, fig. 2 is a block diagram illustrating a circuit layout according to the present invention, first, in step 202, binary thixotropic rate data (which may be summarized as a data table of binary thixotropic rates) of each block on a circuit board is provided. In step 204, a preliminary block configuration scheme is generated according to the collected binary thixotropic rate data and netlist (netlist) information, and a plurality of blocks are planned on the circuit board, wherein each of the blocks includes an operation space for setting components and a DCAP reserved space, and an access rate of each block can be obtained through the binary thixotropic rate data table.

Referring to step 204, referring to FIG. 3, FIG. 3 is a block classification table according to the binary thixotropic rate of the block, wherein the blocks cell (n), cell (n-1), cell (n-2), cell (n-3) classified into the block group FFG1 have the highest binary thixotropic rate, so that the larger the number allocated to DCAP16 ("DCAP"), the larger the space is reserved for placing the capacitor. For example, the block set to DCAP8 will be allocated less capacitance headroom than the block set to DCAP16, the block set to DCAP4 will be allocated less capacitance headroom than the block set to DCAP8, and so on. It should be noted that, although the capacitor is used as a solution for voltage decay in the example of the present invention, the present invention is not limited thereto, and the capacitor may be replaced by another passive device as long as the same effect is achieved.

The dashed line in the middle of fig. 3 indicates that the current grouping only uses four block groups FFG 1-FFG 4, and the dashed line can be pulled down when finer grouping is required. For example, when the dotted line moves down by one line, the grouping of blocks becomes 5 groups. Considering that the total area of the reserved space is not made too high as the proportion of the total block, it is necessary to compromise (Trade off) how fine the packet is to be divided (i.e. the magnitude of the broken line to be pulled down). Note that step 206 may further optimize the placement of components by software functions (such as sdc and floorplan) to create candidate circuit layouts.

The above is to sort the blocks with the bi-state thixotropic rates corresponding to the blocks, respectively, wherein the reserved space allocated to the blocks is proportional to the bi-state thixotropic rate, that is, the blocks with possibly higher bi-state thixotropic rates are allocated to the larger DCAP blocks. In addition, the present invention may also consider whether a block is located at or adjacent to a hot spot (e.g., adjacent CPU, GPU, DDR, etc.), such as the distance between each block and the hot spot.

In order to utilize the redundant circuit space as much as possible for the DCAP application, and to avoid occupying the important component placement space for the DCAP, in step 208, the present invention may additionally use "DCAP blocks do not occupy 1% -3% (e.g., 2%) of the area of all blocks" as the judgment condition, which considers that if the reserved DCAP space is too large, the efficiency of the whole circuit will be affected. When it is determined that the reserved space exceeds the predetermined value (or the predetermined percentage) of the total block area, the flow must return to steps 204 and 206 to regenerate the candidate circuit layout.

Then, step 210 continues to further inspect the candidate circuit layout, and if the determined DCAP space size of the corresponding block can achieve the predetermined target for the overall dynamic voltage attenuation (DYNAMIC IR drop), the current circuit layout is used as the output final layout, and step 212 generates the circuit layout, wherein the predetermined target can be a range for enabling the circuit layout to work normally, which is not limited by the present invention.

Referring to fig. 4, fig. 4 is a schematic diagram of a circuit layout obtained by using the architecture shown in fig. 2, in which the hot spot locations are circled to have enough DCAP blocks compared with fig. 1, and there are no unused large blocks in the overall layout.

Referring to fig. 5, fig. 5 is a method for generating a circuit layout using simulation software according to an embodiment of the invention. Note that these steps are not necessarily performed in the order of execution shown in fig. 5, provided that substantially the same results are obtained. The method of fig. 5 can be briefly summarized as follows:

502: a plurality of blocks are planned on a circuit board, wherein each block comprises: an operation space and a reserved space;

504: determining the size of the reserved space in the block according to at least one specific condition;

506: determining whether the determined size of the reserved space in the block needs to be corrected according to at least one judging condition, if so, returning to the step 504; if not, the flow proceeds to step 508;

508: generating a circuit layout according to the determined size of the reserved space in the block.

Since the details of each step in fig. 5 will be readily understood by those skilled in the art after reading the above paragraphs, further description will be omitted here for brevity.

In summary, by implementing the technical features of the present invention, the redundant space on the circuit board can be utilized properly. In addition, the invention generates the corresponding circuit layout according to the binary thixotropic rate data table by software, so the generation speed is extremely high, the space utilization is extremely accurate, large blocks which cannot be utilized are not left, and the placement of important circuit elements is not sacrificed.

The foregoing description is only of the preferred embodiments of the present invention, and all equivalent changes and modifications made in the claims should be construed to fall within the scope of the present invention.

Claims

1. A method of generating a circuit layout using simulation software, comprising the steps of:

(A) Programming a plurality of blocks on a circuit board, wherein each block comprises: an operation space and a reserved space;

(B) Determining the size of the reserved space in the block according to at least one specific condition;

(C) Determining whether to adjust the size of the reserved space in the block determined in the step (B) according to at least one judging condition; and

(D) Generating the circuit layout according to the size of the reserved space in the block determined in the step (B) when the step (C) judges that the adjustment is not needed,

Wherein the at least one specific condition comprises: the at least one judgment condition comprises: whether the total reserved space in the block exceeds a preset value.

2. A method of generating a circuit layout using simulation software, comprising the steps of:

Wherein the at least one specific condition comprises: the at least one judgment condition comprises: whether the size of the reserved space in the block determined in the step (B) enables the overall dynamic voltage attenuation to reach a preset target or not.

3. A method of generating a circuit layout using simulation software, comprising the steps of:

Wherein the at least one specific condition further comprises: whether the blocks are located at the hot spot or the distance between each of the blocks and the hot spot, and the at least one judgment condition includes: whether the total reserved space in the block exceeds a preset value.

4. A method of generating a circuit layout using simulation software, comprising the steps of:

Wherein the at least one specific condition further comprises: whether the blocks are located at the hot spot or the distance between each of the blocks and the hot spot, and the at least one judgment condition includes: whether the size of the reserved space in the block determined in the step (B) enables the overall dynamic voltage attenuation to reach a preset target or not.

5. The method of any one of claims 1 to 4, wherein when step (C) determines that adjustment is required, step (a) is skipped.

6. The method of claim 1 or 2, wherein step (B) further comprises: the blocks are ordered according to the magnitude of the bi-state thixotropic rate corresponding to the block, wherein the reserved space to which a block is allocated is proportional to its bi-state thixotropic rate.

7. A method as claimed in claim 1 or 3, wherein the predetermined value is a predetermined percentage of the total area of the block, and the predetermined percentage is 1% to 3%.

8. The method of claim 2 or 4, wherein the predetermined goal is that the circuit layout is capable of maintaining a state of normal operation.

9. The method of any one of claims 1 to 4, wherein a headspace in the block is used to set a capacitance.