CN111950222A

CN111950222A - Method for generating circuit layout by using simulation software

Info

Publication number: CN111950222A
Application number: CN201910357312.0A
Authority: CN
Inventors: 刘建成; 刘时志; 张云智; 高淑怡
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2019-04-29
Filing date: 2019-04-29
Publication date: 2020-11-17

Abstract

A method for generating a circuit layout using simulation software, comprising the steps of: (A) planning a plurality of blocks on a circuit board, wherein each of the blocks comprises: an operation space and a reserved space; (B) determining the size of the reserved space in the block according to at least one specific condition; (C) determining whether to adjust the size of the reserved space in the block determined in the step (B) according to at least one determination condition; and (D) when the step (C) judges that the adjustment is not needed, generating the circuit layout according to the size of the reserved space in the block determined in the step (B).

Description

Method for generating circuit layout by using simulation software

Technical Field

The present disclosure relates to Power Integration (PI) applications, and more particularly, to a method for properly determining a circuit layout to improve the problem of abnormal operation of a circuit.

Background

In circuit layouts, such as printed circuit board layouts (PCB layout), in consideration of voltage degradation (also called IR Drop), there is usually a space reserved between devices to place capacitors (this operation is also called DCAP) as a solution to abnormal circuit operation. The voltage decline is divided into static voltage decline and dynamic voltage decline, wherein the static voltage decline is mainly related to the structure and the connection details of the power supply network, so the static voltage decline mainly considers the resistance effect and analyzes the influence of the resistance. Dynamic voltage droop is the voltage drop caused by current fluctuations when the power supply switches on and off the circuit. This phenomenon occurs at the triggering edge of the clock, often generating a large current on the whole chip in a short time, and this instantaneous large current causes the voltage decay phenomenon. Meanwhile, the more the number of the transistors of the switch is, the more easily the dynamic voltage decline phenomenon is triggered.

However, the prior art lacks a proper mechanism to determine how much space is reserved between the devices for placing the capacitors, for example, the prior art does not consider the toggle rate (toggle rate) of the circuit, and simply finds out the space for placing the capacitors from the existing space as much as possible. Referring to fig. 1, fig. 1 is a circuit layout diagram of the prior art reserved DCAP space, which is inefficient for reducing voltage degradation because the prior art method is random reserved space or guessed empirically. For example, if some blocks are fully populated (the space usage is high), there is not enough space to place DCAP with higher capacitance (the capacitance is proportional to the volume) to suppress dynamic voltage decay, and the toggle rate of blocks with higher element placement density is usually higher, such as hot spot (hotspot) blocks (as circled positions) near the processing Chip (CPU), display chip (GPU) and memory (DDR). In contrast, in the empty region where the device placement density is not high, there is a very sufficient space for placing DCAP, but such a region generally has a low two-state contact rate.

In summary, the circuit layout efficiency of the prior art for the voltage droop prevention is very poor, so that the performance is reduced and the cost is greatly increased.

Disclosure of Invention

In view of the fact that the traditional circuit design method does not consider the influence of the toggle rate (toggle rate) on the circuit planning, the invention provides a method for determining the reserved DCAP space based on the degree of the toggle rate, and analyzes information through software to properly determine the scheme of the DCAP space, so as to achieve the purpose of reducing dynamic voltage and realize the optimization of circuit configuration.

An embodiment of the present invention provides a method for generating a circuit layout using simulation software, comprising the steps of: (A) planning a plurality of blocks on a circuit board, wherein each of the blocks comprises: an operation space and a reserved space; (B) determining the size of the reserved space in the block according to at least one specific condition; (C) determining whether to adjust the size of the reserved space in the block determined in the step (B) according to at least one determination condition; and (D) when the step (C) judges that the adjustment is not needed, generating the circuit layout according to the size of the reserved space in the block determined in the step (B).

Drawings

Fig. 1 is a schematic circuit layout diagram of reserving DCAP space in the prior art.

FIG. 2 is a block diagram of a circuit layout generated according to the present invention.

FIG. 3 is a block classification table generated according to bin triggering rate sizes of blocks.

Fig. 4 is a schematic diagram of a circuit layout obtained by using the architecture shown in fig. 2.

FIG. 5 is a method for generating a circuit layout using simulation software according to an embodiment of the invention.

Description of the symbols

202 to 212, 502 to 508

FFG 1-8 block group

Cell (n) -Cell (n-31) block

Capacitor placement space reserved in DCAP 2-DCAP 16

Detailed Description

Referring to fig. 2, fig. 2 is a block diagram of a circuit layout generated according to the present invention, first, in step 202, toggle rate data (which may be summarized as a toggle rate data table) for each block on a circuit board is provided. Step 204 is to generate a preliminary block allocation scheme according to the collected toggle rate data and the information of the netlist (netlist), wherein a plurality of blocks are planned on the circuit board, each block of the blocks includes an operation space for setting components and a DCAP reserved space, and the access rate of each block can be obtained through the toggle rate data table.

Referring to fig. 3, in step 204, fig. 3 is a block classification table generated according to the bin triggering rate of the blocks, wherein the blocks cell (n), cell (n-1), cell (n-2), and cell (n-3) classified into the block group FFG1 have the highest bin triggering rate, and thus are set as DCAP16 ("DCAP" is assigned with larger numbers, so that a larger space is reserved for placing capacitance). For example, the allocated capacitance headroom of the block set to DCAP8 is less than the allocated capacitance headroom of the block set to DCAP16, the allocated capacitance headroom of the block set to DCAP4 is less than the allocated capacitance headroom of the block set to DCAP8, and so on. It should be noted that although the present invention is illustrated by using a capacitor as a solution to the voltage sag, the present invention is not limited thereto, and the capacitor can be replaced by other passive devices as long as the same effect can be achieved.

The middle dotted line in fig. 3 indicates that the current grouping is performed only for the four groups of blocks FFG 1-FFG 4, and the dotted line can be pulled down when finer grouping is required. For example, when the dotted line is shifted down by one row, the blocks become 5 groups. Considering that the total area of the reserved space does not make the proportion of the whole block too high, there must be a Trade-off (Trade off) on how fine the packet is to be divided (i.e. the magnitude of the dotted line to be pulled down). Note that step 206 may further optimize the placement of components by software functions (such as sdc and floorplan) to produce candidate circuit layouts.

The blocks are sorted according to their respective toggle rates, wherein the reserved space to which a block is allocated is proportional to its toggle rate, i.e. a block with a higher toggle rate is allocated to a larger DCAP block. In addition, the present invention may also consider whether the block is located at a hot spot (e.g., adjacent to the CPU, GPU, DDR, etc.) or adjacent to the hot spot, e.g., the distance between each block and the hot spot.

In order to utilize the redundant circuit space as much as possible for DCAP purposes and to eliminate the occupation of important device placement space in consideration of DCAP, in step 208, the present invention may additionally use "DCAP blocks do not occupy 1% -3% (e.g., 2%) of all block areas" as a determination condition, which is considered that if the reserved DCAP space is too large, the efficiency of the whole circuit will be affected. When it is determined that the reserved space exceeds the predetermined value (or the predetermined percentage) of the total block area, the process must return to

steps

204 and 206 to regenerate the candidate circuit layouts.

Then, step 210 continues to further inspect the candidate circuit layout, and if the determined DCAP space size of the corresponding block can make the overall dynamic voltage droop (dynamic IR drop) reach a predetermined target, the current circuit layout is used as the final output layout, step 212 generates the circuit layout, wherein the predetermined target may be a range within which the circuit layout can normally operate, and the invention is not limited thereto.

Referring to fig. 4, fig. 4 is a schematic diagram of a circuit layout obtained by using the architecture shown in fig. 2, compared to fig. 1, the circled hot spot locations have sufficient DCAP blocks and there are no unused large blocks in the overall layout.

Referring to fig. 5, fig. 5 is a method for generating a circuit layout using simulation software according to an embodiment of the invention. Please note that, if substantially the same result is obtained, the steps are not necessarily performed according to the order shown in FIG. 5. The method of FIG. 5 can be briefly summarized as follows:

502: planning a plurality of blocks on a circuit board, wherein each block comprises: an operation space and a reserved space;

504: determining the size of a reserved space in the block according to at least one specific condition;

506: determining whether the determined size of the reserved space in the block needs to be modified according to at least one determination condition, if yes, returning to step 504; if not, the flow proceeds to step 508;

508: generating a circuit layout according to the determined size of the reserved space in the block.

Since the details of each step in fig. 5 should be easily understood by those skilled in the art after reading the above paragraphs, further description will be omitted here for the sake of brevity.

In summary, by implementing the technical features of the present invention, the redundant space on the circuit board can be properly utilized. In addition, because the corresponding circuit layout is generated according to the two-state triggering rate data table by software, the method has extremely high generation speed and extremely accurate space utilization, and does not leave a large number of unusable blocks and sacrifice the placement of important circuit elements.

The above-mentioned embodiments are only preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.

Claims

1. A method for generating a circuit layout using simulation software, comprising the steps of:

(A) planning a plurality of blocks on a circuit board, wherein each of the blocks comprises: an operation space and a reserved space;

(B) determining the size of the reserved space in the block according to at least one specific condition;

(C) determining whether to adjust the size of the reserved space in the block determined in the step (B) according to at least one determination condition; and

(D) generating the circuit layout according to the size of the reserved space in the block determined in the step (B) when the step (C) determines that the adjustment is not required.

2. The method of claim 1, wherein when step (C) determines that adjustment is required, jumping to step (a).

3. The method of claim 1, wherein the at least one specific condition comprises: a plurality of bin touch-up rates corresponding to the blocks.

4. The method of claim 3, wherein step (B) further comprises: sorting the blocks according to the magnitude of the bin-touch-variability corresponding to the blocks, wherein the reserved space to which a block is allocated is proportional to its bin-touch-variability.

5. The method of claim 1 or 3, wherein the at least one specific condition further comprises: whether the block is located at a hot spot, or the distance between each of the blocks and a hot spot.

6. The method of claim 1, wherein the at least one determining condition comprises: whether the total reserved space in the block exceeds a predetermined value.

7. The method according to claim 6, wherein the predetermined value is a predetermined percentage of the total area of the blocks, and the predetermined percentage is 1% -3%.

8. The method according to claim 1 or 6, wherein the at least one determining condition comprises: determining whether the size of the reserved space in the block determined in step (B) allows the overall dynamic voltage decay to reach a predetermined target.

9. The method of claim 8, wherein the predetermined goal is that the circuit layout can maintain a state of normal operation.

10. The method of claim 1, wherein a reserved space in the block is used to set a capacitance.