CN111936673A - 内衬钴的特征上的铜电沉积 - Google Patents
内衬钴的特征上的铜电沉积 Download PDFInfo
- Publication number
- CN111936673A CN111936673A CN201980024132.9A CN201980024132A CN111936673A CN 111936673 A CN111936673 A CN 111936673A CN 201980024132 A CN201980024132 A CN 201980024132A CN 111936673 A CN111936673 A CN 111936673A
- Authority
- CN
- China
- Prior art keywords
- reverse
- convection
- direct current
- wafer
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010949 copper Substances 0.000 title claims abstract description 52
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 49
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 49
- 229910017052 cobalt Inorganic materials 0.000 title claims abstract description 28
- 239000010941 cobalt Substances 0.000 title claims abstract description 28
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 title claims abstract description 28
- 238000004070 electrodeposition Methods 0.000 title description 6
- 239000008151 electrolyte solution Substances 0.000 claims abstract description 32
- 238000009713 electroplating Methods 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims description 52
- 230000002045 lasting effect Effects 0.000 claims description 27
- 230000008569 process Effects 0.000 claims description 19
- 239000002131 composite material Substances 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000007747 plating Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 239000003792 electrolyte Substances 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 3
- 230000006911 nucleation Effects 0.000 description 3
- 238000010899 nucleation Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- KCXVZYZYPLLWCC-UHFFFAOYSA-N EDTA Chemical compound OC(=O)CN(CC(O)=O)CCN(CC(O)=O)CC(O)=O KCXVZYZYPLLWCC-UHFFFAOYSA-N 0.000 description 2
- 230000002378 acidificating effect Effects 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000006722 reduction reaction Methods 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910000428 cobalt oxide Inorganic materials 0.000 description 1
- IVMYJDGYRUAWML-UHFFFAOYSA-N cobalt(ii) oxide Chemical compound [Co]=O IVMYJDGYRUAWML-UHFFFAOYSA-N 0.000 description 1
- 230000000536 complexating effect Effects 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000003487 electrochemical reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000003112 inhibitor Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000003446 ligand Substances 0.000 description 1
- 230000001404 mediated effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
- C25D17/001—Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
- C25D17/007—Current directing devices
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
- C25D17/06—Suspending or supporting devices for articles to be coated
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D21/00—Processes for servicing or operating cells for electrolytic coating
- C25D21/12—Process control or regulation
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/38—Electroplating: Baths therefor from solutions of copper
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/56—Electroplating: Baths therefor from solutions of alloys
- C25D3/562—Electroplating: Baths therefor from solutions of alloys containing more than 50% by weight of iron or nickel or cobalt
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/18—Electroplating using modulated, pulsed or reversing current
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/34—Pretreatment of metallic surfaces to be electroplated
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/60—Electroplating characterised by the structure or texture of the layers
- C25D5/605—Surface topography of the layers, e.g. rough, dendritic or nodular layers
- C25D5/611—Smooth layers
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Organic Chemistry (AREA)
- Electrochemistry (AREA)
- Materials Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Metallurgy (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Sustainable Development (AREA)
- Life Sciences & Earth Sciences (AREA)
- Automation & Control Theory (AREA)
- Electrodes Of Semiconductors (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
在一示例中,电镀系统包括浴槽、保持设备、阳极、直流电源和控制器。浴槽包含电解质溶液。保持设备保持浸没在电解质溶液中的晶片。晶片包括被钴层覆盖的特征。阳极与晶片相对,并浸没在电解质溶液中。直流电源在保持设备和阳极之间产生直流电流。在保持设备和阳极之间施加正向脉冲和反向脉冲的组合,以在晶片的钴层上电镀铜层。
Description
优先权主张
本申请是于2018年3月30日提交的美国专利申请序列No.15/941,258的继续,并且根据35 U.S.C.§120要求其优先权利益,其全部内容通过引用合并于此。
技术领域
本公开内容整体上涉及电镀系统和方法,且尤其涉及用于直接在钴衬里上电镀铜的系统和方法。
背景技术
在常规的电镀方法中,在添加剂的存在下进行铜电沉积可在双镶嵌金属化中产生亚微米特征(例如通孔和沟槽)的无空隙电镀。通常采用这种方法在低于50nm技术节点的高级微处理器中制造互连。然而,随着互连件尺寸的减小,将互连件金属化工艺缩放到更窄的几何形状变得越来越困难。例如,铜在钴衬里上的物理气相沉积(PVD)会在特征开口处导致不希望有的缺陷,例如凸起或“突出”,从而导致夹断。此外,这些小特征的侧壁台阶覆盖率也可能导致在镀敷后的侧壁产生空隙。这样的缺陷会导致电短路和可靠性问题。
这里提供的背景描述是为了总体呈现本公开的背景的目的。当前指定的发明人的工作在其在此背景技术部分以及在提交申请时不能确定为现有技术的说明的各方面中描述的范围内既不明确也不暗示地承认是针对本公开的现有技术。
附图说明
一些实施方案通过示例而非限制的方式示于附图的视图中:
图1是根据示例性实施方案的电镀系统的框图。
图2是根据示例性实施方案的用于处理晶片的方法的流程图。
图3是根据示例性实施方案的用于电镀的方法的流程图。
图4是根据另一示例性实施方案的用于电镀的方法的流程图。
图5是根据另一示例性实施方案的描绘反向脉冲的示例的图。
图6示出了根据另一示例性实施方案的描绘正向脉冲和反向脉冲的示例的两个曲线图。
图7A-7D是晶片的截面图,示出了在钴层上沉积的铜层。
图8是说明机器的示例的框图,一或多个示例性实施方案可在该机器上实施、或可通过该机器控制一或多个示例性实施方案。
具体实施方式
随后的描述包括实现本发明主题的示例性实施方案的系统、方法、技术、指令序列以及计算机器程序产品。在以下的描述中,出于解释的目的,提出许多具体细节,以便提供对示例性实施方案的透彻理解。然而,对于本领域技术人员而言,显而易见的是,可在没有这些具体细节的情况下实践本发明实施方案。
本专利文件的公开内容的一部分含有受版权保护的材料。版权所有者不反对由任何人对专利文件或专利公开内容进行传真复制,因为其出现在专利及商标局的专利档案或记录中,但在任何其他方面保留所有版权。以下声明适用于如下面所述以及在形成本文件的一部分的附图中的任何数据:版权LAM Research Corporation,2018,保留所有权利。
在本公开中,使用各种术语来描述半导体处理表面:“晶片”和“衬底”可以互换地使用。经由电化学反应将金属沉积或镀敷到晶片的导电表面上的工艺可通常被称为“电沉积”或“电镀”。
晶片包括形成互连的诸如沟槽和通孔之类的特征。随着互连的尺寸缩小(例如,小于50nm的尺寸),在更窄的几何形状中的特征的金属化变得越来越困难。例如,通孔周围的“突出”之类的缺陷可能导致铜镀层夹断,并在特征中留下空隙缺陷。
为了解决上述挑战,本公开内容描述了基于直接铜电沉积到诸如钴之类的保形扩散阻挡层上的替代电镀工艺。该电镀工艺使用电沉积化学过程,从而使铜能成核并在晶片(例如300mm电阻晶片)上均匀沉积。碱性复合铜电解质浴比酸性电解液具有更好的铜成核密度和镀层均匀性。与酸性电解质相比,碱性复合铜电解质对籽晶层溶解的敏感性较低。因此,从碱性复合铜浴中在钴上直接镀敷的一个有益效果是可以最小化或消除侧壁空隙。本公开内容描述了在碱性复合铜电解质浴中的电镀工艺,其防止或最小化晶片的特征中的接缝或中心空隙的形成。
在本公开的一些示例实施方式中,提供了一种电镀工艺,该电镀工艺使用具有正向直流脉冲和反向直流脉冲的组合的碱性复合铜电解质浴。这种电镀工艺能够将铜层直接沉积在晶片特征上的钴衬里上,而不会在晶片的通孔和沟槽中造成接缝或空隙。
图1是根据示例性实施方案的电镀系统100的框图。电镀系统100包括浴槽112、诸如夹具108之类的保持设备、阳极106、直流(DC)电源104和控制器102。
浴槽112包含碱性复合铜电解质溶液114。在一示例中,碱性复合铜电解质溶液114包含铜(例如,约0.5g/L至约2.0g/L),复合配体(例如乙二胺四乙酸或EDTA)和添加剂(例如促进剂和抑制剂)。用泵(未示出)将碱性复合铜电解质溶液114连续地提供至浴槽112。碱性复合铜电解质溶液114通过泵循环进出浴槽112。
夹具108保持浸没在碱性复合铜电解质溶液114中的晶片110。在一示例中,夹具108包括安装到主轴的保持装置,该主轴使得夹具108和晶片110能旋转。
晶片110包括使用例如原子层沉积(ALD)工艺或化学气相沉积(CVD)工艺沉积有钴层的特征(通孔和沟槽)。
DC电源104产生在夹具108和阳极106之间流动的直流电流。DC电源104包括负极输出电极116和正极输出电极118。负极输出电极116电连接到夹具108和晶片110。正极输出电极118电连接到位于碱性复合铜电解质溶液114中的阳极106。阳极106位于碱性复合铜电解质溶液114中与晶片110相对的位置。
控制器102连接到DC电源104并被编程以控制DC电源104。例如,控制器102包括程序指令,该程序指令指定将与持续时间和次数一起应用于晶片110的电流和电压电平,在该持续时间和次数,电流和电压电平变化。在一示例性实施方案中,控制器102控制DC电源104以在夹具108/晶片110与阳极106之间产生正向脉冲和反向脉冲的组合。正向脉冲包括直流电流,其持续预定持续时间(例如100ms),从而导致铜从碱性复合铜电解质溶液114沉积在晶片110上。反向脉冲包括反极性的直流电流,其持续预定持续时间(例如10ms),从而导致铜从晶片110除去。
在正向脉冲期间,DC电源104将晶片110偏置为相对于阳极106具有负电位。这导致电流从阳极106流向晶片110,并且电化学还原(例如,Cu2++2e-→Cu0)在晶片表面(阴极)上进行,这导致铜沉积在晶片110的表面上。在反向脉冲期间,发生相反的情况:晶片表面上的反应是氧化(例如Cu0→Cu2++2e-),从而导致从晶片110的表面去除铜。
图2是根据示例性实施方案的用于处理晶片的方法200的流程图。方法200包括:在操作202,在晶片110上执行钴的CVD。ALD工艺使用交替剂量的前体材料沉积非常薄的钴层,所述前体材料首先使表面饱和,然后形成薄的钴层沉积物。CVD工艺涉及向室提供一种或多种气态反应物,该反应物反应以在晶片表面上沉积钴膜。尽管通常使用ALD和CVD工艺来沉积钴(或其他半贵金属)层,但也可以使用其他沉积工艺。在操作204,在高温下用氢氦等离子体对晶片110进行预处理。当暴露于大气中时,CVD沉积的钴开始形成天然氧化物,从而产生约1nm至约1.2nm的厚度。在氧化钴上镀敷铜可能具有挑战性,因为镀敷会导致侧壁空隙或不良的黏附性。高温(例如约250℃)预处理可帮助除去所有氧化物与附聚的钴。在操作206,执行氧催化和脉动介导的工艺(OCPM)。OCPM工艺的第一步是铜复合钝化层的启动和设置。高传质条件有助于实现均匀的场和特征钝化。当施加铜电镀电位时,O2还原反应会消耗特征中的可用的O2。然后进行水还原反应并增大pH。pH升高会破坏钝化膜,因此有利于Cu沉积。然后,施加短的反向脉冲以用于Cu+生成,并在现场改善钝化完整性,从而促进超保形填充。反向脉冲有助于实现某些蚀刻/剥离,从而有助于促进平滑的特征内成核特性。
在操作208中,常规的铜浴(例如,约2g/L至约40g/L)、酸(例如,约10g/L至约20g/L)和氯化物(例如,约30ppm至约100ppm)用于沉积铜覆盖层。在操作210,执行化学机械平坦化(CMP)以平坦化晶片110并去除多余的铜。
本公开还包括示例性方法。在一个示例中,参考图3,电镀方法300包括在操作302处将晶片浸没在包含电解质溶液的浴槽中。在操作304,产生正向脉冲和反向脉冲的组合。正向脉冲和反向脉冲的组合包括高对流正向脉冲、高对流反向脉冲和低对流反向脉冲的组合。在操作306,通过将正向脉冲和反向脉冲的组合施加到在电解质溶液中的晶片以及与晶片相对设置的阳极而将铜层沉积在晶片的钴层上。
在一些示例中,正向脉冲和反向脉冲的组合包括高对流正向脉冲、其后的高对流反向脉冲以及其后的低对流反向脉冲。高对流正向脉冲和高对流反向脉冲均包括至少约150rpm的对流。高对流正向脉冲包括强度为至少约0.85mA/cm2的持续至少约100ms的正向直流电流以及在正向直流电流之后的持续至少约200ms的无直流电流。高对流反向脉冲包括强度为至少约0.85mA/cm2的持续至少约100ms的正向直流电流、在正向直流电流之后的强度为至少约-0.85mA/cm2的持续至少约10ms的反向直流电流以及在反向直流电流之后的持续至少约200ms的无直流电流。所述低对流反向脉冲包括至多约20rpm的对流,其中所述低对流反向脉冲包括强度为至少约0.85mA/cm2的持续至少约100ms的正向直流电流、在正向直流电流之后的强度为至少约-0.85mA/cm2的持续至少约10ms的反向直流电流以及在反向直流电流之后持续至少约200ms的无直流电流。电解质溶液包括碱性复合铜电解质溶液。
图4是根据另一示例性实施方案的用于电镀晶片的方法400的流程图。方法400包括,在操作402处,用DC电源104产生高对流正向脉冲。在一个示例性实施方案中,DC电源104产生约0.60mA/cm2至约2.0mA/cm2的持续约100ms至约200ms的电流。然后,DC电源104关闭电流持续约200ms至约500ms。在高对流正向脉冲期间,晶片的旋转速率为约100rpm至约200rpm。
在操作404,DC电源104产生高对流反向脉冲。在一示例性实施方案中,DC电源104产生约0.60mA/cm2至约2.0mA/cm2的持续约100ms至约200ms的电流。然后,DC电源104产生约-0.60mA/cm2至约-2.0mA/cm2的持续约10ms至约20ms的持续时间的反向电流。然后,DC电源104关闭电流持续约200ms至约500ms。在高对流反向脉冲期间,晶片的旋转速率为约100rpm至约200rpm。
在操作406,DC电源104产生低对流反向脉冲。在一示例性实施方案中,DC电源104产生约0.60mA/cm2至约2.0mA/cm2的持续约100ms至约200ms的电流。然后,DC电源104产生约-0.6mA/cm2至约2.0mA/cm2的持续约10ms至约20ms的反向电流。然后,DC电源104关闭电流持续约200ms至约500ms。在低对流反向脉冲期间,晶片的旋转速率为约10rpm至约25rpm。
图5是描绘根据另一示例性实施方案的反向脉冲500的示例的图。反向脉冲500包括约0.85mA/cm2的持续约100ms的正电流、其后的约-0.85mA/cm2的持续约10ms的负电流、其后的持续约200ms的无电流。
图6示出了根据另一示例性实施方案的描绘正向脉冲602和反向脉冲604的示例的两个曲线图。正向脉冲602包括约0.85mA/cm2的持续约100ms的正电流、其后的约200ms的无电流。反向脉冲604包括约0.85mA/cm2的持续约100ms的正电流、随后的约-0.85mA/cm2的持续约10ms的负电流、随后的约200ms的无电流。
图7A-7D是在图3中描述的电镀工艺之前、期间和之后的晶片的截面图。图7A示出了在电镀工艺之前晶片701的特征的横截面。示出了钴层702沉积在通孔704上。图7B示出了在一系列正向脉冲和反向脉冲之后的晶片701的特征的横截面的示例。铜层706被示出为部分地填充通孔704的底部。图7C示出了在一系列正向脉冲和反向脉冲之后晶片701的特征的横截面的另一示例。铜层706被示出为部分填充通孔704。图7D示出了在一系列正向脉冲和反向脉冲之后晶片701的特征的横截面的另一示例。用铜层706填充通孔704,在通孔704中没有任何空隙。
因此,在一些示例中,提供了一种电镀系统,其包括:用于容纳电解质溶液的浴槽;以及用于保持浸没在电解质溶液中的晶片的保持设备,该晶片包括被钴层覆盖的特征;阳极与晶片相对设置并浸没在电解质溶液中;用于在保持设备和阳极之间产生直流电流的直流电源;以及耦合到直流电源的控制器,该控制器被配置为控制直流电源以在保持设备和阳极之间产生正向脉冲和反向脉冲的组合,并在晶片的钴层上电镀铜层。
在一些示例中,正向脉冲和反向脉冲的组合包括高对流正向脉冲、高对流反向脉冲和低对流反向脉冲。高对流正向脉冲和高对流反向脉冲均包括至少150rpm的对流。高对流正向脉冲包括强度至少为0.85mA/cm2的持续至少100ms的正向直流电流,以及在正向直流电流之后的持续至少200ms的无直流电流。高对流反向脉冲包括持续至少100ms的正向直流电流、在正向直流电流之后的持续至少10ms的反向直流电流和反向直流电流之后的持续至少200ms的无直流电流。低对流反向脉冲包括最高20rpm的对流,其中低对流反向脉冲包括强度至少为0.85mA/cm2的持续至少100ms的正向直流电流、正向直流电流之后的强度至少为-0.85mA/cm2的持续至少10ms的反向直流电流,以及反向电流之后的持续至少200ms的无直流电流。电解质溶液包括碱性复合铜电解质溶液。
在一些示例中,非瞬时机器可读介质包括指令,该指令当由机器读取时,造成该机器控制所述方法中的操作,所述操作至少包含上面所概述的非限制性示例性操作。
图8是说明机器800的示例的框图,本文所述的一或多个示例性处理实施方案可在机器800上实施,或本文所述的一或多个示例性处理实施方案可由机器800控制。在替代性实施方案中,机器800可作为独立设备操作或可连接(例如联网)至其他机器。在联网的部署中,机器800可以在服务器-客户端网络环境中以服务器机器、客户端机器或服务器机器和客户端机器两者的能力操作。在一示例中,机器800可充当点对点(P2P)(或其他分布式)网络环境中的对等机器。另外,虽然仅说明了单一机器800,但术语“机器”也应视为包括任何机器的集合,其个别地或共同地执行一组(或多组)指令以执行本文所讨论的方法中的任一者或多者,诸如经由云计算、软件即服务(SaaS)、或其他计算机集群配置进行。
如本文所述的示例可包括逻辑、多个部件或机构,或可通过逻辑、多个部件或机构操作。电路系统是在有形实体中实施的电路的集合,其包括硬件(例如简单的电路、栅极、逻辑等)。电路系统资格可随时间推移以及潜在的硬件可变性而具有灵活性。电路系统包括可在操作时单独或组合地执行指定操作的构件。在一示例中,电路系统的硬件可不变地设计成执行特定的操作(例如,硬连线)。在一示例中,电路系统的硬件可包括可变地连接的物理部件(例如,执行单元、晶体管、简单电路等),其包括经物理性(例如,磁性、电性、通过无变化群集粒子的可移动放置等)修改的计算机可读介质,以将特定操作的指令编码。在连接物理部件方面,硬件组件的潜在的电性质被改变(例如,由绝缘体改变成导体、或反之亦然)。指令使嵌入式硬件(例如,执行单元或加载机构)能够经由可变连接来建立硬件中的电路系统的构件,以在操作时执行部分特定操作。因此,当设备正操作时,计算机可读介质通信耦合至电路系统的其他部件。在一示例中,物理部件中的任何部件可用于超过一个电路系统的超过一个的构件中。例如,在操作状态下,执行单元可在一时间点用于第一电路系统的第一电路中,并在不同时间由第一电路系统中的第二电路、或由第二电路系统中的第三电路重复使用。
机器(例如计算机系统)800可包括硬件处理器802(例如中央处理单元(CPU)、硬件处理器芯、或其任何组合)、图形处理单元(GPU)803、主存储器804、及静态存储器806、这些中的一些或全部可经由互连链路(例如总线)808彼此通信。机器800还可包括显示设备810、字母数字输入设备812(例如键盘)、以及用户接口(UI)导航设备814(例如,鼠标)。在一示例中,显示设备810、字母数字输入设备812以及UI导航设备814可为触摸屏显示器。机器800可另外包括大容量储存设备(例如,驱动单元)816、信号产生设备818(例如,扬声器)、网络接口设备820、以及一或多个传感器821(诸如全球定位系统(GPS)传感器、罗盘、加速度计、或另一传感器)。机器800可包括输出控制器828,诸如串联(例如,通用序列总线(USB))、并联、或其他有线或无线(例如,红外线(IR)、近场通讯(NFC)等)连接,以与一或多个外围设备(例如,打印机、卡片阅读机等)通信或控制该一或多个外围设备。
大容量储存设备816可以包括机器可读介质822,其上储存一或多组数据结构或指令824(例如软件),该数据结构或指令824由本文所述的技术或功能中的任一者或多者体现或利用。指令824在其由机器800执行期间,也可完全或至少部分地常驻在主存储器804内、静态存储器806内、硬件处理器802内、或GPU 803内。在一示例中,硬件处理器802、GPU 803、主存储器804、静态存储器806、或大容量储存设备816中的一者或任何组合可构成机器可读介质822。
虽然机器可读介质822被作为单一介质说明,但术语“机器可读介质”可包括被构造成储存一或多个指令824的单一介质或多个介质(例如,集中式或分布式数据库、和/或相关联的高速缓存及服务器)。
术语“机器可读介质”可包括任何介质,其可储存、编码、或承载供机器800执行的指令824,并造成机器800执行本公开内容的技术的任一者或多者,或其可储存、编码、或承载由此指令824所使用或与此指令824相关联的数据结构。非限制性机器可读介质的示例可包括固态存储器、及光学与磁性介质。在一示例中,群集的机器可读介质包括具有多个颗粒的机器可读介质822,该颗粒具有不变(例如,静止)质量。因此,群集的机器可读介质不是瞬时传播信号。群集的机器可读介质的特定示例可包括非挥发性存储器,诸如半导体存储器设备(例如电可编程序只读存储器(EPROM)、电可擦写可编程只读存储器(EEPROM))及闪存设备;磁盘,诸如内部硬盘及可移动磁盘;磁光盘;以及CD-ROM和DVD-ROM盘。指令824还可经由网络接口设备820使用传输介质在通信网络826上传输或接收。。
尽管已参考特定的示例性实施方案描述实施方案,但显而易见,可在不脱离本发明的更宽广的精神及范围的情况下对这些实施方案作出各种修改和变化。因此,说明书和附图应视为说明性而非限制性意义。形成本文的一部分的附图通过说明而非限制的方式示出具体实施方案,在所述具体实施方案中可实施主题。所说明的实施方案被充分详细地描述,以使本领域技术人员能够实践本文所公开的教导。可利用其他实施方案并由其推导,使得可在不脱离本公开内容的范围的情况下作出结构和逻辑替代及改变。因此,该详细描述不应视为具有限制意义,且各种实施方案的范围仅由所附权利要求、随同这些权利要求被赋予的等同方案的完整范围所界定。
本发明主题的此类实施方案可仅为了方便而在本文中由术语“发明”单独地和/或共同地指代,且如果事实上公开超过一个发明或发明构思,则不旨在将本申请的范围自发地限制于任何单一发明或发明构思。因此,虽然已在本文说明和描述了特定实施方案,但应理解经计算来达成相同目的的任何配置可替代所示的特定实施方案。本公开内容旨在涵盖各种实施方案的所有改编或变型。在审视以上描述时,上述实施方案与未在本文具体描述的其他实施方案的组合对于本领域技术人员而言将是显而易见的。
Claims (20)
1.一种电镀系统,其包括:
用于容纳电解质溶液的浴槽;
保持设备,其用于保持浸没在所述电解质溶液中的晶片,所述晶片包括被钴层覆盖的特征;
阳极,其与所述晶片相对设置并且浸没在所述电解质溶液中;
直流电源,其用于在所述保持设备和所述阳极之间产生直流电流;和
在所述保持设备和所述阳极之间施加所述直流电流的正向脉冲和反向脉冲的组合,以在所述晶片的所述钴层上电镀铜层。
2.根据权利要求1所述的电镀系统,其中,所述正向脉冲和反向脉冲的组合包括高对流正向脉冲、高对流反向脉冲和低对流反向脉冲。
3.根据权利要求2所述的电镀系统,其中,所述高对流正向脉冲和所述高对流反向脉冲均包括至少150rpm的对流。
4.根据权利要求3所述的电镀系统,其中,所述高对流正向脉冲包括强度为至少0.85mA/cm2的持续至少100ms的正向直流电流和在所述正向直流电流之后的持续至少200ms的无直流电流。
5.根据权利要求3所述的电镀系统,其中,所述高对流反向脉冲包括持续至少100ms的正向直流电流、在所述正向直流电流之后的持续至少10ms的反向直流电流以及在所述反向直流电流之后的持续至少200ms的无直流电流。
6.根据权利要求2所述的电镀系统,其中,所述低对流反向脉冲包括最多20rpm的对流,其中,所述低对流反向脉冲包括强度为至少0.85mA/cm2的持续至少100ms的正向直流电流、在所述正向直流电流之后的强度至少为-0.85mA/cm2的持续至少10ms的反向直流电流以及在所述反向直流电流之后的持续至少200ms的无直流电流。
7.根据权利要求1所述的电镀系统,其中,所述电解质溶液包括碱性复合铜电解质溶液。
8.一种用于电镀晶片的方法,该方法包括:
将所述晶片浸没在含有电解质溶液的浴槽中;
产生正向脉冲和反向脉冲的组合,所述正向脉冲和反向脉冲的组合包括高对流正向脉冲、高对流反向脉冲和低对流反向脉冲;以及
通过向在所述电解质溶液中的所述晶片以及与所述晶片相对设置的阳极施加所述正向脉冲和反向脉冲的组合,将铜层沉积在所述晶片的钴层上。
9.根据权利要求8所述的方法,其中,所述正向脉冲和反向脉冲的组合包括高对流正向脉冲、其后的所述高对流反向脉冲、其后的所述低对流反向脉冲。
10.根据权利要求9所述的方法,其中,所述高对流正向脉冲和所述高对流反向脉冲均包括至少150rpm的对流。
11.根据权利要求10所述的方法,其中,所述高对流正向脉冲包括强度为至少0.85mA/cm2的持续至少100ms的正向直流电流和在所述正向直流电流之后的持续至少200ms的无直流电流。
12.根据权利要求10所述的方法,其中,所述高对流反向脉冲包括强度为至少0.85mA/cm2的持续至少100ms的正向直流电流、在所述正向直流电流之后的强度为至少-0.85mA/cm2的持续至少10ms的反向直流电流以及在所述反向直流电流之后的持续至少200ms的无直流电流。
13.根据权利要求9所述的方法,其中,所述低对流反向脉冲包括最多20rpm的对流,其中,所述低对流反向脉冲包括强度为至少0.85mA/cm2的持续至少100ms的正向直流电流、在所述正向直流电流之后的强度至少为-0.85mA/cm2的持续至少10ms的反向直流电流以及在所述反向直流电流之后的持续至少200ms的无直流电流。
14.根据权利要求8所述的方法,其中,所述电解质溶液包括碱性复合铜电解质溶液。
15.一种方法,其包括:
提供上面具有钴层的半导体晶片;以及
通过向浸没在电解质溶液中的半导体晶片施加正向直流脉冲和反向直流脉冲的组合,使用电镀工艺在所述钴层上沉积铜层。
16.根据权利要求15所述的方法,其中,所述正向直流脉冲和反向直流脉冲的组合包括一系列的高对流正向脉冲、高对流反向脉冲和低对流反向脉冲。
17.根据权利要求16所述的方法,其中,所述高对流正向脉冲包括至少150rpm的对流,其中,所述高对流正向脉冲包括强度为至少0.85mA/cm2的持续至少100ms的正向直流电流和在所述正向直流电流之后的持续至少200ms的无直流电流。
18.根据权利要求16所述的方法,其中,所述高对流反向脉冲包括至少150rpm的对流,其中,所述高对流反向脉冲包括强度为至少0.85mA/cm2的持续至少100ms的正向直流电流、在所述正向直流电流之后的强度为至少-0.85mA/cm2的持续至少10ms的反向直流电流以及在所述反向直流电流之后的持续至少200ms的无直流电流。
19.根据权利要求16所述的方法,其中,所述低对流反向脉冲包括最多20rpm的对流,其中,所述低对流反向脉冲包括强度为至少0.85mA/cm2的持续至少100ms的正向直流电流、在所述正向直流电流之后的强度至少为-0.85mA/cm2的持续至少10ms的反向直流电流以及在所述反向直流电流之后的持续至少200ms的无直流电流。
20.一种包含指令的机器可读介质,所述指令在被机器读取时使所述机器控制电镀方法中的操作,所述电镀方法至少包括:
将晶片浸没在含有电解质溶液的浴槽中;
产生正向脉冲和反向脉冲的组合,所述正向脉冲和反向脉冲的组合包括高对流正向脉冲、高对流反向脉冲和低对流反向脉冲;以及
通过向在所述电解质溶液中的所述晶片以及与所述晶片相对设置的阳极施加所述正向脉冲和反向脉冲的组合,将铜层沉积在所述晶片的钴层上。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/941,258 US10648097B2 (en) | 2018-03-30 | 2018-03-30 | Copper electrodeposition on cobalt lined features |
US15/941,258 | 2018-03-30 | ||
PCT/US2019/024722 WO2019191523A1 (en) | 2018-03-30 | 2019-03-29 | Copper electrodeposition on cobalt lined features |
Publications (2)
Publication Number | Publication Date |
---|---|
CN111936673A true CN111936673A (zh) | 2020-11-13 |
CN111936673B CN111936673B (zh) | 2023-12-08 |
Family
ID=68056838
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201980024132.9A Active CN111936673B (zh) | 2018-03-30 | 2019-03-29 | 内衬钴的特征上的铜电沉积 |
Country Status (4)
Country | Link |
---|---|
US (2) | US10648097B2 (zh) |
KR (1) | KR20200128186A (zh) |
CN (1) | CN111936673B (zh) |
WO (1) | WO2019191523A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11168407B2 (en) | 2018-03-30 | 2021-11-09 | Lam Research Comporation | Copper electrodeposition on cobalt lined features |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3754052A1 (en) * | 2019-06-21 | 2020-12-23 | Infineon Technologies AG | Roughening of a metallization layer on a semiconductor wafer |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6440289B1 (en) * | 1999-04-02 | 2002-08-27 | Advanced Micro Devices, Inc. | Method for improving seed layer electroplating for semiconductor |
US20060054505A1 (en) * | 2004-09-16 | 2006-03-16 | Herdman Roderick D | Controlling the hardness of electrodeposited copper coatings by variation of current profile |
US20070125657A1 (en) * | 2003-07-08 | 2007-06-07 | Zhi-Wen Sun | Method of direct plating of copper on a substrate structure |
US20090250352A1 (en) * | 2008-04-04 | 2009-10-08 | Emat Technology, Llc | Methods for electroplating copper |
US7964506B1 (en) * | 2008-03-06 | 2011-06-21 | Novellus Systems, Inc. | Two step copper electroplating process with anneal for uniform across wafer deposition and void free filling on ruthenium coated wafers |
CN102449742A (zh) * | 2009-05-27 | 2012-05-09 | 诺发系统有限公司 | 用于在薄籽晶层上进行电镀的脉冲序列 |
CN102732924A (zh) * | 2011-04-04 | 2012-10-17 | 诺发系统有限公司 | 用于定制的均匀性分布的电镀设备 |
CN103114319A (zh) * | 2011-11-17 | 2013-05-22 | 盛美半导体设备(上海)有限公司 | 用于半导体硅片上深孔均匀金属互连的方法与装置 |
US20150299886A1 (en) * | 2014-04-18 | 2015-10-22 | Lam Research Corporation | Method and apparatus for preparing a substrate with a semi-noble metal layer |
CN105027265A (zh) * | 2013-03-15 | 2015-11-04 | 应用材料公司 | 用于半导体晶片的电化学沉积工艺 |
US20160258077A1 (en) * | 2013-10-22 | 2016-09-08 | Atotech Deutschland Gmbh | Copper electroplating method |
CN106609384A (zh) * | 2015-10-27 | 2017-05-03 | 罗门哈斯电子材料有限责任公司 | 从酸性铜电镀浴液向衬底上的通孔中电镀铜的方法 |
CN107109677A (zh) * | 2014-12-05 | 2017-08-29 | 埃托特克德国有限公司 | 用来在衬底上电镀金属的方法及设备 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9385035B2 (en) * | 2010-05-24 | 2016-07-05 | Novellus Systems, Inc. | Current ramping and current pulsing entry of substrates for electroplating |
US10648097B2 (en) | 2018-03-30 | 2020-05-12 | Lam Research Corporation | Copper electrodeposition on cobalt lined features |
-
2018
- 2018-03-30 US US15/941,258 patent/US10648097B2/en active Active
-
2019
- 2019-03-29 WO PCT/US2019/024722 patent/WO2019191523A1/en active Application Filing
- 2019-03-29 KR KR1020207031393A patent/KR20200128186A/ko not_active Application Discontinuation
- 2019-03-29 CN CN201980024132.9A patent/CN111936673B/zh active Active
-
2020
- 2020-02-06 US US16/784,232 patent/US11168407B2/en active Active
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6440289B1 (en) * | 1999-04-02 | 2002-08-27 | Advanced Micro Devices, Inc. | Method for improving seed layer electroplating for semiconductor |
US20070125657A1 (en) * | 2003-07-08 | 2007-06-07 | Zhi-Wen Sun | Method of direct plating of copper on a substrate structure |
US20060054505A1 (en) * | 2004-09-16 | 2006-03-16 | Herdman Roderick D | Controlling the hardness of electrodeposited copper coatings by variation of current profile |
US7964506B1 (en) * | 2008-03-06 | 2011-06-21 | Novellus Systems, Inc. | Two step copper electroplating process with anneal for uniform across wafer deposition and void free filling on ruthenium coated wafers |
US20090250352A1 (en) * | 2008-04-04 | 2009-10-08 | Emat Technology, Llc | Methods for electroplating copper |
CN102449742A (zh) * | 2009-05-27 | 2012-05-09 | 诺发系统有限公司 | 用于在薄籽晶层上进行电镀的脉冲序列 |
CN102732924A (zh) * | 2011-04-04 | 2012-10-17 | 诺发系统有限公司 | 用于定制的均匀性分布的电镀设备 |
CN103114319A (zh) * | 2011-11-17 | 2013-05-22 | 盛美半导体设备(上海)有限公司 | 用于半导体硅片上深孔均匀金属互连的方法与装置 |
CN105027265A (zh) * | 2013-03-15 | 2015-11-04 | 应用材料公司 | 用于半导体晶片的电化学沉积工艺 |
US20160258077A1 (en) * | 2013-10-22 | 2016-09-08 | Atotech Deutschland Gmbh | Copper electroplating method |
US20150299886A1 (en) * | 2014-04-18 | 2015-10-22 | Lam Research Corporation | Method and apparatus for preparing a substrate with a semi-noble metal layer |
CN107109677A (zh) * | 2014-12-05 | 2017-08-29 | 埃托特克德国有限公司 | 用来在衬底上电镀金属的方法及设备 |
CN106609384A (zh) * | 2015-10-27 | 2017-05-03 | 罗门哈斯电子材料有限责任公司 | 从酸性铜电镀浴液向衬底上的通孔中电镀铜的方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11168407B2 (en) | 2018-03-30 | 2021-11-09 | Lam Research Comporation | Copper electrodeposition on cobalt lined features |
Also Published As
Publication number | Publication date |
---|---|
US10648097B2 (en) | 2020-05-12 |
KR20200128186A (ko) | 2020-11-11 |
US20200255964A1 (en) | 2020-08-13 |
US11168407B2 (en) | 2021-11-09 |
US20190301040A1 (en) | 2019-10-03 |
CN111936673B (zh) | 2023-12-08 |
WO2019191523A1 (en) | 2019-10-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20230298894A1 (en) | Copper electrodeposition sequence for the filling of cobalt lined features | |
US7189146B2 (en) | Method for reduction of defects in wet processed layers | |
US7964506B1 (en) | Two step copper electroplating process with anneal for uniform across wafer deposition and void free filling on ruthenium coated wafers | |
US10774438B2 (en) | Monitoring electrolytes during electroplating | |
US8168540B1 (en) | Methods and apparatus for depositing copper on tungsten | |
US20150140814A1 (en) | Alkaline pretreatment for electroplating | |
CN111936673B (zh) | 内衬钴的特征上的铜电沉积 | |
KR20230026331A (ko) | 나노쌍정된 (nanotwinned) 구리 피처 및 비나노쌍정 (non-nanotwinned) 구리 피처의 전기도금 | |
US20220415710A1 (en) | Interconnect structure with selective electroplated via fill | |
JP2008088498A (ja) | 電気めっき方法 | |
US11603602B2 (en) | Method for controlling electrochemical deposition to avoid defects in interconnect structures | |
KR20220159469A (ko) | 레벨링 화합물 제어 | |
US11598016B2 (en) | Electrochemical plating system and method of using | |
Basol | Advanced Planarization Techniques | |
Datta | Electrochemical processing tools for advanced copper interconnects: an introduction |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |