CN111931449A - Analysis method of layout graph density - Google Patents
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- 238000004519 manufacturing process Methods 0.000 abstract description 17
- 230000005856 abnormality Effects 0.000 abstract description 13
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- 210000000078 claw Anatomy 0.000 description 2
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- 238000005530 etching Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
The invention provides a method for analyzing layout graph density, which comprises the following steps: dividing the layout into a plurality of grids, calculating a first local graph density of each grid, and judging whether the first local graph density exceeds a first specification; if the first local pattern density does not exceed the first specification, judging whether the first local pattern density exceeds a second specification; if the grid exceeds the preset range, marking the grid as 1, otherwise marking the grid as 0, and collecting to obtain a first density matrix; copying a plurality of first density matrixes to form a second density matrix; when the wafer is produced, if the wafer is abnormal, marking the grid corresponding to the abnormal part as 1, otherwise marking the grid as 0 to form a third density matrix; and sequentially obtaining the product of the numerical values of all the grids in the second density matrix and the numerical value of the third density matrix, wherein if the product is 1, the local graph density of the corresponding grid does not reach the standard. The wafer yield in subsequent production can be improved by considering the abnormality of the wafer and the machine in the analysis of the graph density of the layout.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a layout graph density analysis method.
Background
With the development of integrated circuit technology, layout patterns become more and more complex, and pattern density analysis becomes an important step of data analysis of many critical-level reticles. In the semiconductor manufacturing process, whether the pattern density distribution is uniform or not greatly affects the etching process and the chemical mechanical polishing process, and in the case of non-uniform pattern density distribution, not only is the load effect in etching easily increased, but also the final dimension of a part of the pattern is deviated from the target dimension, and the pattern is more easily over-polished in the chemical mechanical polishing process. Therefore, the pattern density is accurately calculated, the high-risk process area is found, engineers can know the specific position and the pattern characteristics of the high-risk process hotspot of the product in time, corresponding countermeasures are made as soon as possible, and the flow sheet and the mass production of the product are smoothly achieved.
In the traditional pattern density analysis, the pattern density of the layout of the current layer is checked according to the data of the layout, namely the ch ip, but in the actual production, the effect of a production machine on the wafer is not considered, and only the layout pattern density analysis of the ch ip data can miss some influences on the whole wafer. For example, wafer edge is more susceptible to defocus for photolithography, and pattern density differences in wafer edge are more sensitive to process. For example, the position of the mechanical claw of the film deposition machine is fixed, the thickness of the film deposited on the wafer is different from the position of the middle of the wafer, and the influence of the pattern density difference on the claw part is also different from the position of the middle of the wafer. If only density analysis of layout data is performed, and the layout data is managed and controlled by the same spec, a loss is inevitably caused.
Disclosure of Invention
The invention aims to provide a layout graph density analysis method, which considers the abnormality during wafer production into layout design, analyzes the layout graph, and designs a layout capable of indirectly improving the abnormality during wafer production, thereby improving the yield of wafers during subsequent production.
In order to achieve the above object, the present invention provides a layout graph density analysis method, including:
dividing a layout into a plurality of grids, calculating a first local graph density of each grid, and judging whether the first local graph density exceeds a first specification;
if the first local graph density does not exceed the first specification, judging whether the first local graph density exceeds a second specification;
if the second specification is exceeded, marking the grid as 1, otherwise marking the grid as 0;
collecting a plurality of marks to obtain a first density matrix;
replicating a plurality of the first density matrices to form a second density matrix;
when a wafer is produced, if the wafer is abnormal, marking grids on a layout corresponding to the abnormal part of the wafer as 1, if the wafer is not abnormal, marking grids on the corresponding layout as 0, and collecting the marks of a plurality of grids to form a third density matrix;
and sequentially obtaining the product of the numerical values of all the grids in the second density matrix and the numerical value of the third density matrix, wherein if the product is 1, the local graph density of the corresponding grid does not reach the standard.
Optionally, in the analysis method of the layout pattern density, if the first local pattern density exceeds a first specification, an alarm process is performed.
Optionally, in the analysis method of layout graph density, the first specification has a first upper limit and a first lower limit, the second specification has a second upper limit and a second lower limit, a value of the second upper limit is smaller than a value of the first upper limit, and a value of the second lower limit is larger than a value of the first lower limit.
Optionally, in the analysis method of the layout graph density, the value of the second upper limit is less than 5% to 15% of the value of the first upper limit; the second lower limit is greater than the first lower limit by 5% to 15%.
Optionally, in the analysis method of the layout graph density, the first density matrix, the second density matrix and the third density matrix are all rectangular matrices or square matrices.
Optionally, in the analysis method of layout pattern density, n first density matrix combinations are copied to form a second density matrix, where n is the number of crystal grains formed on one wafer.
Optionally, in the analysis method of the layout graph density, the number of rows of the second density matrix is the same as the number of rows of the third density matrix; the number of columns of the second density matrix is the same as the number of columns of the third density matrix.
Optionally, in the analysis method for the density of the layout graph, the position of the mark of the same grid in the second density matrix is the same as the position of the mark of the same grid in the third density matrix.
Optionally, in the analysis method for the layout graph density, the product of the numerical values of all the grids in the second density matrix and the numerical values of all the grids in the third density matrix is sequentially obtained, and if the product is 0, the corresponding local graph density of the grids reaches the standard.
Optionally, in the analysis method for the density of the layout graph, when the density of the local graph of the grid does not reach the standard, alarm processing is performed.
According to the method for analyzing the pattern density of the layout, provided by the invention, the abnormity of the wafer and the machine during wafer production is considered in the analysis of the pattern density of the layout, so that the manufacturability of the layout is improved from the aspect of layout design, and the accuracy of product prediction is improved from the aspect of process, thereby improving the yield of the wafer during subsequent production.
Drawings
FIG. 1 is a flow chart of a method for analyzing layout pattern density according to an embodiment of the present invention;
FIG. 2 is a method for dividing grids on a layout of a layout according to an embodiment of the present invention;
FIG. 3 is a schematic illustration of a first density matrix of an embodiment of the invention;
FIG. 4 is a schematic illustration of a second density matrix of an embodiment of the present invention;
FIG. 5 is a schematic illustration of a third density matrix of an embodiment of the present invention;
FIG. 6 is a schematic illustration of a fourth density matrix of an embodiment of the present invention;
in the figure: 100-layout, 110-grid, 200-first density matrix, 300-second density matrix, 400-third density matrix, and 500-fourth density matrix.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. Advantages and features of the present invention will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the following, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
The invention provides a method for analyzing layout graph density, which comprises the following steps:
s11: dividing a layout into a plurality of grids, calculating a first local graph density of each grid, and judging whether the first local graph density exceeds a first specification;
s12: if the first local graph density does not exceed the first specification, judging whether the first local graph density exceeds a second specification;
s13: if the second specification is exceeded, marking the grid as 1, otherwise marking the grid as 0;
s14: collecting a plurality of marks to obtain a first density matrix;
s15: replicating a plurality of the first density matrices to form a second density matrix;
s16: when a wafer is produced, if the wafer is abnormal, marking grids on a layout corresponding to the abnormal part of the wafer as 1, if the wafer is not abnormal, marking grids on the corresponding layout as 0, and collecting the marks of a plurality of grids to form a third density matrix;
s17: and sequentially obtaining the product of the numerical values of all the grids in the second density matrix and the numerical value of the third density matrix, wherein if the product is 1, the local graph density of the corresponding grid does not reach the standard.
Specifically, in step S11, the layout of the wafer is first divided into a plurality of grids, for example, fig. 2, the entire layout is divided into a plurality of grids, and the local density of the layout pattern may be obtained in a manner of obtaining the pattern density of each grid. The specific division into how many grids the inventor determines according to the actual situation. The method for calculating the pattern density in each grid is the prior art and is not described herein. And when the first local graph density in a certain grid exceeds a first specification, performing alarm processing. The inventors can then process this layout for pattern density anomalies.
Where the first specification is a number set by the inventor, it may be a range having an upper limit and a lower limit, and the first pattern density may be considered to be beyond the first specification regardless of whether the first pattern density is higher than the upper limit or lower than the lower limit.
In step S11, the possible local density anomalies of the layout pattern are preliminarily processed, and some anomalies may exist. Next, step S12 is performed, and in step S12, the specification for determining the local density of the pattern is tightened, and the second specification also has a second upper limit and a second lower limit, the second upper limit having a value smaller than the first upper limit, and the second lower limit having a value larger than the first lower limit. That is, the requirement of the second specification is stricter than that of the first specification, and specifically, the value of the second upper limit is less than 5% to 15% of that of the first upper limit; the second lower limit is greater than the first lower limit by 5% to 15%. The value of the upper and lower limits may be determined by the inventors in accordance with a particular invention or production scenario.
Then, step S13 is performed, if the grid of the first local pattern density exceeding the second specification is marked as 1, otherwise, the grid is marked as 0, and a first density matrix is obtained by collecting the marks of the grids, where the first density matrix may be a rectangular matrix or a square matrix. Specifically, as shown in fig. 2, the layout is divided into a plurality of grids, the division is only a schematic diagram, and the number of the specific grids may be different. Then, sequentially calculating the density of the layout patterns in the grid from the first grid, if the density of the first local pattern exceeds the grid of the second specification, marking the grid as 1, otherwise marking the grid as 0, and sequentially filling the obtained 1 or 0 into a matrix to form a first density matrix, as shown in fig. 3, it can be seen that three elements in the first density matrix 200 have values of 1, which indicates that the layout has 3 local densities exceeding the second specification.
Next, step S14 is performed to copy a plurality of the first density matrices 200 to form a second density matrix 300. Specifically, n first density matrix combinations are copied to form a second density matrix, wherein n is the number of crystal grains formed on one wafer. The number of the first density matrices 200 is the number of dies on the wafer, the second density matrix is the set of the first density matrices 200 for all dies on the wafer, and each wafer has a plurality of identical dies, so that the plurality of first density matrices 200 can be directly duplicated to form the second density matrix 300. The specific number is determined according to the actual production condition. The embodiment of the present invention uses 16, but the embodiment is only used for convenience of illustration and is not limited. The second density matrix 300 may be a rectangular matrix or a square matrix.
Then, step S15 is performed, when a wafer is produced, if an abnormality occurs in the wafer, for example, an abnormality caused by a machine or manufacturing process, and if the abnormality is not processed in advance, a lot of wafer abnormalities may be caused, the grid on the layout corresponding to the abnormal portion of the wafer is marked as 1, otherwise, the grid is marked as 0, and a plurality of marks of the grid are collected to form a third density matrix. Because the machine and the process are relatively fixed, the abnormality of the wafer caused by the machine or the process or the wafer in the production is combined with the inspection of the graph of the layout, and the abnormality can amplify the abnormality in the graph of the layout. For example, when the pattern of the layout is inspected, the size of some places may be slightly small but not exceed the specification, however, if the places are just abnormal areas of the machine or the wafer process, the places may exceed the specification and become defective products. The embodiment of the invention can detect the places which can not be detected by the prior art and can be abnormal after actual production. On the other hand, the wafer abnormality caused by the machine or the wafer process may be a large area, and actually, the area is not always a bad area, so that a lot of time and energy are wasted when the area is directly used as the bad area for processing. Finally, the extracted abnormality is reflected to a process engineer in the post-processing procedure so as to improve a process machine, thereby improving the yield of the subsequent wafer production.
The grids of the layouts of the same batch of wafers are divided in the same manner, and the number of values included in the second density matrix 300 is the same as the number of values included in the third density matrix 400. The number of rows of the second density matrix 300 is the same as the number of rows of the third density matrix 400; the number of columns of the second density matrix 300 is the same as the number of columns of the third density matrix 400. Likewise, each grid is located in the same position in the second density matrix 300 and the third density matrix 400.
Then, step S16 is performed to sequentially obtain the product of the values of the second density matrix 300 and the values of the third density matrix 400 for all the grids, and if the product is 1, the local pattern density of the corresponding grid does not meet the standard. And if the product is 1, the density of the corresponding local graph of the grid reaches the standard. And (5) alarming when the local graph density of the grid does not reach the standard. A specific example of this step may be that, a value corresponding to a grid in the second density matrix 300 is multiplied by a value corresponding to a grid in the third density matrix 400, and all the calculated values are obtained in sequence, and the values of the products are filled into the matrices respectively to form a fourth density matrix 500, for example, the first value of the second density matrix 300 is 0, the first value of the third density matrix 400 is also 0, and the value obtained by multiplying the two values is also 0 as the first value of the fourth density matrix 500, and the values of the fifth row and the fifteenth column in the second density matrix 300 are 1, and the values of the fifth row and the fifteenth column in the third density matrix 400 are 1, so that the values obtained by multiplying the two values are 1, and the values obtained by multiplying the fifth row and the fifteenth column in the fourth density matrix 500 are obtained in sequence. Finally, it is very convenient to find out which grid corresponds to the value 1, which grid corresponds to the value 0, 1 is that the density of the layout graph of the grid does not reach the standard, and 0 is that the density of the layout graph of the grid reaches the standard directly from the fourth density matrix 500, so that the method can easily and obviously find out which grids do not reach the standard from the fourth density matrix 500.
In summary, in the method for analyzing the pattern density of the layout provided in the embodiment of the present invention, when the wafer is produced, the abnormality of the wafer and the machine is considered in the analysis of the pattern density of the layout, and therefore, the manufacturability of the layout is improved from the aspect of layout design, and the accuracy of product prediction is improved from the aspect of process, so that the yield of the wafer during subsequent production is improved.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method for analyzing layout graph density is characterized by comprising the following steps:
dividing a layout into a plurality of grids, calculating a first local graph density of each grid, and judging whether the first local graph density exceeds a first specification;
if the first local graph density does not exceed the first specification, judging whether the first local graph density exceeds a second specification;
if the second specification is exceeded, marking the grid as 1, otherwise marking the grid as 0;
collecting a plurality of marks to obtain a first density matrix;
replicating a plurality of the first density matrices to form a second density matrix;
when a wafer is produced, if the wafer is abnormal, marking grids on a layout corresponding to the abnormal part of the wafer as 1, if the wafer is not abnormal, marking grids on the corresponding layout as 0, and collecting the marks of a plurality of grids to form a third density matrix;
and sequentially obtaining the product of the numerical values of all the grids in the second density matrix and the numerical value of the third density matrix, wherein if the product is 1, the local graph density of the corresponding grid does not reach the standard.
2. The method for analyzing layout pattern density according to claim 1, wherein an alarm process is performed if the first local pattern density exceeds a first specification.
3. The method for analyzing layout pattern density according to claim 1, wherein the first specification has a first upper limit and a first lower limit, the second specification has a second upper limit and a second lower limit, the value of the second upper limit is smaller than the value of the first upper limit, and the value of the second lower limit is larger than the value of the first lower limit.
4. The method for analyzing layout pattern density according to claim 3, wherein the value of the second upper limit is less than 5% -15% of the value of the first upper limit; the second lower limit is greater than the first lower limit by 5% to 15%.
5. The method for analyzing the density of layout graphics as claimed in claim 1, wherein the first density matrix, the second density matrix and the third density matrix are all rectangular matrices or square matrices.
6. The method for analyzing layout pattern density of claim 1, wherein n combinations of the first density matrices are duplicated to form a second density matrix, where n is the number of dies formed on one wafer.
7. The method for analyzing layout pattern density according to claim 1, wherein the number of rows of the second density matrix is the same as the number of rows of the third density matrix; the number of columns of the second density matrix is the same as the number of columns of the third density matrix.
8. The method for analyzing layout pattern density according to claim 7, wherein the position of the mark of the same grid in the second density matrix is the same as the position of the mark in the third density matrix.
9. The method for analyzing layout pattern density according to claim 1, wherein the product of the numerical values of all the grids in the second density matrix and the numerical values of all the grids in the third density matrix is obtained in sequence, and if the product is 0, the corresponding local pattern density of the grids reaches the standard.
10. The method for analyzing layout pattern density according to claim 1, wherein an alarm process is performed when the local pattern density of the grid does not meet a criterion.
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