CN116342557A - Method for detecting pattern defects of semiconductor process - Google Patents

Method for detecting pattern defects of semiconductor process Download PDF

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Publication number
CN116342557A
CN116342557A CN202310333354.7A CN202310333354A CN116342557A CN 116342557 A CN116342557 A CN 116342557A CN 202310333354 A CN202310333354 A CN 202310333354A CN 116342557 A CN116342557 A CN 116342557A
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hot spot
defects
areas
risk
high risk
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曹云
顾晓芳
魏芳
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/0002—Inspection of images, e.g. flaw detection
    • G06T7/0004—Industrial image inspection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/60—Analysis of geometric attributes
    • G06T7/62—Analysis of geometric attributes of area, perimeter, diameter or volume
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30108—Industrial image inspection
    • G06T2207/30148—Semiconductor; IC; Wafer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/30—Computing systems specially adapted for manufacturing

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Geometry (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

The invention provides a method for detecting defects of a semiconductor process pattern, which predicts products through a virtual process model to obtain a high-risk hot spot distribution diagram of each process, improves the sensitivity of a high-risk area by setting scanning program parameters of different areas, optimizes a defect scanning program and a defect spot inspection mode, solves the problem of missing report of systematic defects of part of the process, improves the speed of finding online process defects of the products, improves the comprehensiveness and timeliness of online defect monitoring, optimizes the process in time and improves the yield.

Description

Method for detecting pattern defects of semiconductor process
Technical Field
The invention belongs to the field of integrated circuit manufacturing, and particularly relates to a method for detecting defects of a semiconductor process pattern.
Background
Advanced integrated circuit manufacturing processes generally comprise hundreds of steps, and minor errors in any link can lead to failure of the entire chip, particularly as the critical dimensions of the circuit are reduced, the more stringent the process control requirements. In order to ensure the stability of the yield, the wafer is subjected to defect scanning after the process, so that various machine stations and abnormal process weaknesses in the production process can be effectively found in time, and the quick adjustment of the machine stations and the optimization of the process are important links for ensuring the quality of products.
In the existing semiconductor manufacturing process, a defect scanning program is established after each process step to scan the wafer, and the defect scanning program simply divides different areas (such as an ASRAM area, a logic area and the like) according to the function of the chip and sets different program parameters according to the function mark level, so that most defects caused by grasping process fluctuation are ensured. However, with the continuous shrinking of the critical dimensions, part of the patterns with poor process design friendliness are difficult to grasp due to systematic defects caused by process fluctuation, and the part of defects can often cause the loss of product yield.
Disclosure of Invention
The invention aims to provide a method for detecting defects of a semiconductor process pattern, so as to optimize a defect scanning program, solve the problem of partial systematic defect reporting, optimize the process in time and improve the yield.
In order to achieve the above object, the present invention provides a method for detecting defects of a semiconductor process pattern, comprising:
establishing a corresponding virtual process model based on each process characteristic, and defining the type and specification of each corresponding process manufacturability hot spot;
invoking a virtual process model to predict a product layout and running hot spot specifications to obtain a distribution diagram of each process high risk hot spot of the product layout;
expanding the high-risk hot spot positions to obtain expansion areas of the high-risk hot spots, and merging the expansion areas with the overlapped areas to obtain high-risk areas;
and importing the coordinate information set of the high-risk area into a defect scanning machine terminal, and establishing a scanning program according to the coordinate information set division area to scan the wafer.
In an optional embodiment of the present invention, the sensitivity of the scanning program corresponding to the high risk area is higher than that of the scanning program corresponding to other areas of the product layout.
In an alternative embodiment of the present invention, the wafer scanning by the scanning program further includes:
and performing the selective inspection of the defects on the scanned wafer, and performing defect analysis on the selective inspection result of the defects.
In an optional embodiment of the present invention, the proportion of the selective examination of the defects in the high risk area is higher than that in other areas of the product layout, and the selective examination result of the high risk area is preferentially analyzed for defects.
In an alternative embodiment of the present invention, further comprising: and (5) optimizing the process according to the defect analysis result.
In an alternative embodiment of the invention, the high risk hotspot location extension comprises: taking the center of the high-risk hot spot position as an origin, and expanding outwards by a set expansion size; the extension size ranges from 4um to 2mm.
In an alternative embodiment of the invention, the extension size is 10um.
In an alternative embodiment of the invention, the high risk hot spot location expansion includes expanding outwardly along a square.
In an optional embodiment of the present invention, the virtual process model is based on a stable process platform, and a photomask is designed to perform film-casting to obtain mapping relations between different layout designs and processes;
the virtual process model comprises a photoetching process window model and a chemical mechanical polishing model.
In an alternative embodiment of the present invention, further comprising: combining the expansion areas without the overlapping areas to obtain a secondary high risk area, wherein the sensitivity of the scanning program corresponding to the secondary high risk area is higher than that of the scanning program corresponding to other areas of the product layout except the high risk area.
In summary, the invention provides a method for detecting defects of a semiconductor process pattern, which predicts products through a virtual process model to obtain a high-risk hot spot distribution diagram of each process, improves the sensitivity of a high-risk area by setting scanning program parameters of different areas, optimizes a defect scanning program and a defect spot inspection mode, solves the problem of missing report of systematic defects of part of the processes, improves the speed of finding online process defects of the products, improves the comprehensiveness and timeliness of online defect monitoring, optimizes the process in time, and improves the yield.
Drawings
FIG. 1 is a flow chart of a method for detecting defects in a semiconductor process pattern according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a high risk area division in a method for detecting defects in a semiconductor process pattern according to an embodiment of the present invention.
Wherein, the reference numerals are as follows:
10-exposure unit, 100-hot spot, 110-expansion area of high risk hot spot, 120-high risk area.
Detailed Description
In order to make the contents of the present invention more clear and understandable, the contents of the present invention will be further described with reference to the accompanying drawings. Of course, the invention is not limited to this particular embodiment, and common alternatives known to those skilled in the art are also encompassed within the scope of the invention.
In the following description, the present invention will be described in detail with reference to the drawings, which are not to be construed as limiting the invention, for the purpose of illustration and not as an actual scale.
For ease of description, some embodiments of the invention may use spatially relative terms such as "above" …, "" below "…," "top," "below," and the like to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures of the embodiments. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or components described as "below" or "beneath" other elements or components would then be oriented "above" or "over" the other elements or components. The terms "first," "second," and the like, herein below, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
Fig. 1 is a flowchart of a method for detecting defects of a semiconductor process pattern according to an embodiment of the present invention. Referring to fig. 1, the method for detecting defects of a semiconductor process pattern according to the present embodiment includes:
step S01: establishing a corresponding virtual process model based on each process characteristic, and defining the type and specification of each corresponding process manufacturability hot spot;
step S02: calling a process model to predict a product layout and running hot spot specifications to obtain a distribution diagram of each process high risk hot spot of the product layout;
step S03: expanding the high-risk hot spot positions to obtain expansion areas of the high-risk hot spots, and merging the expansion areas with the overlapped areas to obtain high-risk areas;
step S04: and importing the coordinate information set of the high-risk area into a defect scanning machine terminal, and establishing a scanning program according to the coordinate information set dividing area.
Specifically, first, step S01 is executed, a corresponding virtual process model is established based on each process feature, and the type and specification of each corresponding manufacturability hot spot are defined. The virtual process Model (VMP Model)) is based on a stable process platform, and a photomask is designed to conduct flow sheet to obtain mapping relations between different layout designs and processes. In this embodiment, the dummy process model may be a photolithography process window model, a Chemical Mechanical Polishing (CMP) model, but is not limited thereto. Accordingly, manufacturability hot spots may illustrate photolithography process hot spots/etching process hot spots, CMP process hot spots, and the like.
And then, executing step S02, calling a virtual process model to predict the product layout, and operating the hot spot specification to obtain a distribution diagram of each process high risk hot spot of the product layout. The high-risk hot spot is obtained by predicting a customer product through a process virtual model, the process window of the hot spot area is small, the response to the process fluctuation is sensitive, the defect scanning of the area can rapidly capture the process fluctuation and the product abnormality, and the timeliness of online defect monitoring is improved. That is, the present embodiment uses a process simulation means of DFM (manufacturability design) to guide inline process defect inspection, and applies a DFM process model to perform simulation on a product layout to obtain a process hot spot distribution map in the product layout.
Taking a CMP process as an example, under a stable process platform, testing patterns with different linewidths and different densities are utilized to show different thicknesses after chemical mechanical polishing, and a database of surface morphology and concave conditions is used for calibrating internal physical model parameters to obtain a CMP prediction model, so that the result of a product after CMP polishing can be accurately simulated and predicted; and (5) calling a CMP process model to predict the product layout and running the hot spot specification to obtain the hot spot distribution map of the surface morphology of the product layout.
Then, step S03 is executed to expand the high risk hot spot position to obtain an expanded region of the high risk hot spot, and the expanded regions with overlapping regions are merged to obtain the high risk region.
As shown in fig. 2, the high risk hotspot location extension includes: in an exposure unit 10, the center of the high-risk hot spot 100 is taken as an origin, and the expansion area 110 of the high-risk hot spot is obtained by expanding outwards by the expansion size d. The extension d ranges from 4um to 2mm, preferably, the extension d is 10um, that is, the expansion area 110 of the high risk hot spot includes the high risk hot spot and the peripheral range of 10um. Illustratively, the high risk hot spot location expansion includes expansion outward along a square, i.e., the expansion area 110 of the high risk hot spot 100 is square, the square being 2 times longer by the expansion dimension d. In other embodiments of the present invention, the expansion of the location of the high risk hot spot may also be expanded outwards in other ways, such as a circle.
With continued reference to FIG. 2, after the development area 110 of the high risk hotspot 100 is obtained, the development areas with overlapping areas are merged to obtain the high risk area 120.
Then, step S04 is executed to introduce the coordinate information set of the high risk area into the defect scanner terminal, and a scanning program is established according to the divided areas of the coordinate information set.
And distinguishing the high-risk area in the product layout from other areas of the product layout, setting different program parameters, and improving the scanning sensitivity of the defects of the area, so that the sensitivity of the scanning program corresponding to the high-risk area is higher than that of the scanning program corresponding to other areas of the product layout.
Further, in the method for detecting a defect of a semiconductor process pattern provided in this embodiment, after the wafer is scanned by the scanning program, the method further includes:
s05: performing defect selective inspection on the scanned product layout, and performing defect analysis on a defect selective inspection result;
s06: and optimizing the process according to the defect analysis result.
The proportion of the selective examination of the defects of the high-risk area is higher than that of other areas of the product layout, and the selective examination result of the high-risk area is subjected to defect analysis preferentially.
In this embodiment, the discrimination area sets appropriate program parameters for defect scanning, and establishes a scanning program with higher sensitivity to the high risk area; after the wafer is scanned by the defect scanning program, the proportion of the sample spot inspection (Review) of the defects in the high-risk area is increased, and the spot inspection result of the high-risk area is subjected to defect analysis preferentially, so that the problem of partial process systematic defect missing report can be effectively solved, the speed of finding the online process defects of the product is increased, the timeliness of online defect monitoring is improved, the process is optimized in time, and the yield is increased.
According to the method for detecting the defects of the semiconductor process patterns, the high-sensitivity region required in the defect scanning program is defined by combining the manufacturability process hot spot region, so that system defect report causing yield problem is effectively reduced, defect analysis time is shortened by 30%, process fluctuation and product abnormality can be rapidly grasped, and comprehensiveness and timeliness of online defect monitoring are improved.
In other embodiments of the present invention, the method for detecting defects in a semiconductor process pattern further includes: after expanding the high-risk hot spot position to obtain an expansion area of the high-risk hot spot, merging the expansion areas without the overlapped area to obtain a secondary high-risk area, wherein the sensitivity of a scanning program corresponding to the secondary high-risk area is higher than that of scanning programs corresponding to other areas of the product layout except the high-risk area. Correspondingly, after the wafer scanning is finished, the defect sampling rate corresponding to the next-highest risk area is higher than the defect sampling rate corresponding to other areas except the high-risk areas of the product layout. The division of the next highest risk regions further refines the wafer scan program, more specifically optimizes the process, relative to the single high risk region.
In summary, the method for detecting defects of a semiconductor process pattern provided by the invention predicts products through a virtual process model to obtain a high-risk hot spot distribution diagram of each process, and sets scanning program parameters of different areas to improve the sensitivity of the high-risk areas, optimize the defect scanning program and the defect spot inspection mode, solve the problem of partial systematic defect missing report of the process, improve the speed of finding online process defects of the products, improve the comprehensiveness and timeliness of online defect monitoring, optimize the process in time and improve the yield.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (10)

1. The method for detecting the pattern defects of the semiconductor process is characterized by comprising the following steps of:
establishing a corresponding virtual process model based on each process characteristic, and defining the type and specification of each corresponding process manufacturability hot spot;
invoking a virtual process model to predict a product layout and running hot spot specifications to obtain a distribution diagram of each process high risk hot spot of the product layout;
expanding the high-risk hot spot positions to obtain expansion areas of the high-risk hot spots, and merging the expansion areas with the overlapped areas to obtain high-risk areas;
and importing the coordinate information set of the high-risk area into a defect scanning machine terminal, and establishing a scanning program according to the coordinate information set division area to scan the wafer.
2. The method for detecting defects of a semiconductor process pattern according to claim 1, wherein the sensitivity of the scanning program corresponding to the high risk region is higher than that of the scanning program corresponding to other regions of the product layout.
3. The method of claim 1, wherein the scanning the wafer by the scanning program further comprises:
and performing the selective inspection of the defects on the scanned wafer, and performing defect analysis on the selective inspection result of the defects.
4. The method for detecting defects of a semiconductor process pattern according to claim 3, wherein the ratio of the random inspection of the high risk area is higher than that of other areas of the product layout, and the random inspection result of the high risk area is subjected to the defect analysis preferentially.
5. The method for detecting defects of a semiconductor process pattern according to claim 3 or 4, further comprising: and (5) optimizing the process according to the defect analysis result.
6. The method of claim 1, wherein the high risk hot spot location extension comprises: taking the center of the high-risk hot spot position as an origin, and expanding outwards by a set expansion size; the extension size ranges from 4um to 2mm.
7. The method of claim 6, wherein the extension dimension is 10um.
8. The method of claim 6, wherein the high risk hot spot location expansion comprises expanding outward along a square.
9. The method for detecting the defects of the semiconductor process pattern according to claim 1, wherein the virtual process model is based on a stable process platform, and a photomask is designed to conduct wafer flow so as to obtain mapping relations between different layout designs and processes;
the virtual process model comprises a photoetching process window model and a chemical mechanical polishing model.
10. The method for detecting defects of a semiconductor process pattern according to claim 1, further comprising: combining the expansion areas without the overlapping areas to obtain a secondary high risk area, wherein the sensitivity of the scanning program corresponding to the secondary high risk area is higher than that of the scanning program corresponding to other areas of the product layout except the high risk area.
CN202310333354.7A 2023-03-31 2023-03-31 Method for detecting pattern defects of semiconductor process Pending CN116342557A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310333354.7A CN116342557A (en) 2023-03-31 2023-03-31 Method for detecting pattern defects of semiconductor process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310333354.7A CN116342557A (en) 2023-03-31 2023-03-31 Method for detecting pattern defects of semiconductor process

Publications (1)

Publication Number Publication Date
CN116342557A true CN116342557A (en) 2023-06-27

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