CN111930578A

CN111930578A - Onboard DDR (double data Rate) bandwidth testing method and system based on FPGA (field programmable Gate array)

Info

Publication number: CN111930578A
Application number: CN202010673862.6A
Authority: CN
Inventors: 何志伟; 代宗骏; 高明煜; 黄继业
Original assignee: Hangzhou Dianzi University
Current assignee: Hangzhou Dianzi University
Priority date: 2020-07-14
Filing date: 2020-07-14
Publication date: 2020-11-13

Abstract

The invention discloses an onboard DDR bandwidth testing method and system based on an FPGA. The CPU driving program accesses the configuration space of the currently mounted FPGA equipment through a PCIe bus; the DDR control module initiates DDR HARD IP corresponding read-write command operation, and the whole bandwidth test starts to be executed; the bandwidth calculation module writes the actual DDR read-write bandwidth and the measurement error which are obtained through calculation into a corresponding configuration space register; the bandwidth calculation module initiates an interrupt request to the PCIe HARD IP, and the interrupt request is transmitted to the CPU through the PCIe bus. The method has short measurement period, and can complete the bandwidth test on the onboard DDR without compiling a brand new test code; the DDR bandwidth can be tested only by changing the parameter modification of the memory control IP of the onboard DDR; no board-on-board testing is required.

Description

Onboard DDR (double data Rate) bandwidth testing method and system based on FPGA (field programmable Gate array)

Technical Field

The invention belongs to the technical field of storage, and particularly relates to an onboard DDR (double data rate) bandwidth testing method and system based on an FPGA (field programmable gate array).

Background

Currently, an FPGA (Field-Programmable Gate Array) plays a great role in the fields of technology research and development, product manufacturing, subject research, and the like. DDR (DDR SDRAM, double data rate synchronous Dynamic Random Access Memory) becomes a common external Memory in FPGA hardware design due to its advantages of large capacity, small delay, and strong environmental adaptability. With the increasing access amount to the FPGA on-board DDR memory and the bandwidth performance as an important technical index of the DDR memory, the bandwidth of the memory controller is also becoming a concern of designers. In a conventional wide testing method for an on-board DDR of an FPGA, a common testing method is to write a brand-new bandwidth testing code by a hardware designer, and perform a bandwidth test on the on-board DDR by using a memory control IP (referred to as DDR hard IP). More often, for a specific FPGA development project with use of DDR memory, the test work (including consistency test, bandwidth test, etc.) in the early stage of on-board DDR is performed separately, and there is no uniform bandwidth test scheme and tool. The disadvantages of this method are the following: 1. the time period for the measurement is long. Brand new test codes need to be written, and time and labor are wasted; 2. the measurement method is not highly multiplexed. When the model of the FPGA is changed, the configuration parameters of the storage control IP are correspondingly modified to adapt to the current DDR memory particles. 3. The convenience of the measuring method is low. The board-loading test is needed to obtain the bandwidth size in a certain intuitive way, and the way generally comprises the steps of grabbing a signal line by the board or displaying a nixie tube and the like.

Disclosure of Invention

The invention aims to solve the technical problem of bandwidth testing, and provides an onboard DDR bandwidth testing method based on an FPGA, which is accurate in measurement, adjustable in mode and precision, so that the limitation of the traditional bandwidth testing mode can be solved.

An onboard DDR bandwidth testing method based on an FPGA comprises the following specific steps:

step (1), the CPU driver accesses the configuration space of the currently mounted FPGA device through the PCIe bus, at this time, the FPGA serves as an EP device (end point) in the current PCIe topology structure, and the driver can modify the value of a corresponding register in the configuration space of the EP device so as to regulate and control the configuration information of the bandwidth test.

The configuration space is provided with a plurality of registers, wherein one part of the registers contain configuration information of corresponding bandwidth test and a bandwidth test result returned by the bandwidth test device, and the rest part of the registers are not processed. The configuration information comprises information such as a bandwidth test starting mark, a bandwidth test mode, bandwidth measurement precision, read-write command duty ratio precision and the like.

The bandwidth test starting mark is a certain register in the configuration space. If the register value is set to 1, the bandwidth test is started.

The bandwidth test mode comprises sequential address reading and writing, random address reading and writing, adjustable reading and writing duty ratio and the like.

The sequential address read-write mode takes sequential addresses as an addressing mode. In this mode, the read and write addresses are generated by the counter accumulation. For other configuration information, the mode control module acquires a register value which is issued by the CPU and contains bandwidth test configuration information from the configuration space, acquires precision information of bandwidth test from the register value, and finally respectively tests the bandwidth size under two scenes of sequential address writing and sequential address reading.

The random address read-write mode takes a random address as an addressing mode. In this mode, the mode control module obtains a register value containing bandwidth test configuration information issued by the CPU from the configuration space, thereby obtaining an initial SEED value SEED of the LFSR, which is used as an initial value of the LFSR. The method is characterized in that a pseudo-random sequence is generated by an LFSR (Linear Feedback Shift Register) algorithm to be used as a read-write address, so that the process of reading and writing the random address is realized, the addressing range is 1-2 ^ N-1, and N represents the order of the LFSR. And simultaneously, acquiring the precision information of the bandwidth test from the configuration space register value.

The read-write duty ratio adjustable mode adopts two configurable addressing modes of a sequential address and a random address. In the mode, the proportion of the read-write command and the addressing mode are both adjustable, wherein the adjustment of the proportion of the read-write command is determined by the duty ratio precision of the read-write command, and the addressing mode is determined by the current duty ratio precision of the read-write commandThe configuration information sent by the CPU. The read-write command duty ratio precision P is obtained by the mode control module from a register value which is issued by the CPU and contains bandwidth test configuration information. Setting duty _ bits in the duty ratio control module to be corresponding bit width according to the acquired read-write command duty ratio precision P, wherein at the moment

The bandwidth testing device respectively tests the read-write bandwidth with the duty ratio of P to 1-P. And simultaneously, acquiring the precision information of the bandwidth test from the configuration space register value.

The definition of the duty ratio precision P value of the read-write command is the proportion between the minimum time of the high level duration in one clock period and the whole clock period. Recording the minimum time of the high level duration as 1(1< F), and if the clock period is F, then P is 1/F;

the duty _ bits in the duty ratio control module represents the bit width of the total read-write command duty ratio range.

The bandwidth test precision is that the mode control module obtains the value of a corresponding register from the configuration space so as to obtain the corresponding bandwidth measurement precision; the bandwidth measurement precision register is represented by 4 bits, and has 16 gears from 0 to 15 respectively, which represent 16 window sizes from 4096 to 20480 respectively, and the difference between each gear is 1024 clock cycles. The longer the window length, the higher the accuracy, and conversely, the smaller the accuracy. The principle of bandwidth measurement is to count the number of read/write commands in a specified time window, and the ratio of the number of read _ cmd _ cnt and write _ cmd _ cnt to the length of the whole time window (window _ size) is multiplied by the theoretical total bandwidth to obtain the measured actual bandwidth. The bandwidth measurement accuracy thus determines the size of the time window length (window _ size).

And (2) when the register position 1 for starting the bandwidth test is marked, marking that the bandwidth test starts, and automatically acquiring corresponding bandwidth test configuration information from a corresponding register in a configuration space by a mode control module in the bandwidth test device, wherein the configuration information comprises information such as input bandwidth test mode type, test precision and the like.

Step (3), the mode control module respectively executes the initialization operation of the corresponding test mode to the address generation module and the duty ratio control module in the DDR adaptation module according to the configuration information of the bandwidth test mode obtained in the step (2);

wherein the initialization operation comprises: 1. appointing the order N of LFSR linear shift register in the address generation module; 2. specifying a size of an initialization SEED value SEED of the LFSR linear shift register; 3. and specifying the duty ratio precision P in the duty ratio control module to obtain the corresponding duty _ bits bit width. 4. Initializing the time window size window _ size in the bandwidth calculation module to match the precision of the current bandwidth test.

Step (4), after the DDR adaptation module is initialized in step (3), the DDR control module initiates DDR HARD IP corresponding read-write command operation, and the whole bandwidth test starts to be executed;

in the test process, the bandwidth calculation module continuously counts the count values (read _ cmd _ cnt and write _ cmd _ cnt) of the read command and the write command in a single specified time window size (window _ size) for multiple times, and calculates the actual DDR read-write bandwidth size according to the formulas (1) to (2).

The theoretical total bandwidth calculation formula is as follows:

BAND_WIDTH ＝fclk* DATA_WIDTH (3)

BAND _ WIDTH in the above formula is the theoretical total bandwidth size, and the unit is Byte; f. of_clkIs the clock frequency; DATA _ WIDTH is the DATA bit WIDTH in bytes.

The calculation formula of the actual write bandwidth is as follows:

in the above formula, WRITE _ BAND _ WIDTH is the actual WRITE bandwidth size, and the unit is Byte; the write _ cmd _ cnt is the number of write commands issued in the test time window; window _ size is the length of a time window, which refers to the total number of clock cycles in a window; f. of_clkIs the clock frequency; DATA _ WIDTH is a DATA bitWidth, unit is Byte.

The calculation formula of the actual read bandwidth is as follows:

in the above formula, READ _ BAND _ WIDTH is the actual READ bandwidth size, and the unit is Byte; the read _ cmd _ cnt is the number of read commands issued in the test time window; window _ size is the time window length; f. of_clkIs the clock frequency; DATA _ WIDTH is the DATA bit WIDTH in bytes.

Step (5), after the whole test is finished, calculating the final total bandwidth and the measurement error by a bandwidth calculation module, and writing the final result into a corresponding configuration space register; and then the bandwidth calculation module initiates an interrupt request to the PCIe HARD IP, and the interrupt request is transmitted to the CPU through the PCIe bus to inform the CPU that the current bandwidth test is completed. After receiving the interrupt, the CPU obtains the value of the register from the configuration space, and finally obtains the actual bandwidth size and error size.

Write bandwidth error estimation: for the write command, the command and the data are issued to the DDR controller at the same time (in the same clock cycle), so when the number of the write commands is used to replace the actual data amount, there is no error, and the write bandwidth error is 0.

And (3) reading bandwidth error estimation: when calculating the actual read bandwidth, the bandwidth size of the read return data in the whole time window is estimated according to the number of the read commands. The actual bandwidth size is related to the size of the time window, since there is some delay in the return of data. Remember that the read data return delay is about M clock cycles and the bandwidth time window is window _ size. The measurement error of the read bandwidth is M/window _ size.

Another object of the present invention is to provide an FPGA-based DDR bandwidth test device for implementing the above method, the device comprising:

the mode control module is used for acquiring a total bandwidth test request and configuration information based on the FPGA on-board DDR memory from the configuration space, and then initializing the address generation module and the duty ratio control module according to the corresponding test request and configuration information; wherein the total bandwidth test request includes a bandwidth mode and configuration information for the current test.

The DDR adaptation module comprises a duty ratio control module, an address generation module, a bandwidth calculation module, a DDR control module and the like.

The address generating module is used for receiving the bandwidth test mode information transmitted by the mode control module and generating corresponding address information; if the corresponding mode is a random address read-write mode or a read-write duty ratio adjustable mode adopting a random address addressing mode, generating pseudo-random sequences based on an LFSR (Linear feedback Shift register), and respectively using the pseudo-random sequences as read-write addresses; if the corresponding mode is a sequential address reading and writing mode or a reading and writing duty ratio adjustable mode adopting a sequential address addressing mode, the counter accumulates to generate a reading and writing address.

The duty ratio control module is used for receiving the bandwidth test mode information transmitted by the mode control module, acquiring the duty ratio precision of the read-write command in the configuration information from the mode control module if the corresponding mode is a read-write duty ratio adjustable mode, and adjusting the read-write command proportion according to the read-write command duty ratio precision; and if the corresponding mode is a sequential address read-write mode or a random address read-write mode, not operating.

The bandwidth calculation module is used for receiving the bandwidth precision information from the mode control module and acquiring the window size window _ size of the current test; the DDR control module is used for receiving the number of read commands (read _ cmd _ cnt) and the number of write commands (write _ cmd _ cnt) from the DDR control module. The read and write bandwidth sizes can thus be calculated from the above three parameters, and the current bandwidth measurement error is recorded, where the measurement error is determined by the size of window _ size.

And the DDR control module is used for initiating a read-write command operation to DDR HARD IP according to the read-write command duty ratio adjustment information of the duty ratio control module and the read-write address information of the address generation module, and simultaneously sending the number of the initiated read and write commands to the bandwidth calculation module.

The invention has the beneficial effects that:

the invention uses PCIe bus to access the configuration space of EP device through CPU driver, based on LFSR algorithm, and multi-mode adjustable testing method, to measure read-write bandwidth of onboard DDR in multiple modes. For the whole testing process, the characteristic of pseudo-randomness of a sequence generated by an LFSR algorithm is mainly utilized to obtain a random address or a random read-write duty ratio to access an on-board DDR memory so as to test the bandwidth size of the on-board DDR in different modes.

The advantages of the whole invention are as follows: firstly, the measurement period is greatly reduced, and the bandwidth test can be completed on the onboard DDR without compiling a brand new test code; secondly, the measurement method has strong portability and high reusability. The DDR bandwidth can be tested only by changing the parameter modification of the memory control IP of the onboard DDR; thirdly, the measurement method is very convenient. The board-up test need not be performed, but instead a test operation is initiated by the CPU side and the test result is displayed on the CPU side. Fourthly, the diversification of the test mode not only supports two modes of conventional common sequential address and random address, but also supports a read-write duty ratio adjustable mode, and better simulates the scene that a user accesses the storage device in actual service.

Drawings

FIG. 1 is a schematic diagram of an error of a read bandwidth of an on-board DDR bandwidth test method based on an FPGA;

FIG. 2 is a schematic diagram of an LFSR algorithm based pseudo-random number generation;

FIG. 3 is a schematic diagram of classification of bandwidth test modes of an on-board DDR bandwidth test method based on an FPGA;

FIG. 4 is a schematic flow chart of an on-board DDR bandwidth testing method based on an FPGA;

FIG. 5 is a block diagram of a structure of an on-board DDR bandwidth testing device based on an FPGA.

Detailed Description

The invention will be further analyzed with reference to the following figures.

As shown in fig. 4, the onboard DDR bandwidth testing method based on the FPGA specifically includes the following steps:

The LFSR is used to generate a repeatable PRBS (Pseudo-Random Binary Sequence), and the circuit consists of n-stage flip-flops and several exclusive-or gates, as shown in fig. 2:

wherein gn is a feedback coefficient, the value of gn can only be 0 or 1, when 0 is taken, the feedback path does not exist, and when 1 is taken, the feedback path exists; the feedback coefficients here determine the difference in the algorithm for generating the random numbers. Expressed as y ═ a by the feedback function₀x⁰+a₁x¹+a₂x²+…+a_n-1x^n-1+a_nxⁿ. The feedback function is a linear, called linear, shift feedback sequence. The initial value of the LFSR is called the seed of the pseudo-random sequence and the bits affecting the next state are called taps. The LFSR's trigger number typically starts at 1 and the tap values range from 1 to 2^ n-1. Tap sequences may be used to describe the feedback polynomial of the LFSR. An LFSR circuit consisting of n flip-flops may produce a sequence with a period of 2^ n-1. Theory shows that to obtain the longest period of the LFSR, the polynomial formed by the tap sequence plus 1 is its feedback polynomial, which must be a primitive polynomial.

It should be noted that the initial value of the LFSR should avoid going into the all 0 disabled state. Because the states are all 0, the user cannot jump to the next state and cannot generate a new random value.

The read-write duty ratio adjustable mode adopts two configurable addressing modes of a sequential address and a random address. In the mode, the proportion of the read-write command and the addressing mode are both adjustable, wherein the adjustment of the proportion of the read-write command is determined by the duty ratio precision of the read-write command, and the addressing mode is determined by the configuration information issued by the current CPU. The read-write command duty ratio precision P is obtained by the mode control module from a register value which is issued by the CPU and contains bandwidth test configuration information. Setting duty _ bits in the duty ratio control module to be corresponding bit width according to the acquired read-write command duty ratio precision P, wherein at the moment

For example, as described below, the bandwidth size is currently measured for a write command ratio of 1/8-7/8 (in this case, the ratio of 7/8-1/8 for read commands). 3bits in the LFSR are intercepted by utilizing the pseudo-randomness of the sequence generated by the LFSR, and the intercepted 3bits are marked as duty _3bits, and the duty _3bits can be used as the control basis for duty ratio regulation because the probability that the value of the duty _3bits is 0-7 is the same.

The specific control is as follows:

when the duty _3bits is less than 1, a write command is initiated, and when the duty _3bits is more than or equal to 1, a read command is initiated. The operation may achieve a write command duty cycle of 1/8 and a read duty cycle of 7/8.

Similarly, when the duty _3bits is less than 7, the write command is initiated, and when the duty _3bits is more than or equal to 7, the read command is initiated. The operation may achieve a write command duty cycle of 7/8 and a read duty cycle of 1/8.

The method is further popularized, and the duty ratio bandwidth test of any read-write command with the denominator of a power number of 2 can be realized.

All bandwidth test patterns are classified as shown in diagram (3).

The theoretical total bandwidth calculation formula is as follows:

BAND_WIDTH ＝fclk* DATA_WIDTH (3)

The calculation formula of the actual write bandwidth is as follows:

in the above formula, WRITE _ BAND _ WIDTH is the actual WRITE bandwidth size, and the unit is Byte; the write _ cmd _ cnt is the number of write commands issued in the test time window; window _ size is the length of a time window, which refers to the total number of clock cycles in a window; f. of_clkIs the clock frequency; DATA _ WIDTH is the DATA bit WIDTH in bytes.

The calculation formula of the actual read bandwidth is as follows:

And (3) reading bandwidth error estimation: when calculating the actual read bandwidth, the bandwidth size of the read return data in the whole time window is estimated according to the number of the read commands. The actual bandwidth size is related to the size of the time window, since there is some delay in the return of data. Note that the read data return delay is about M clock cycles as in fig. 1, and the bandwidth time window is window _ size. The measurement error of the read bandwidth is M/window _ size.

An FPGA-based DDR bandwidth test device for the method described above with reference to fig. 5, the device comprising:

Claims

1. An onboard DDR bandwidth testing method based on an FPGA is characterized by comprising the following steps:

step (1), a CPU driver accesses a configuration space of the currently mounted FPGA device through a PCIe bus, the FPGA is used as an EP device in a current PCIe topological structure, and the CPU driver is used for regulating and controlling configuration information of a bandwidth test by modifying values of corresponding registers in the configuration space of the EP device;

the configuration space is provided with a plurality of registers, wherein one part of the registers contain configuration information of corresponding bandwidth test and a bandwidth test result returned by the bandwidth test device; the configuration information comprises information such as a bandwidth test starting mark, a bandwidth test mode, bandwidth measurement precision, read-write command duty ratio precision and the like;

the bandwidth test mode comprises sequential address reading and writing, random address reading and writing, adjustable reading and writing duty ratio and the like;

the sequential address read-write mode takes sequential addresses as an addressing mode, and the read-write addresses are generated by accumulating a counter; for other configuration information, the mode control module acquires a register value which is issued by the CPU and contains bandwidth test configuration information from the configuration space, acquires precision information of bandwidth test from the register value, and finally respectively tests the bandwidth size under two scenes of sequential address writing and sequential address reading;

the random address read-write mode takes a random address as an addressing mode; in the mode, the mode control module acquires a register value which is issued by the CPU and contains bandwidth test configuration information from a configuration space, so as to acquire an initial SEED value SEED of the LFSR, and the value is used as an initial value of the LFSR; generating a pseudo-random sequence as a read-write address by an LFSR; simultaneously, acquiring the precision information of the bandwidth test from the configuration space register value;

the read-write duty ratio adjustable mode adopts two configurable addressing modes of a sequential address and a random address; in the mode, the proportion of the read-write command and the addressing mode are both adjustable, wherein the adjustment of the proportion of the read-write command is determined by the accuracy of the duty ratio of the read-write command, and the addressing mode is determined by the configuration information issued by the current CPU; the read-write command duty ratio precision P is obtained by the mode control module from a register value which is issued by the CPU and contains bandwidth test configuration information; setting duty _ bits in the duty ratio control module to be corresponding bit width according to the acquired read-write command duty ratio precision P, wherein at the moment

The bandwidth testing device respectively tests the read-write bandwidth with the duty ratio of P to 1-P; simultaneously, acquiring the precision information of the bandwidth test from the configuration space register value;

step (2), when the register 1 for starting the bandwidth test is marked, the bandwidth test is marked to start, and a mode control module in the bandwidth test device can automatically acquire corresponding bandwidth test configuration information from a corresponding register in a configuration space;

in the test process, the bandwidth calculation module continuously counts the count values (read _ cmd _ cnt and write _ cmd _ cnt) of the read command and the write command in a single specified time window size (window _ size) for multiple times, and calculates the actual DDR read-write bandwidth size according to the formulas (1) to (2);

the calculation formula of the actual write bandwidth is as follows:

wherein, the WRITE _ BAND _ WIDTH is the actual WRITE bandwidth size and the unit is Byte; the write _ cmd _ cnt is the number of write commands issued in the test time window; window _ size is the length of a time window, which refers to the total number of clock cycles in a window; f. of_clkIs the clock frequency; DATA _ WIDTH is the DATA bit WIDTH and the unit is Byte;

the calculation formula of the actual read bandwidth is as follows:

wherein, READ _ BAND _ WIDTH is the actual reading bandwidth size and the unit is Byte; the read _ cmd _ cnt is the number of read commands issued in the test time window; window _ size is the time window length; f. of_clkIs the clock frequency; DATA _ WIDTH is the DATA bit WIDTH and the unit is Byte;

step 5, after the whole test is finished, the bandwidth calculation module writes the actual DDR read-write bandwidth and the measurement error which are obtained through calculation into a corresponding configuration space register; wherein the measurement error comprises a write bandwidth error and a read bandwidth error;

write bandwidth error estimation: because the write command and the data are issued to the DDR controller in the same clock cycle, when the actual data volume is replaced by the number of the write commands, no error exists at this time, and the write bandwidth error is 0;

and (3) reading bandwidth error estimation: when the actual read bandwidth is calculated, the bandwidth size of the read return data in the whole time window is estimated according to the number of the read commands; the actual bandwidth size is related to the size of the time window, since there is some delay in the data return; recording the read data return delay to be about M clock cycles, wherein the bandwidth time window is window _ size, and the measurement error of the read bandwidth is M/window _ size;

step (6), the bandwidth calculation module initiates an interrupt request to the PCIe HARD IP, the interrupt request is transmitted to the CPU through the PCIe bus, and the CPU is informed that the current bandwidth test is completed; after receiving the interrupt, the CPU obtains the value of the register from the configuration space, and finally obtains the actual DDR read-write total bandwidth and the measurement error.

2. The FPGA-based on-board DDR bandwidth test method of claim 1, wherein the addressing range for realizing the process of reading and writing the random address in the random address reading and writing mode is 1 to 2^ N-1, N represents the order of LFSR.

3. The FPGA-based on-board DDR bandwidth test method of claim 1, wherein the step (3) of initializing comprises: 1. appointing the order N of LFSR linear shift register in the address generation module; 2. specifying a size of an initialization SEED value SEED of the LFSR linear shift register; 3. specifying the duty ratio precision P in the duty ratio control module to obtain the corresponding duty _bitsbit width; 4. initializing the time window size window _ size in the bandwidth calculation module to match the precision of the current bandwidth test.

4. The FPGA-based on-board DDR bandwidth test method of claim 1, wherein the definition of the precision P value of the duty ratio of the read-write command is the ratio between the minimum time of the duration of the high level in one clock cycle and the whole clock cycle, and the minimum time of the duration of the high level is 1(1< F), and if the clock cycle is F, then P is 1/F.

5. The FPGA-based on-board DDR bandwidth test method of claim 1, wherein the bandwidth test precision is that the mode control module obtains the value of the corresponding register from the configuration space to obtain the corresponding bandwidth measurement precision; the bandwidth measurement precision register is represented by 4 bits, and has 16 gears from 0 to 15 respectively, which represent 16 window sizes from 4096 to 20480 respectively, and the difference between each gear is 1024 clock cycles.

6. An FPGA-based DDR bandwidth test device on board, the device comprising:

the mode control module is used for acquiring a total bandwidth test request and configuration information based on the FPGA on-board DDR memory from the configuration space, and then initializing the address generation module and the duty ratio control module according to the corresponding test request and configuration information; wherein, the total bandwidth test request comprises a bandwidth mode and configuration information aiming at the test;

the DDR adaptation module comprises a duty ratio control module, an address generation module, a bandwidth calculation module, a DDR control module and the like;

the address generating module is used for receiving the bandwidth test mode information transmitted by the mode control module and generating corresponding address information; if the corresponding mode is a random address read-write mode or a read-write duty ratio adjustable mode adopting a random address addressing mode, generating pseudo-random sequences based on an LFSR (Linear feedback Shift register), and respectively using the pseudo-random sequences as read-write addresses; if the corresponding mode is a sequential address reading and writing mode or a reading and writing duty ratio adjustable mode adopting a sequential address addressing mode, accumulating by a counter to generate a reading and writing address;

the duty ratio control module is used for receiving the bandwidth test mode information transmitted by the mode control module, acquiring the duty ratio precision of the read-write command in the configuration information from the mode control module if the corresponding mode is a read-write duty ratio adjustable mode, and adjusting the read-write command proportion according to the read-write command duty ratio precision; if the corresponding mode is a sequential address read-write mode or a random address read-write mode, the operation is not carried out;

the bandwidth calculation module is used for receiving the bandwidth precision information from the mode control module and acquiring the window size window _ size of the current test; the DDR control module is used for receiving the number of read commands (read _ cmd _ cnt) and the number of write commands (write _ cmd _ cnt) from the DDR control module; therefore, the read bandwidth and the write bandwidth can be calculated according to the three parameters, and the current bandwidth measurement error is recorded, wherein the measurement error is determined by the size of the window _ size;