CN111224664A - Digital calibration method and device for SoC built-in high-precision high-speed oscillator - Google Patents
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Abstract
The invention relates to the technical field of electronics, in particular to a digital calibration method and a digital calibration device for a high-precision high-speed oscillator built in a system on chip (SoC). A method of digital calibration of a high speed oscillator, comprising: the device comprises an off-chip auxiliary calibration device, an on-chip I/O multiplexing management module, an OSC digital fast frequency calibration module, a calibration result decision device, an on-chip high-speed oscillator and an embedded Flash; the dichotomy progressive quick correction calibration algorithm supports configurable bit width parameterization of a calibration register Trim so as to meet different SoC chip calibration error requirements; the digital calibration process of the on-chip high-speed oscillator can quickly find the threshold value through dichotomy recursion judgment, so that the efficiency is improved, and the method is simple. Furthermore, the invention also adds a first-stage calibration error decision device, which can further improve the half-bit precision of the calibration system. In addition, the off-chip auxiliary calibration device provides a low-speed clock reference and an upper computer calibration operation interface, so that the operation of a user is facilitated and the mass production process is accelerated.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a digital calibration method and a digital calibration device for a high-precision high-speed oscillator built in a system on chip (SoC).
Background
The on-chip high-speed oscillator is widely used in timers and pulse sources due to the characteristics of easy frequency adjustment, small element size, low cost, low energy consumption and the like. The device can convert a direct current signal into a periodic alternating current signal without an external excitation signal. However, in practical applications, the on-chip high-speed oscillator is limited by the process and temperature, and the output frequency may generate a large error. The traditional on-chip high-speed oscillator only achieves the purpose of shaping the waveform, and does not essentially improve the cycle precision of the on-chip high-speed oscillator. The accuracy and speed of the algorithm in the frequency calibration block is directly related to the performance of the clock circuit of the on-chip high-speed oscillator. If a step-by-step algorithm is adopted, although the target value can be obtained finally, the convergence speed is too slow and the efficiency is not high.
The frequency calibration module detects the frequency of the clock signal output by the clock circuit through the counter. The counter counts the clock signal at a low reference clock high level after the reset signal reset occurs. When the clock frequency meets the requirement and is just a high-speed clock, the counting result is N _ Ref, and the clock calibration is not needed at the moment. In the initial state, the value of the adj _ bit of the logic control unit is 128, and the control signal is used for controlling the on-chip high-speed oscillator. When the clock frequency has deviation, the output value of each adj _ bit of the logic control unit is adjusted in the logic control circuit by writing codes.
The counting result of the counter is N, when the clock period is larger, N is smaller than N _ Ref, the output value of the digital logic control unit is adjusted to be [ adj _ bit +1], the change of the output value of the digital logic control unit can cause the change of the output current in the current mirror switch array, the current is used for charging and discharging the internal capacitor of the clock circuit, the change of the current can cause the change of the charging and discharging time, and the output clock frequency is adjusted. The change of the clock frequency is used as the input of the logic control unit, so that the counting value N of the internal counter is changed. And repeating iteration for several times until the value of N meets the requirement that N is more than or equal to N _ Ref-1 and less than or equal to N _ Ref +1, and at the moment, the output clock frequency meets the requirement and the calibration is finished. When the clock frequency is larger, the counting result N is larger than N _ Ref +1, at the moment, the value of the adj _ bit is adjusted to be [ adj _ bit-1], and iteration is repeated for a plurality of times until the value of N meets the condition that N is larger than or equal to N _ Ref-1 and smaller than or equal to N _ Ref + 1.
Under the typical application of 8 bits of the calibration register, the above scheme needs more than 40 times of calibration to generate a stable clock, and the convergence speed is very slow.
Disclosure of Invention
Therefore, the invention provides a digital calibration method and a digital calibration device for a low-power-consumption high-precision high-speed oscillator built in a SoC (system on chip), which aim to solve the problem of low convergence speed of frequency calibration of the high-speed oscillator in the prior art caused by an algorithm.
In order to achieve the above object, the embodiments of the present invention provide the following technical solutions:
according to a first aspect of embodiments of the present invention, a method for calibrating a high-speed oscillator includes:
acquiring the reference frequency of the off-chip auxiliary calibration device; and the output frequency of the high-speed oscillator after calibration;
and according to the reference frequency, performing frequency calibration on the output frequency of the high-speed oscillator by using a dichotomy progressive quick correction calibration algorithm so as to enable the final output frequency of the high-speed oscillator to be in accordance with expectation.
Further, a dichotomy progressive fast correction calibration algorithm is adopted to perform frequency calibration on the output frequency of the high-speed oscillator, and the method comprises the following steps:
calibrating through a plurality of calibration periods; a dichotomy progressive quick correction calibration algorithm is used in each calibration period, so that the output frequency of the high-speed oscillator is gradually approximated to the expected frequency.
Further, after the calibration is completed, the method further includes:
recording current _ stat _ cnt of the last two calibration periods, which are respectively marked as stat _ cnt [ BT _ MAX-1] and stat _ cnt [ BT _ MAX ]; and recording the corresponding Trim1 and Trim 2;
calculating to obtain a difference value A between stat _ cnt [ BT _ MAX ] and current _ stat _ cnt;
calculating the difference B between stat _ cnt [ BT _ MAX-1] and cur _ stat _ cnt;
comparing the sizes of A and B;
if A is smaller than B, determining Trim2 as the final Trim value of the calibration register;
if B is smaller than A, determining Trim1 as the final Trim value of the calibration register;
the cur _ stat _ cnt is the number of clock pulses of the high-speed oscillator in one calibration period.
According to a second aspect of the embodiments of the present invention, a calibration apparatus of a high-speed oscillator includes:
the device comprises an off-chip auxiliary calibration device, an on-chip I/O multiplexing management module, an OSC digital rapid calibration frequency module, a calibration result decision device, an on-chip high-speed oscillator and an embedded Flash;
the upper computer in the off-chip auxiliary device is used for controlling the Soc chip to start calibration and receiving a status indication mark indicating whether the calibration result is successful or not;
the on-chip calibration register is used for storing Trim values after each calibration period is finished; sending the Trim value to an on-chip high-speed oscillator;
the on-chip high-speed oscillator is used for receiving the Trim value of each calibration period sent by the on-chip calibration register; updating the clock frequency according to the received Trim value and outputting the clock frequency to a digital circuit;
the OSC digital fast calibration frequency module is used for acquiring a reference frequency provided by the off-chip calibration auxiliary device; and the frequency of the output of the high-speed oscillator after digital calibration;
and calculating by adopting a dichotomy progressive quick correction calibration algorithm, and performing frequency calibration on the output frequency of the high-speed oscillator so as to enable the output frequency of the high-speed oscillator to be in line with expectation.
Further, still include:
a calibration result decision device in the SoC chip;
the calibration result decision device is used for recording the last two times of current _ stat _ cnt which are respectively marked as stat _ cnt [ BT _ MAX-1] and stat _ cnt [ BT _ MAX ]; and recording the corresponding Trim1 and Trim 2;
calculating to obtain a difference value A between stat _ cnt [ BT _ MAX ] and current _ stat _ cnt;
calculating the difference B between stat _ cnt [ BT _ MAX-1] and cur _ stat _ cnt;
comparing the sizes of A and B;
if A is smaller than B, determining Trim2 as a Trim value of a calibration register;
if B is less than A, then Trim1 is determined as the calibration register Trim value.
Further, the system also comprises a Flash memory in the SoC chip, and the Flash memory is used for storing the final Trim value after digital calibration.
Further, the bit width parameter of the calibration register may be configured, typically with 8 or 12 bits.
Furthermore, the upper computer of the off-chip calibration auxiliary device is also used for receiving the completion information sent by the chip after the SoC chip is calibrated; and when the calibration is started, sending a command for starting the calibration to the SoC chip.
The embodiment of the invention has the following advantages: a digital calibration method and device for a low-power-consumption high-precision high-speed oscillator built in an SoC (system on chip) comprise an off-chip auxiliary calibration device, an on-chip I/O multiplexing management module, an OSC (open channel controller) quick calibration frequency module, a calibration result decision device, an on-chip high-speed oscillator and an embedded Flash. The dichotomy progressive quick correction calibration algorithm supports configurable bit width parameterization of a calibration register Trim so as to meet different SoC chip calibration error requirements; the digital calibration process of the on-chip high-speed oscillator can quickly find the threshold value through dichotomy recursion judgment, so that the efficiency is improved, and the method is simple. The invention also adds a first-stage calibration error decision device, which can further improve the half-bit precision of the calibration system. In addition, the off-chip auxiliary calibration device provides a low-speed clock reference and an upper computer calibration operation interface, so that the operation of a user is facilitated and the mass production process is accelerated.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It should be apparent that the drawings in the following description are merely exemplary, and that other embodiments can be derived from the drawings provided by those of ordinary skill in the art without inventive effort.
The structures, ratios, sizes, and the like shown in the present specification are only used for matching with the contents disclosed in the specification, so that those skilled in the art can understand and read the present invention, and do not limit the conditions for implementing the present invention, so that the present invention has no technical significance, and any structural modifications, changes in the ratio relationship, or adjustments of the sizes, without affecting the functions and purposes of the present invention, should still fall within the scope of the present invention.
Fig. 1 is a flowchart of a calibration method for a high-speed oscillator according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a digital calibration apparatus with a low power consumption, high precision and high speed oscillator built in SoC according to an embodiment of the present invention;
fig. 3 is a dichotomy progressive fast correction calibration process according to an embodiment of the present invention.
Detailed Description
The present invention is described in terms of particular embodiments, other advantages and features of the invention will become apparent to those skilled in the art from the following disclosure, and it is to be understood that the described embodiments are merely exemplary of the invention and that it is not intended to limit the invention to the particular embodiments disclosed. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A method of calibrating a high speed oscillator, see fig. 1, the method comprising:
step S101, acquiring a reference frequency of an off-chip auxiliary calibration device; and the output frequency of the high-speed oscillator after calibration;
wherein, the reference frequency can be provided by an external auxiliary upper computer;
the output frequency of the high-speed oscillator is distorted and deviates from the expected frequency, and the number of clock pulses in a preset time needs to be counted by a counter to obtain the accurate output frequency of the high-speed oscillator.
And S102, according to the reference frequency, performing frequency calibration on the output frequency of the high-speed oscillator by using a dichotomy progressive quick correction calibration algorithm so as to enable the final output frequency of the high-speed oscillator to be in line with expectation.
Wherein the expected frequency is a standard frequency of the high-speed oscillator in normal operation.
The method for calibrating the frequency of the output frequency of the high-speed oscillator by adopting a dichotomy progressive quick correction calibration algorithm comprises the following steps:
calibrating through a plurality of calibration periods; a binary progressive fast correction calibration is used in each calibration period so that the output frequency of the high speed oscillator is successively approximated to the expected frequency.
In the present application, the reference frequency is a, the frequency of the high-speed oscillator is b, the expected frequency is c, and the interval between b and c can be gradually narrowed through a plurality of dichotomy progressive fast correction calibrations, so that the frequency b output by the high-speed oscillator approaches c and is finally equal to c.
The method of the invention carries out calibration by using the dichotomy progressive quick correction calibration algorithm, fully utilizes the characteristics of the traditional dichotomy and improves the calculation efficiency.
After the calibration is completed, in order to improve the half-bit precision, in one embodiment, the method further comprises the following steps:
recording current _ stat _ cnt of the last two calibration periods, which are respectively marked as stat _ cnt [ BT _ MAX-1] and stat _ cnt [ BT _ MAX ]; and recording the corresponding Trim1 and Trim 2;
calculating to obtain a difference value A between stat _ cnt [ BT _ MAX ] and current _ stat _ cnt;
calculating the difference B between stat _ cnt [ BT _ MAX-1] and cur _ stat _ cnt;
comparing the sizes of A and B;
if A is smaller than B, determining Trim2 as the final Trim value of the calibration register;
if B is smaller than A, determining Trim1 as the final Trim value of the calibration register;
the cur _ stat _ cnt is the number of clock pulses of the high frequency oscillator in one calibration period.
The parameter of the calibration register, i.e. the Trim value, determines the magnitude of the output frequency of the high frequency oscillator. When the Trim value becomes larger, the output frequency of the high-speed oscillator is increased, and when the Trim value becomes smaller, the output frequency of the high-speed oscillator is reduced.
The present application also provides a calibration system for a high-speed oscillator, comprising: the system comprises an upper computer outside the SoC chip, a high-speed oscillator in the SoC chip and a calibration register in the SoC chip;
the upper computer is used for controlling the Soc chip to start calibration and receiving a final result;
the on-chip calibration register is used for storing Trim values after each calibration period is finished; sending the Trim value to an on-chip high-speed oscillator;
the on-chip high-speed oscillator is used for receiving the Trim value of each calibration period sent by the on-chip calibration register; updating the clock frequency according to the received Trim value and outputting the clock frequency to a digital circuit;
the OSC digital fast frequency calibration module is used for acquiring a reference frequency provided by the off-chip calibration auxiliary device; and the frequency of the output of the high-speed oscillator after digital calibration;
and calculating by adopting a dichotomy progressive quick correction calibration algorithm, and performing frequency calibration on the output frequency of the high-speed oscillator so as to enable the output frequency of the high-speed oscillator to be in line with expectation.
The frequency calibration module of the application adopts a dichotomy progressive quick correction calibration algorithm, supports configurable bit width parameterization of a calibration register Trim, and meets different SoC chip calibration error requirements; the digital calibration process of the on-chip high-speed oscillator can quickly find the reference frequency through dichotomy recursion judgment, and compared with an algorithm adopted by a frequency calibration module in the prior art, the method is simpler, the convergence speed is increased, and the calibration efficiency is increased.
Referring to fig. 2, the system includes an off-chip auxiliary calibration device, an on-chip I/O multiplexing management module, an OSC digital fast calibration frequency module, a calibration result decision device, an on-chip high-speed oscillator, and an embedded Flash.
The off-chip auxiliary calibration comprises an upper computer and a reference clock; the upper computer is provided with calibration software, establishes connection with the SOC chip, controls the chip to calibrate and receives a calibration result. The output frequency of the on-chip high-speed oscillator is calibrated through an OSC digital rapid calibration frequency module and a judgment algorithm, and the calibrated frequency value is checked to judge whether the requirement is met; if yes, storing the trim value into an embedded Flash memory in the chip; if not, returning an error flag bit to the upper computer, and controlling by an off-chip calibration auxiliary device to determine whether to continue calibration.
In one embodiment, the method further comprises: a calibration result decision device in the SoC chip;
the calibration result decision device is used for recording the last two times of current _ stat _ cnt which are respectively marked as stat _ cnt [ BT _ MAX-1] and stat _ cnt [ BT _ MAX ]; and recording the corresponding Trim1 and Trim 2;
calculating to obtain a difference value A between stat _ cnt [ BT _ MAX ] and current _ stat _ cnt;
calculating the difference B between stat _ cnt [ BT _ MAX-1] and cur _ stat _ cnt;
comparing the sizes of A and B;
if A is smaller than B, determining Trim2 as a Trim value of a calibration register;
if B is less than A, then Trim1 is determined as the calibration register Trim value.
In one embodiment, the system further comprises a Flash memory in the SoC chip, and the Flash memory is used for receiving the final Trim value sent by the upper computer.
In one embodiment, the calibration register has a bit width of 12 bits.
The method supports parameterization and configurability of the Trim bit width of the calibration register, and if the BT _ MAX is 8bit width, the error range of calibration can be controlled within 1%; if BT _ MAX is 12bit wide, the error range of calibration can be controlled within 0.1%.
In one embodiment, the upper computer is further configured to receive completion information sent by the SoC chip after the SoC chip is calibrated; and when the calibration is started, sending a command for starting the calibration to the chip.
The technical scheme of the invention is described in detail below
The off-chip auxiliary calibration device comprises an upper computer and an OSC calibration auxiliary low-speed clock providing device, wherein the upper computer is used for providing a reference clock, and can be a notebook computer or a PC; the upper computer is provided with a software operation interface, so that the operation is convenient; an operator can control the start of calibration by using an operation interface of the upper computer; and ending.
Comprises the following 3 steps
1) And a physical connection is established with the SoC chip on the Socket expansion board through a USB port of a desktop PC or a notebook computer and a USB-to-serial port adapter.
2) The off-chip OSC provides a low speed clock reference as a reference clock for two-stage digital calibration.
3) The PC starts calibration, completes the initialization process of the upper computer software and the SoC chip, and then the upper computer enters a receiving mode and waits for receiving response data; the Data responded is 1Byte Data _1 st;
if the Data _1st Data content is 0xAA, the calibration is successful, the upper computer sends a storage operation command, a digital circuit in the SoC converts the command into an eflash erase + eflash write operation, and writes the Trim value into an embedded Flash storage unit; if the Data _1st Data content is 0x55, it indicates that the calibration has failed.
Two, two-dichotomy progressive quick correction calibration
The signed binary number is stored in the calibration register, and the negative number is represented in complement form, and the most significant bit Trim [ BT _ MAX ] is the sign bit. When the sign bit is 1, the value of the calibration register of each calibration period is reduced by Trim [ BT _ MAX-1:0 ]; when the sign bit is 0, the calibration register value for each calibration period is incremented by Trim [ BT _ MAX-1:0 ].
The application provides and realizes a dichotomy progressive quick correction calibration algorithm to realize fine tuning of an on-chip high-speed oscillator so as to compensate an output clock. Referring to fig. 3, the clock generated by the on-chip high-speed oscillator is a fast clock, denoted as CLK _ F; the off-chip clock is a reference clock and is a slow clock and is marked as CLK _ S; after the slow clock and the fast clock are subjected to clock domain crossing synchronous processing, counting N × CLK _ F/CLK _ S clock cycles; n is 8 or 12; counting the number CLK _ F _ CNT of CLK _ F in 1 or a plurality of CLK _ S clock cycles; and calculating by adopting a dichotomy progressive quick correction calibration algorithm to obtain a final TRIM value. And then further checking is carried out, wherein the checking method is to count the calibration errors of the last two calibration registers, and the calibration is finished.
Marking the target value std _ stat _ cnt as N × CLK _ F/CLK _ S, counting a window block _ win by each CLK _ S, counting the CLK _ F as current _ stat _ cnt, and setting a flag bit after counting as a pulse signal block _ win _ end _ flag; the non-discrete characteristic of an analog device is considered, and a certain delay exists in the system; in order to ensure the accuracy of the statistical result, a certain fast clock domain signal stabilizing window is added in each statistical window. When block _ win _ end _ flag is valid, if current _ stat _ cnt is smaller than std _ stat _ cnt, the binary decision is determined as an upper half area, otherwise, the binary decision is determined as a lower half area; through dichotomy recursion judgment, the threshold value, namely the frequency standard value, can be quickly found, so that the efficiency is improved, and the method is simple.
In order to further improve the calibration accuracy, after the calibration is completed, the patent records the last two times of current _ stat _ cnt which are respectively recorded as stat _ cnt [ BT _ MAX-1] and stat _ cnt [ BT _ MAX ], and correspondingly, Trim values are respectively recorded as Trim1 and Trim 2. If the deviation between stat _ cnt [ BT _ MAX ] and current _ stat _ cnt is small, adopting Trim2 as a final Trim value of the calibration register; if the deviation between stat _ cnt [ BT _ MAX-1] and current _ stat _ cnt is small, Trim1 is used as the final Trim value of the calibration register. By the aid of the primary decision device, half bit precision of the calibration system can be further improved.
Although the invention has been described in detail above with reference to a general description and specific examples, it will be apparent to one skilled in the art that modifications or improvements may be made thereto based on the invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.
Claims (8)
1. A method for digital calibration of a high speed oscillator, comprising:
acquiring the reference frequency of the off-chip auxiliary calibration device; and the output frequency of the high-speed oscillator after calibration;
and according to the reference frequency, performing frequency calibration on the output frequency of the high-speed oscillator by using a dichotomy progressive quick correction calibration algorithm so as to enable the final output frequency of the high-speed oscillator to be in accordance with expectation.
2. The digital calibration method for a high-speed oscillator of claim 1, wherein the frequency calibration for the output frequency of the high-speed oscillator using a binary progressive fast correction calibration algorithm comprises:
calibrating through a plurality of calibration periods; a dichotomy progressive quick correction calibration algorithm is used in each calibration period, so that the output frequency of the high-speed oscillator is gradually approximated to the expected frequency.
3. A method for digital calibration of a high speed oscillator according to claim 1, wherein after calibration is complete, the method further comprises:
recording current _ stat _ cnt of the last two calibration periods, which are respectively marked as stat _ cnt [ BT _ MAX-1] and stat _ cnt [ BT _ MAX ]; and recording the corresponding Trim1 and Trim 2;
calculating to obtain a difference value A between stat _ cnt [ BT _ MAX ] and current _ stat _ cnt;
calculating the difference B between stat _ cnt [ BT _ MAX-1] and cur _ stat _ cnt;
comparing the sizes of A and B;
if A is smaller than B, determining Trim2 as the final Trim value of the calibration register;
if B is smaller than A, determining Trim1 as the final Trim value of the calibration register;
the cur _ stat _ cnt is the number of clock pulses of the high-speed oscillator in one calibration period.
4. A digital calibration arrangement for a high speed oscillator, comprising: the device comprises an off-chip auxiliary calibration device, an on-chip I/O multiplexing management module, an OSC digital fast frequency calibration module, a calibration result decision device, an on-chip high-speed oscillator and an embedded Flash;
the upper computer in the off-chip auxiliary calibration device is used for controlling the SoC chip to start calibration and receiving a status indication mark indicating whether the calibration result is successful or not;
the on-chip calibration register is used for storing Trim values after each calibration period is finished; sending the Trim value to an on-chip high-speed oscillator;
the on-chip high-speed oscillator is used for receiving the Trim value of each calibration period sent by the on-chip calibration register; updating the clock frequency according to the received Trim value and outputting the clock frequency to a digital circuit;
the OSC digital fast frequency calibration module is used for acquiring a reference frequency provided by the off-chip calibration auxiliary device; and the frequency of the output of the high-speed oscillator after digital calibration;
and calculating by adopting a dichotomy progressive quick correction calibration algorithm, and performing frequency calibration on the output frequency of the high-speed oscillator so as to enable the output frequency of the high-speed oscillator to be in line with expectation.
5. The digital calibration arrangement for a high-speed oscillator of claim 4, further comprising: a calibration result decision device in the SoC chip;
the calibration result decision device is used for recording the last two times of current _ stat _ cnt which are respectively marked as stat _ cnt [ BT _ MAX-1] and stat _ cnt [ BT _ MAX ]; and recording the corresponding Trim1 and Trim 2;
calculating to obtain a difference value A between stat _ cnt [ BT _ MAX ] and current _ stat _ cnt;
calculating the difference B between stat _ cnt [ BT _ MAX-1] and cur _ stat _ cnt;
comparing the sizes of A and B;
if A is smaller than B, determining Trim2 as a Trim value of a calibration register;
if B is less than A, then Trim1 is determined as the calibration register Trim value.
6. The digital calibration apparatus for a high-speed oscillator of claim 4, further comprising a Flash memory within the SoC chip for storing the digitally calibrated final Trim value.
7. A digital calibration arrangement for a high speed oscillator according to claim 4, characterized in that the bit width parameter of the calibration register is configurable, typically with 8 or 12 bits.
8. The digital calibration device of a high-speed oscillator according to claim 4, wherein the upper computer of the off-chip calibration auxiliary device is further configured to receive completion information sent by the chip after the SoC chip is calibrated; and when the calibration is started, sending a command for starting the calibration to the SoC chip.
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| CN112036103A (en) * | 2020-09-01 | 2020-12-04 | 深圳市傲立电子有限公司 | Device and method for processing multi-bit data from fast clock domain to slow clock domain |
| CN116094527A (en) * | 2023-04-07 | 2023-05-09 | 核芯互联科技(青岛)有限公司 | Integral differential modulator for eliminating walk-around spurious |
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| CN104133520A (en) * | 2014-07-29 | 2014-11-05 | 江苏宏云技术有限公司 | High-precision calibration method of oscillators in embedded processor chip |
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| CN111541450B (en) * | 2020-06-19 | 2024-01-30 | 小华半导体有限公司 | Clock automatic calibration circuit and method |
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| CN112036103B (en) * | 2020-09-01 | 2024-03-08 | 深圳市傲立电子有限公司 | Device and method for processing multi-bit data from fast clock domain to slow clock domain |
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