CN113467570B - Clock accurate calibration system and method for USB full-speed equipment chip - Google Patents
Clock accurate calibration system and method for USB full-speed equipment chip Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention relates to a clock accurate calibration system and a method of a full-speed USB equipment chip, wherein the system comprises the following components: USB equipment chip, MCU master control and crystal oscillator; the output end of the MCU master control is connected with the input end of the USB device chip, the output end of the USB device chip is connected with the input end of the MCU master control, and the MCU master control is also externally connected with the crystal oscillator. The invention can accurately correct the built-in clock frequency of the USB device chip by multiplexing the D+/D-pin and an additional pin of the USB device chip.
Description
Technical Field
The invention relates to the field of clock calibration, in particular to a clock accurate calibration system and method of a USB full-speed device chip.
Background
The frequency of the communication signal between the full-speed USB device and the host is 12MHz, the system clock frequency of a common full-speed USB device chip is 48MHz, the communication frequency error is required to be 2500PPM (0.25 percent) by the USB communication protocol, and once the communication frequency error exceeds the range, the USB communication failure can occur. Because of the manufacturing process deviation of the chip, it is difficult to achieve the clock frequency accurate enough, and in order to achieve the frequency, the following method is generally used:
an external crystal oscillator is adopted, a phase-locked loop (PLL) is utilized to multiply the frequency of a system clock, the frequency error of the external crystal oscillator can reach 30PPM and even lower, but the external crystal oscillator can additionally increase the application cost, and the starting time of the crystal oscillator can be longer;
when the USB is full-speed, D+ has a resistance of 1.5K, after the host is plugged in, the host detects that the full-speed device is plugged in, SOF packets (SOFs: frame first packets are sent by the USB host controller at the nominal rate of the full-speed bus every 1.00 ms+/-0.0005 ms) are sent for a period of time every 1ms, and the internal oscillator frequency of the chip is calibrated by using 1ms intervals of the SOF packets. Multiple SOFs are required to accurately calibrate the frequency. However, this method has the disadvantage that the interval time of the SOF sent by the host has some errors and is easily affected by the host, if there is external interference, or the number of SOF sent by the host is too small, if the calibration is still not accurate before the host sends the first instruction, the USB cannot perform normal communication.
The internal clock of the chip is corrected through the external crystal oscillator, and the correction data is stored in a memory in the chip, so that an additional correction communication interface is usually added, and the correction error is larger.
Disclosure of Invention
The invention aims to provide a clock accurate calibration system and method for a full-speed USB equipment chip, which can accurately correct the built-in clock frequency of the USB equipment chip.
In order to achieve the above object, the present invention provides the following solutions:
a clock accurate calibration system for a USB full-speed device chip, comprising:
USB equipment chip, MCU master control and crystal oscillator; the output end of the MCU master control is connected with the input end of the USB device chip, the output end of the USB device chip is connected with the input end of the MCU master control, and the MCU master control is also externally connected with the crystal oscillator.
Optionally, the MCU master control is in communication connection with the USB device chip through a USB/I2C interface.
Optionally, the USB device chip includes a USB/I2C communication module, a clock frequency adjustment module, a pin control module, and an OTP memory module;
the communication protocol of the USB/I2C communication module for switching the interface is USB or I2C; the clock frequency adjusting module is used for adjusting the clock frequency through an N bit register; the pin control module is used for switching the functions of pins through a register; the OTP storage module is used for storing corrected frequency data;
the MCU master control is respectively connected with the USB/I2C communication module and the pin control module, and the USB/I2C communication module is respectively connected with the OTP storage module, the clock frequency adjusting module and the pin control module; the clock frequency adjusting module is respectively connected with the OTP storage module and the pin control module.
A method for accurately calibrating a clock of a USB full-speed device chip, the method being used for calibrating a clock accurate calibration system of the USB full-speed device chip, comprising:
switching the interface of the MCU main control and the USB equipment chip into an I2C interface;
switching the pin function of the USB equipment chip into a frequency output function, and dividing the frequency by M times;
setting the value of a register of the clock frequency adjusting module to 0, and outputting X clock cycles by using a counting pin of the USB equipment chip by using crystal oscillator counting to obtain a first count value N1;
calculating the sum of the first periods of the X clocks according to the first count value N1, and marking the sum as T1;
setting the value of the register of the clock frequency adjusting module to 2 N 1, counting by using a crystal oscillator, outputting X clock cycles by a counting pin of a USB device chip, and obtaining a second counting value N2;
calculating the sum of the second periods of the X clocks according to the second count value N2, and marking the sum as T2;
calculating a configuration value Rsys of the clock frequency adjusting module according to the N1, the T1, the N2 and the T2;
changing the value of a register of the clock frequency adjusting module into the configuration value Rsys;
outputting X clock cycles by using a counting pin of the USB equipment chip by using crystal oscillator counting to obtain a third counting value Nreal;
acquiring a counting theoretical value of X clock cycles of a clock to be corrected, and recording the counting theoretical value as Nsys;
if the absolute value of the register of the clock frequency adjusting module is (Nreal/NSys) -1 is less than 0.1%, recording the value of the register of the clock frequency adjusting module, recording the value as Rreal, and switching the interface of the MCU main control and the USB equipment chip into a USB interface;
judging whether the communication of the USB device chip is normal, if so, completing clock calibration; if not, the step is skipped to the step of switching the interface of the MCU main control and the USB device chip to an I2C interface.
Optionally, the method further comprises:
if (Nreal/NSys) -1I is more than or equal to 0.1 percent and Nreal is more than NSys, adding 1 to the value of a register of the clock frequency adjusting module, and jumping to the step of using crystal oscillator counting, outputting X clock cycles by a counting pin of a USB device chip to obtain a third counting value Nreal';
otherwise, the value of the register of the clock frequency adjusting module is reduced by 1, and the step of using crystal oscillator counting is skipped, and the counting pin of the USB device chip outputs X clock cycles to obtain a third counting value Nreal.
Optionally, the first period sum of the X clocks is calculated by using the formula t1=tosc, where Tosc is the crystal oscillator period controlled by the MCU.
Optionally, the sum of the second periods of the X clocks is calculated by using the formula t2=tosc, where Tosc is the period of the crystal oscillator controlled by the MCU.
Alternatively, the formula rsys=2 is used N *(Tsysa-T1)/(T2-T1)＝2 N * And (NSys-N1)/(N2-N1) calculating the configuration value Rsys of the clock frequency adjusting module, wherein Tsysa is the sum of X clock cycles of the theoretical clock cycles, and NSys is the counting theoretical value of X clock cycles of the clock to be corrected.
Optionally, after the clock calibration is completed, the method further includes: and writing the Rreal into the OTP storage module through a USB interface, and reading the value to the clock frequency adjusting module when the USB equipment chip is powered on.
Optionally, the sum of the second periods T2< the sum of the first periods T1.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention corrects the internal clock of the USB device chip by using the external crystal oscillator, and the pin function is multiplexed under the condition of not increasing the pins of the chip, so that the frequency of the clock built in the chip is corrected accurately.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a clock accurate calibration system for a full-speed USB device chip of the present invention;
FIG. 2 is a flow chart of a method for precisely calibrating the clock of a full-speed USB device chip according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention aims to provide a clock accurate calibration system and method for a full-speed USB equipment chip, which can accurately correct the built-in clock frequency of the USB equipment chip.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Fig. 1 is a block diagram of a clock accurate calibration system of a full-speed USB device chip according to the present invention, as shown in fig. 1, a clock accurate calibration system of a full-speed USB device chip includes a USB device chip, an MCU master control, and a crystal oscillator, where the USB device chip includes a USB/I2C communication module, a clock frequency adjustment module, a pin control module, and an OTP memory module.
The MCU master control is in communication connection with the USB equipment chip through the USB/I2C interface, one pin output clock of the USB equipment chip is connected to the MCU master control, the MCU master control is externally connected with the crystal oscillator, and the MCU master control is connected with the USB/I2C communication module, the pin control module and the crystal oscillator; the USB/I2C communication module is connected with the OTP storage module, the clock frequency adjusting module and the pin control module; the clock frequency adjusting module is connected with the OTP storage module and the pin control module.
The USB/I2C communication module is used for switching the communication interface into USB or I2C, if the USB interface is adopted, USB communication is used, if the USB interface is adopted, I2C communication is used, and particularly, a pull-up resistor is used on the interface for distinguishing; the clock frequency adjusting module adjusts the clock frequency through an N bit register, wherein the larger the register value is, the faster the frequency is, and the clock frequency adjusting module is in a linear increasing mode, and the total is 2 N The seed frequency range, where the greater N, the more accurate the adjustment, the smaller the error, typically n=8; wherein the clock error is as low as 30PPM (PPM: parts per million, representing the deviation of the clock frequency from the nominal value) or even lower; the pin control module switches the functions of pins through a register, and the original functions (such as standard input/output, LED driving and the like) of the chip pins are switched with the output functions of the clock after M frequency division; the OTP memory module is used for storing corrected frequency data, and the power failure is avoided in the solidified chip.
Based on the system structure, the invention also provides a clock accurate calibration method of the USB full-speed device chip, as shown in figure 2, the specific implementation steps are as follows:
step 1: the MCU master control switches the interface into an I2C interface and pulls up communication signals D+ and D < - > of the chip end of the USB equipment; when the USB/I2C communication module in the chip detects that D+ and D < - > are both high level, the USB communication interface is converted into an I2C interface, D+ is converted into SCL (serial clock line), and D < - > is converted into SDA (serial data line); specifically, since the USB device chip pulls up a d+ and now passes through the d+/D-pull-up resistor, the communication interface at this time can be distinguished to be changed into an I2C interface for transmitting signals.
Step 2: the MCU master control sends an instruction by using an I2C interface, controls a pin control module, switches chip pin functions (such as standard input/output, LED driving and the like) into a frequency output function, divides the frequency by M times and outputs the frequency to a corresponding pin;
step 3: the MCU master control counts the value R1=0 of a register of the clock frequency adjusting module through the I2C interface, the MCU utilizes an external crystal oscillator to count the number of the clock output pins by X clock cycles to obtain a first count value N1, the sum of the number of the output pins by X cycles is calculated as T1=Tosc which is the crystal oscillator cycle of the MCU master control, and the higher the frequency of the crystal oscillator is, the smaller the correction error of the chip is;
step 4: MCU master control adjusts the value R2 = 2 of the register of the module through I2C interface N 1, the clock frequency adjusting module is linearly changed by a register, the frequency output by the pin is changed into T2 by dividing frequency M times, the output clock of the pin is counted for X clock cycles,obtaining a second count value of N2, and a sum of X periods t2=tosc N2; the output clock frequency of the clock frequency adjusting module increases linearly with the increase of the register, so T2<T1；
Step 5: calculating a configuration value Rsys corresponding to a register of the theoretical clock frequency adjusting module:
Rsys＝2 N *(Tsysa-T1)/(T2-T1)＝2 N *(Nsys-N1)/(N2-N1)，
wherein Tsysa is the sum of the theoretical clock period X clock periods, tsysa=tosc×nsys; nsys is a theoretical counting value of X clock cycles of a clock to be corrected under a crystal oscillator, nsys= (Tsys/Tosc) M X, N1 is a first counting value, T1 is a sum of the first cycles, N2 is a second counting value, T2 is a sum of the second cycles, tsys is a theoretical system clock cycle of a full-speed USB device chip, and a Rsys calculating value is written into a register of an internal clock frequency regulating module of the chip through an I2C interface;
step 6: the MCU master control counts the sum of X clock cycles output by the pins at the moment to obtain a third count value (the third count value is Nreal which is the actual count obtained under the current clock configuration value), the sum of X cycles Treal=tosc is Nreal, if the clock frequency error at the moment is within 1000PPM (Nreal/NSys) -1| <0.1%, the clock frequency register value Rreal at the moment is recorded, (wherein Rreal is the configuration value of the clock after final calibration, and the register value at the moment is recorded and stored after multiple times of calibration) and then the step 8 is carried out; otherwise, enter step 7;
step 7: if Nreal > Nys, adding 1 to the value of the register corresponding to the clock frequency adjusting module, and returning to the step 6; otherwise, the value of the register corresponding to the clock frequency adjusting module is reduced by 1, and the step 6 is returned;
step 8: the MCU master control firstly sends an instruction to restore the pin function to the original function, then disconnects a pull-up resistor on SCL and SDA, switches an interface to a USB interface, switches a USB/I2C communication module in the chip back to the USB interface communication at the moment, switches SCL back to D+ and switches SDA back to D-; the MCU master control sends a standard USB instruction to test USB communication, if the communication is normal, the internal clock correction of the chip is completed, and the step 9 is entered; returning to step 1 to try correction again if communication is abnormal;
step 9: and writing the clock frequency register value Rreal into an OTP storage module in the chip through a USB interface, so that the chip can read the value into a clock frequency adjusting module when the chip is electrified, and the clock frequency error in the chip after each electrification is ensured to be within 1000 PPM.
The invention also discloses the following technical effects:
1. and pins are multiplexed, so that the cost is lower.
2. And the clock is corrected according to theoretical calculation and actual counting results, so that the correction speed is high.
3. Before correction is completed, USB is used for communication trial, secondary correction is carried out, and the risk of correction errors is reduced.
4. Communication using a universal interface (USB/I2C, etc.), the application is simple.
5. And the internal clock of the chip is calibrated by utilizing the high-precision crystal oscillator, and the clock frequency calibration error is low.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; also, it is within the scope of the present invention to be modified by those of ordinary skill in the art in light of the present teachings. In view of the foregoing, this description should not be construed as limiting the invention.
Claims (6)
1. The clock accurate calibration method for the full-speed USB device chip is used for calibrating a clock accurate calibration system of the full-speed USB device chip and is characterized by comprising the following steps of:
USB equipment chip, MCU master control and crystal oscillator; the output end of the MCU main control is connected with the input end of the USB equipment chip, the output end of the USB equipment chip is connected with the input end of the MCU main control, and the MCU main control is also externally connected with the crystal oscillator;
the USB equipment chip comprises a USB/I2C communication module, a clock frequency adjusting module, a pin control module and an OTP storage module;
the communication protocol of the USB/I2C communication module for switching the interface is USB or I2C; the clock frequency adjusting module is used for adjusting the clock frequency through an N bit register; the pin control module is used for switching the functions of pins through a register; the OTP storage module is used for storing corrected frequency data;
the MCU master control is in communication connection with the USB equipment chip through a USB/I2C interface;
the MCU master control is respectively connected with the USB/I2C communication module and the pin control module, and the USB/I2C communication module is respectively connected with the OTP storage module, the clock frequency adjusting module and the pin control module; the clock frequency adjusting module is respectively connected with the OTP storage module and the pin control module;
the clock accurate calibration method of the USB full-speed equipment chip comprises the following steps:
switching the interface of the MCU main control and the USB equipment chip into an I2C interface;
switching the pin function of the USB equipment chip into a frequency output function, and dividing the frequency by M times;
setting the value of a register of the clock frequency adjusting module to 0, and outputting X clock cycles by using a counting pin of the USB equipment chip by using crystal oscillator counting to obtain a first count value N1;
calculating the sum of the first periods of the X clocks according to the first count value N1, and marking the sum as T1;
setting the value of the register of the clock frequency adjusting module to 2 N 1, counting by using a crystal oscillator, outputting X clock cycles by a counting pin of a USB device chip, and obtaining a second counting value N2;
calculating the sum of the second periods of the X clocks according to the second count value N2, and marking the sum as T2;
calculating a configuration value Rsys of the clock frequency adjusting module according to the N1, the T1, the N2 and the T2;
changing the value of a register of the clock frequency adjusting module into the configuration value Rsys;
outputting X clock cycles by using a counting pin of the USB equipment chip by using crystal oscillator counting to obtain a third counting value Nreal;
acquiring a counting theoretical value of X clock cycles of a clock to be corrected, and recording the counting theoretical value as Nsys;
if the absolute value of the register of the clock frequency adjusting module is (Nreal/NSys) -1 is less than 0.1%, recording the value of the register of the clock frequency adjusting module, recording the value as Rreal, and switching the interface of the MCU main control and the USB equipment chip into a USB interface;
judging whether the communication of the USB device chip is normal, if so, completing clock calibration; if not, jumping to the step of switching the interface of the MCU main control and the USB equipment chip to an I2C interface;
using the formula rsys=2 N *(Tsysa-T1)/(T2-T1)=2 N * And (NSys-N1)/(N2-N1) calculating the configuration value Rsys of the clock frequency adjusting module, wherein Tsysa is the sum of X clock cycles of the theoretical clock cycles, and NSys is the counting theoretical value of X clock cycles of the clock to be corrected.
2. The method for precisely calibrating a clock of a USB full-speed device chip of claim 1, further comprising:
if (Nreal/NSys) -1I is more than or equal to 0.1 percent and Nreal is more than NSys, adding 1 to a register value of the clock frequency adjusting module, and jumping to the step of using crystal oscillator counting, outputting X clock cycles by a counting pin of a USB device chip to obtain a third counting value Nreal';
otherwise, the register value of the clock frequency adjusting module is reduced by 1, and the step is skipped to' utilize crystal oscillator counting, the counting pin of the USB device chip outputs X clock cycles, and a third counting value Nreal is obtained.
3. The method for precisely calibrating the clock of the full-speed USB device chip of claim 1, wherein the sum of the first periods of the X clocks is calculated using the formula t1=tosc, N1, where Tosc is the period of the crystal oscillator controlled by the MCU.
4. The method of claim 1, wherein the second period sum of the X clocks is calculated using the formula t2=tosc N2, where Tosc is the period of the crystal oscillator controlled by the MCU.
5. The method for precisely calibrating a clock of a USB full-speed device chip of claim 1, further comprising, after the clock calibration is completed: and writing the Rreal into the OTP storage module through a USB interface, and reading the value to the clock frequency adjusting module when the USB equipment chip is powered on.
6. The method of claim 1, wherein the sum of the second periods T2 is less than the sum of the first periods T1.
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| Title |
|---|
| 工业机器人控制器与伺服驱动器LVDS通讯设计;范春健;韩斌;林永才;周根成;;制造业自动化(第04期);全文 * |
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| CN113467570A (en) | 2021-10-01 |
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