KR20030050944A - A semiconductor memory device with self refresh mode - Google Patents

Abstract

PURPOSE: A semiconductor memory device having a self refresh mode is provided to improve a refresh characteristic of the semiconductor memory device by measuring a period of the semiconductor memory device having a variable refresh period and tuning the refresh period. CONSTITUTION: A semiconductor memory device includes a data storage portion and a refresh period measurement portion(108). The refresh period measurement portion includes an unit period oscillator(202), a period multiplier(204), and a period measuring portion(206). The unit period oscillator generates a clock of an unit period to form a self refresh period. The period multiplier receives an output clock of the unit period oscillator and generates a clock of an MA period. The period measuring portion is enabled by the clock of the MA period in order to the clock received from the outside.

Description

A SEMICONDUCTOR MEMORY DEVICE WITH SELF REFRESH MODE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a refresh mode, and more particularly, to a semiconductor memory device having an internal refresh period measuring circuit for tuning a self refresh period.

A memory device is a generic term used for temporarily or permanently storing data or instructions used in a computer, a communication system, an image processing system, and the like, and include a semiconductor, a tape, a disk, and a light. The double semiconductor memory is again classified according to data storage method and electrical characteristics, such as DRAM, SRAM, Pseudo SRAM, FRAM, Flash Memory, and ROM. ROM).

These various types of semiconductor memories are classified into volatile memory and nonvolatile memory according to whether data is preserved when the external power is cut off. Volatile memories include DRAM, SRAM and pseudo SRAM. Nonvolatile memories include flash memory and ROM. Volatile memory is also classified according to whether the data is recharged. An SRAM cell is composed of a flip-flop circuit and two switches. Preservation is possible. In contrast, a DRAM cell is composed of a transistor that acts as a switch and a capacitor that stores charge (data). The "high" and "low" data are distinguished depending on whether or not the capacitor in the memory cell has no charge, that is, whether the terminal voltage of the capacitor is high or low.

The data is stored in the capacitor because the charge is accumulated, so there is no power consumption in principle. However, since the initial charge amount stored in the MOS transistor is leaked due to a leakage current such as a PN coupling, data may be lost. To prevent this, before data is lost, the data in the memory cell must be read and recharged back to the initial charge amount according to the read information. This operation must be repeated periodically to keep the data stored. This process of recharging the cell charge is called a refresh operation, and the refresh control is performed in a DRAM controller. At this time, the refresh can be classified into two types according to the operation method. First, there is an external refresh method for giving a refresh command from the DRAM controller. Second, only a refresh start signal is given from the DRAM controller. For example, there is a self refresh method that performs a refresh on its own inside the device until a refresh exit signal is received.

Self refresh periodically performs the refresh according to the internally determined cycle. At this time, the rewriting period (called the "refresh period") is determined by the capacity of the cell and the extinction time. The self-refresh cycle determined in this way is generated by an oscillator inside the device, and the oscillator may react sensitively to changes in the characteristics of semiconductor devices or semiconductor manufacturing process conditions, resulting in a certain degree of error. The oscillator's error can immediately affect the self-refresh cycle, resulting in a failure due to refresh, which leads to a reduction in production yield.

Accordingly, the present invention provides a semiconductor memory device which measures a refresh period by adding a circuit for measuring the refresh period internally in the semiconductor device to prevent a decrease in yield due to a change in the refresh period, and uses the same to tune the refresh period. The purpose is to provide.

1 is a diagram illustrating a connection relationship between a semiconductor device and a test device for measuring a self refresh period according to an embodiment of the present invention.

FIG. 2 is a block diagram of the refresh period measuring unit of FIG. 1. FIG.

3 is a circuit diagram of an example of a unit period oscillator of FIG.

4 is a circuit diagram of an example of the cycle multiplier of FIG.

5 is a circuit diagram of an example of a one bit counter of FIG.

6 is a circuit diagram of an example of the period meter of FIG.

7 is a circuit diagram of an example of the register control circuit of FIG.

8 is a circuit diagram of an example of the one bit register circuit of FIG.

9 is a block diagram of the data multiplexer and data output buffer of FIG.

FIG. 10 is a circuit diagram of an example of the one bit multiplexer circuit of FIG.

FIG. 11 is a signal waveform diagram illustrating the operation of the period meter of FIG. 6. FIG.

12 is a diagram illustrating a connection relationship between a semiconductor device and a test device for measuring a self refresh period according to another embodiment of the present invention.

FIG. 13 is a block diagram of the refresh period measuring unit of FIG. 12. FIG.

14 is a circuit diagram of an example of the period meter of FIG.

15 is a circuit diagram of an example of the register control circuit of FIG.

16 is a signal waveform diagram illustrating an operation of the register control circuit in FIG. 15.

In order to achieve the above object, the present invention provides a semiconductor memory device having a self refresh mode, wherein the semiconductor memory device includes a data storage unit and a refresh cycle measuring unit, and the refresh cycle measuring unit is configured to create a self refresh cycle. A unit cycle oscillator for generating a clock having a unit cycle A, a periodic multiplier for receiving a output clock of the unit cycle oscillator and generating a clock having a period of MA, and a clock of the cycle MA. It is characterized in that it comprises a period meter which is enabled by the counting the clock input from the outside. In addition, it is preferable to further include a clock buffer which is enabled by a control signal input from the outside to provide the external clock to the period measuring device. In addition, it is preferable to further include a data multiplexer for outputting the count value of the period meter in the periodic measurement mode, and outputting the output value of the data storage unit in the normal mode.

The periodic multiplier consists of a plurality of 1-bit counters connected in series, the plurality of 1-bit counters are enabled together by a test mode signal input from the outside, and the unit cycle oscillator is included in the least significant bit of the plurality of counters. The output clock of is input.

The period measuring device includes a plurality of one-bit counters connected in series. The plurality of one-bit counters are enabled by a clock of the period MA, and the external clock is input to a counter of the least significant bit of the plurality of counters. The period measuring device preferably starts counting the external clock on the rising edge of the clock of the period MA and outputs the value counted on the falling edge.

In another aspect, the present invention provides a semiconductor memory device having a self refresh mode, wherein the semiconductor memory device includes a data storage unit and a refresh cycle measuring unit, and the refresh cycle measuring unit has a unit cycle A for creating a self refresh cycle. The apparatus may further include a unit period oscillator for generating a clock, and a period meter for enabling the clock of the unit period to be enabled by an external control signal.

According to the configuration of the present invention as described above, the semiconductor memory device by measuring the period of the semiconductor memory devices having a non-constant refresh cycle according to the manufacturing process variable of the semiconductor memory device, thereby tuning the refresh cycle to have a constant refresh cycle The refresh characteristics of the device can be guaranteed. In addition, the production efficiency can be improved by reducing the failure due to the refresh characteristics during mass production.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; In the drawings, the same reference numerals are used to refer to the same or similar components and signals for the sake of consistency of description.

1 is a diagram illustrating a connection relationship between a semiconductor device and a test device for measuring a self refresh period according to an embodiment of the present invention. As shown in FIG. 1, the test device 104 provides an external clock signal extclk and a test mode control signal TM to the semiconductor memory device 102 to measure the self refresh period. The semiconductor memory device 102 includes not only the data storage unit 106 but also the refresh period measurement unit 108 internally. When the test mode control signal TM is received from the test device 104, the self refresh cycle test is enabled in the semiconductor memory device 102, and the semiconductor memory device 102 based on the external clock signal extclk as a measurement reference. Self-refresh cycle is measured. The measured period is fed back to the test apparatus 104 as binary data Data_out. The test device 104 determines the acceleration / decrease of the refresh cycle based on the measurement data Data_out to tune the refresh cycle of the semiconductor memory device 102 through a method such as fuse cutting.

FIG. 2 is a block diagram of the refresh period measuring unit of FIG. 1. As shown in FIG. 2, the refresh period measuring unit 108 includes a unit period oscillator 202, a period multiplier 204, a period meter 206, a data mux and an output buffer 208, and a clock buffer 210. Consists of The unit period oscillator 202 generates a clock having a unit period (A) s as a period for making a self refresh period and provides it to the period multiplier 204. The periodic multiplier 204 receives the output clock of the unit period oscillator 202 to generate a clock having a period of (nA) s, (2nA) s and provides it to the period meter 206. This clock generation in the cycle multiplier 204 is enabled by the application of the test mode control signal TM from the test apparatus 104 of FIG. 1. The period meter 206 measures the period of the period 2nA clock by counting a clock extclk that is enabled by the clock of the period 2nA and input from the outside. The external clock buffer 210 is enabled by the test mode control signal TM to buffer the external clock signal extclk and provide it to the period meter 206 as a clock Clock_i. The data multiplexer and output buffer 208 are enabled by the test mode control signal TM. The data multiplexer and the output buffer 208 binaryize the count value of the period meter 206 in the refresh period measurement mode in which the test period control signal TM becomes a high level and the refresh period measurement unit 108 of FIG. 1 is enabled. In the normal mode in which the data is output as data Data_out and the test mode control signal TM is at a low level and the refresh period measuring unit 108 of FIG. 1 is disabled, the output value of the data storage unit 106 of FIG. 1 Normal_data_out )

Next, the operation of the period measuring unit 108 will be described. First, the unit period generator 202 generates a clock of unit periods (A) s for creating a refresh period. The unit cycle signal generated by the unit cycle generator 202 generates a periodic signal of (nA) s and (2nA) s through the cycle multiplier 204. At this time, the enable signal of the cycle multiplier 204 is used as a test device. The test mode control signal TM applied at 104 is used. The clock signals produced by the period multiplier 204 are used as inputs of the period meter 206. The period meter 206 measures the period of the period signal provided from the period multiplier 204 based on the clock Clock_i provided from the external clock buffer 210 enabled by the test mode control signal TM. The measured value is converted into N bits of binary data and sent to the test apparatus 104 via the data multiplexer and the output buffer 208. Here, the number of bits N of the measured value is determined by the period tuning offset value, the relationship between the external clock extclk and the refresh period, and the tuning range.

3 is a circuit diagram of an example of a unit period oscillator of FIG. 2. As shown in FIG. 3, the unit period oscillator 202 may include a ring oscillator 300 formed of an inverter 302 and a delay element 304. The unit period oscillator 202 generates and outputs a unit period signal having a period (A) s. The refresh period is an integer multiple of this unit period.

4 is a circuit diagram of an example of the cycle multiplier of FIG. 2. As shown in Fig. 4, the cycle multiplier 204 is composed of a plurality of one-bit counters 402 connected in series, which are connected by a test mode control signal TM input from the outside. It is enabled together. The output clock of the unit period oscillator 202 is input to the least significant bit counter 402a of the plurality of 1-bit counters 402. The low bit counter 402a generates a periodic signal having a period of (2A) s and provides it to the next low bit counter 402b. Counter 402b generates a periodic signal with a period of (4A) s, counter 402c generates a periodic signal with a period of (8A) s, and counter 402d generates a periodic signal with a period of (16A) s. And a counter 402e generates a periodic signal whose period is (32A) s. Through this process, a periodic signal having a desired period is obtained.

5A is a circuit diagram of an example of the 1-bit counter of FIG. 4, and FIG. 5B is an operational waveform diagram of the circuit of FIG. 5A. In Fig. 5, the output Cn-1 of the counter of the previous stage is used as an input, and the output Cn of this counter 500 is used as the input of the counter of the next stage. As the enable signal Enable, as previously mentioned in FIG. 4, the test mode control signal TM provided from the test apparatus 104 of FIG. 1 is used. If the enable signal Enable is low level, the output Cn remains low. If the enable signal Enable becomes high, it is like a T flip-flop toggled by the falling edge of the input Cn-1. It will work. The operating waveform is as shown in Figure 5b.

6 is a circuit diagram of an example of the period meter of FIG. 2. As shown in FIG. 6, the period meter 206 consists of an N bit binary counter 602, an N bit register 604, and a register control circuit 608. N-bit binary counter 602 consists of a plurality of one-bit counters 606 connected in series. The least significant bit counter 606a is provided with a clock Clock_i from an external clock buffer (210 in FIG. 2). The bit counter 606a generates a clock P_data_in <0> having a period twice as large as the clock Clock_i and provides it to the next bit counter 606b and the N bit register 604. The bit counter 606b receives the clock P_data_in <0> as an input, generates a clock P_data_in <1> having a period twice as large as the clock P_data_in <0>, and generates the clock P_data_in <1>. The next stage is provided to the bit counter 606c and the N bit register 604. Similarly, the bit counter 606c generates a clock P_data_in <2>, the bit counter 606d generates a clock P_data_in <3>, and the bit counter 606d generates a clock P_data_in <4>, respectively. The bit register 604 and the bit counter of the next stage are provided. All one-bit counters 606 that make up the period measurement block 602 are enabled by the signal of period 32As provided from the period multiplier (204 of FIG. 2) in this embodiment. Therefore, the clock Clock_i is started counting on the rising edge of the signal of the period 32As, the counting of the clock Clock_i ends on the falling edge, and the count value at the end point is used as the signal P_data_in. To register 604. The N bit register 604 latches the signal P_data_in and outputs it as the signal P_data_out. The register control circuit 608 controls the N bit register 604 by using the period 16As signal and the period 32As signal generated by the cycle multiplier 204 in this embodiment (Reset, Onb_off). )

Next, the operation of the period meter 206 will be described. First, since the N-bit binary counter 602 needs to operate only for the period to be measured, the enable signal of the N-bit binary counter 602 is generated using the multiplied period of the measurement period. The binary data P_data_in measured at the counter 602 is stored in the N bit register 604. The N bit register 604 exports the stored data as a signal P_data_out for a predetermined time through the data multiplexer and the data buffer 208 of FIG. 2, and then generates a reset signal generated by the register control circuit 608. Reset). The transmission time of the signal P_data_out is set to a time sufficient to receive a signal from an external device. The signal for controlling this is made using a periodic signal to be measured in the present invention.

FIG. 7 is a circuit diagram of an example of the register control circuit of FIG. 6. As shown in FIG. 7, the register control circuit 608 is composed of an inverter 702, a NOR gate 704, a pulse generator 706, and an inverter 708. In FIG. 7, the control signal Onb_off is generated by inverting the signal having the period 32As by the inverter 708. For example, if you want to measure the period of (16A) s, use the (32A) s signal to enable the binary counter (602 in FIG. 6), output the measurement result for (8A) s after the period measurement, and reset And generates a signal Reset to reset the N bit register (604 in FIG. 6).

FIG. 8 is a circuit diagram of an example of the one bit register circuit of FIG. 6. The N bit register (604 in FIG. 6) is made up of N one bit register circuits 800 having such a configuration. As shown in FIG. 8, the transmission gate 802 receives the output P_data_in <n> of the binary counter (602 of FIG. 6) as an input, and a control signal generated from the register control circuit 608 of FIG. It is controlled by the signal of (Onb_off) and period (32A) s. Therefore, the transfer gate 802 sends the output P_data_in <n> of the binary counter (602 of FIG. 6) to the output terminal only when the signal of the period 32As is at the high level. The NMOS transistor 804 in which the reset signal Reset generated from the register control circuit 608 of FIG. 6 is input to the gate is configured to make the node aa low while the reset signal Reset is at a high level. Reset the register circuit 800. The latch 806 serves to maintain the level of node aa, and the inverter 808 is for generating an output P_data_out <n> having the same level as the input P_data_in <n>.

9 is a block diagram of the data multiplexer and data output buffer of FIG. 2. As shown in FIG. 9, in the data multiplexer 902, data P_data_out <n>, which is a result of the refresh period measurement, and normal data (Normal_data_out <n) output from the data storage unit 106 of FIG. >) Is input, and a normal mode enable signal NEN and a test mode control signal TM are input to the select terminal select. The normal mode enable signal NEN and the test mode control signal TM do not go high at the same time. The normal mode enable signal NEN is generated by a memory controller (not shown), and the test mode control signal TM is generated from the test apparatus 104 of FIG. 1 as described with reference to FIG. 1. The data multiplexer 902 selects data to be sent to the outside through the data output buffer 904, in order to write the data output buffer 904 to the data in the normal mode and the data in the periodic test mode. The operation of the data multiplexer 902 is that data P_data_out <n> is sent to the data output buffer 904 when in the periodic test mode, and data (Normal_data_out <n>) is sent to the data output buffer 904 when in the normal mode. Is sent. In FIG. 9, the signal Mux_out_ <n> represents the output of the data multiplexer 902, and the signal Data_out_ <n> represents the output of the data output buffer 904, respectively. As shown in FIG. 9, the data output buffer 904 is enabled by the test mode control signal TM.

10 is a circuit diagram of an example of the 1-bit multiplexer circuit of FIG. 9. As shown in FIG. 10, the 1-bit multiplexer circuit 1000 consists of transmission gates 1002, 1004, latch 1006, and inverter 1008. The transfer gate 1002 is controlled by the test mode control signals TM and TM_b, and passes the period measurement data P_data_out <n> when the test mode control signal TM is at a high level. The signal TM_b is a signal in which the signal TM is inverted by an inverter (not shown). The transfer gate 1004 is controlled by the normal mode enable signals NEN and NEN_b, and passes the normal data Normal_data_out <n> when the normal mode enable signal NEN is at a high level. The signal NEN_b is a signal in which the signal NEN is inverted by an inverter (not shown). In the periodic test mode in which the test mode control signal TM is at the high level, the period measurement data P_data_out <n> is latched to the output Mux_out <n>, and the normal mode enable signal NEN is at the high level. In the normal mode, the output data Normal_data_out <n> of the memory storage unit 106 of FIG. 1 is latched to the output Mux_out <n>. The test mode control signal TM and the normal mode enable signal NEN do not go high at the same time.

FIG. 11 is a signal waveform diagram illustrating an operation of the period meter of FIG. 6. In Fig. 11, signal N16 denotes a periodic signal having a period of (16A) s, and signal N32 denotes a periodic signal of a period of (32A) s. In addition, time ta indicates a measurement target period, time tb indicates a period measurement period, time tc indicates a period during which the period measurement result is output, and time td indicates a period during which the reset is performed.

12 is a diagram illustrating a connection relationship between a semiconductor device and a test device for measuring a self refresh period according to another embodiment of the present invention. The semiconductor memory device 1202 includes a data storage unit 1202 for outputting data in a normal mode and a refresh cycle measurement unit 1208 for measuring a refresh cycle of the semiconductor memory device 1202. In this embodiment, as shown in FIG. 12, only the test mode control signal TM is provided to the semiconductor memory device 1202 from the test device 1204. In the embodiment shown in FIG. 1, the test device 104 provides the semiconductor memory device 102 with the external clock signal extclk as well as the test mode control signal TM. The data Data_out which is the result of the refresh cycle measurement in the semiconductor memory device 1202 is provided to the test device 1204 from the semiconductor memory device 1202.

FIG. 13 is a block diagram of the refresh period measuring unit of FIG. 12. As shown in FIG. 13, the refresh period measuring unit 1300 includes a unit period oscillator 1302, a period measuring unit 1304, a data multiplexer, and a data output buffer 1306. The unit period oscillator 1302 is enabled by the test mode control signal TM generated from the test apparatus 1204 of FIG. 12 to generate a signal of period (A) s which is a unit period for creating a refresh period. The periodic signal is provided to a periodic meter 1304. The period measuring unit 1304 is also enabled by the test mode control signal TM, measures the refresh period of the semiconductor memory device 1202 by inputting the unit period signal provided from the unit period oscillator 1302, and measures the measurement result. The signal P_data_out is provided to the data multiplexer and the data output buffer 1306. The data multiplexer and the data output buffer 1306 are also enabled by the test mode control signal TM, and are output from the periodic measurement data P_data_out provided from the period meter 1304 and the data storage unit 1202 of FIG. 12. (Normal_data_out) is selectively output as the output signal Data_out in accordance with the test mode control signal TM.

Compared to the refresh period measuring unit 108 of FIG. 2, the period measuring unit 206 receives the clock Clock_i from the clock buffer 210, but the period measuring unit 1304 is the unit period oscillator 1302. The output of is taken directly as input. The period meter 206 also uses the output of the cycle multiplier 204 as an enable signal, but the period meter 1304 receives the test mode control signal TM directly as an enable signal.

FIG. 14 is a circuit diagram of an example of the period meter of FIG. 13. As shown in FIG. 14, the period meter 1304 includes an N bit binary counter 1402, an N bit register 1404, and a register control circuit 1406. The N bit binary counter 1402 can be configured by having N one bit binary counters 1408 connected in series. The distinction compared to the period meter 206 of FIG. 6 is that the binary counter 602 and the register control circuit 608 of the period meter 206 are enabled by the output of the period multiplier (204 of FIG. 2), The binary counter 1402 and the register control circuit 1406 of the period meter 1304 are directly enabled by the test mode control signal TM.

FIG. 15 is a circuit diagram of an example of the register control circuit of FIG. 14, and FIG. 16 is a signal waveform diagram illustrating the operation of the register control circuit shown in FIG. 15. As shown in FIG. 15, the register control circuit 1406 may consist of a pulse generator 1502 and an inverter 1504. The input signal of the register control circuit 1406 is a test mode control signal TM. The reset signal Reset is generated as a short pulse on the rising edge of the test mode control signal TM, as shown in FIG. 16, and before the binary counter (1402 of FIG. 14) starts counting. 1404). The N bit register 1404 is reset at the time of disable, i.e., after passing the period measurement data P_data_out to the data multiplexer and the output Data_out of the output buffer 1306, without making the reset signal at test mode enable. You can also create a reset signal.

The embodiments described herein are merely intended to enable those skilled in the art to easily understand and practice the present invention, and are not intended to limit the scope of the present invention. Therefore, those skilled in the art should note that various modifications or changes are possible within the scope of the present invention. The scope of the invention is defined in principle by the claims that follow.

According to the configuration of the present invention, the semiconductor memory device by measuring the period of the semiconductor memory device having a non-constant refresh cycle according to a variable in the manufacturing process of the semiconductor memory device, thereby tuning the refresh cycle to have a constant refresh cycle The refresh characteristics of the device can be guaranteed. In addition, production efficiency can be improved by reducing failure due to refresh characteristics during mass production.

Claims (7)

In a semiconductor memory device having a self refresh mode, The semiconductor memory device includes a data storage unit and a refresh cycle measurement unit. The refresh period measuring unit A unit period oscillator for generating a clock having a unit period A as a period for making a self refresh period, A period multiplier for receiving the output clock of the unit period oscillator and generating a clock having a period of MA; A period meter which is enabled by the clock of the period MA and counts a clock input from the outside; A semiconductor memory device having a self refresh mode. The method of claim 1, The period multiplier is composed of a plurality of 1-bit counters connected in series, the plurality of 1-bit counters are enabled together by a test mode signal input from the outside, and the unit period is included in the least significant bit of the plurality of counters. A semiconductor memory device having a self refresh mode, characterized in that an output clock of an oscillator is input. The method of claim 1, The period measuring device includes a plurality of 1-bit counters connected in series, the plurality of 1-bit counters are enabled by a clock of the period MA, and the external clock is input to a counter of the least significant bit of the plurality of counters. A semiconductor memory device having a self refresh mode. The method of claim 3, wherein And the period measuring device starts counting the external clock at the rising edge of the clock of the period MA and outputs the value counted at the falling edge. The method of claim 1, And a clock buffer unit which is enabled by a control signal input from an external device and provides the external clock to a period measuring device. The method of claim 1, And a data multiplexer for outputting a count value of the period meter in a periodic measurement mode, and outputting an output value of the data storage unit in a normal mode. In a semiconductor memory device having a self refresh mode, The semiconductor memory device includes a data storage unit and a refresh cycle measurement unit. The refresh period measuring unit A unit period oscillator for generating a clock having a unit period A as a period for making a self refresh period, A period meter which is enabled by a control signal from an external device and counts a clock of the unit period A semiconductor memory device having a self refresh mode.