CN111918046A - Novel movie server control display system - Google Patents
Novel movie server control display system Download PDFInfo
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- CN111918046A CN111918046A CN202010800735.8A CN202010800735A CN111918046A CN 111918046 A CN111918046 A CN 111918046A CN 202010800735 A CN202010800735 A CN 202010800735A CN 111918046 A CN111918046 A CN 111918046A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/12—Picture reproducers
- H04N9/31—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/12—Picture reproducers
- H04N9/31—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM]
- H04N9/3141—Constructional details thereof
- H04N9/315—Modulator illumination systems
Abstract
The invention discloses a novel movie server control display system, which comprises a sending end and a receiving end, wherein the sending end comprises a receiving and conversion front end X ' Y ' Z ' signal module, a DDR signal segmentation processing module, a 12bit 16bit lifting module and an SFP transmission module, the receiving end comprises an SFP receiving module, a signal processing module, a receiving card module and a box body (an LED screen), the sending end also comprises an FPGA, a DDR, a data conversion module and an optical fiber interface module, the FPGA comprises a plurality of BANKs, one BANK comprises a plurality of groups of SerDes, each group of SerDes comprises two pins, and the transmission rate of each SerDes pin is not less than 16.3 Gb/s; the receiving end comprises a box body and a connecting plate, the box body comprises a receiving card and a cascade module, and the connecting plate comprises an optical fiber interface module and a DDR for signal data processing. Compared with the traditional projection playing mode, the self-luminous characteristic of the LED screen can perfectly restore the single color of 12 bits, and meanwhile, the color and the brightness of the display picture of the LED screen conform to the DCI authentication standard by adapting the signal parameters of the LED screen through the receiving card.
Description
Technical Field
The invention relates to the technical field of a movie server control display system, in particular to a novel movie server control display system.
Background
The common film server is in a projection mode, the gray scale is difficult to reach 12 bits, the video playing effect cannot reach high quality, the server is not easy to perform later maintenance, once a projection head is damaged, the whole replacement is required, the time is consumed, and the maintenance cost is high.
Disclosure of Invention
The invention aims to provide a novel movie server control display system to solve the problems that an ordinary movie server is in a projection mode, the gray scale is difficult to reach 12 bits, the video playing effect cannot reach high quality, the server is not easy to perform later maintenance, once a projection head is damaged, the whole movie server needs to be replaced, time is consumed, and the maintenance cost is high.
In order to achieve the purpose, the invention provides the following technical scheme: a new film server control display system comprises a sending end and a receiving end, wherein the sending end comprises a front end X ' Y ' Z ' signal receiving and converting module, a DDR signal segmentation processing module, a 12bit 16bit increasing module and an SFP transmission module, and the receiving end comprises an SFP receiving module, a signal processing module, a receiving card module and a box body (an LED screen);
the transmitting end further comprises an FPGA, a DDR, a data conversion module and an optical fiber interface module, wherein the FPGA comprises a plurality of BANKs, one BANK comprises a plurality of groups of SerDes, each group of SerDes comprises two pins, and the transmission rate of each SerDes pin is not less than 16.3 Gb/s;
the receiving end further comprises a box body and a connecting plate, the box body comprises a receiving card and a cascade module, and the connecting plate comprises an optical fiber interface module and a DDR for signal data processing.
Further, the front end 50G data DDR through 2400MHz 64bit parameters access, divided into 16 groups of data to 156MHz 32bit parameters sent to the receiving end.
Furthermore, the DDR clock circuit and the basic clock are 100MHz, and 2400MHz can be achieved through a frequency multiplication mode.
Further, the sending end receives 4K 120Hz video data sent by the server to the FPGA through the 8-channel SerDes, the FPGA receives 50Gbps video data, then the video data is transmitted to the DDR4 through the data conversion module, the data is cached, read and divided into 16 groups of data, and then the data is transmitted to the 12-bit 16-bit module, the 16 groups of data are transmitted to the optical fiber interface module after 16-bit, and an optical fiber port of the optical fiber interface module is distributed to the receiving card end;
wherein, each channel transmits data of 6.25G, and 8 channels transmit data of 50G in total.
Furthermore, the front end X ' Y ' Z ' signal receiving and converting module is an FPGA receiving signal source, and the signals are converted into RGB signals through the data converting module.
Further, the SFP interface is communicatively coupled to the SerDes.
Furthermore, the receiving card is adapted to the signal parameters of the LED screen, and the display picture of the LED screen meets the DCI authentication standard. Compared with the prior art, the invention has the beneficial effects that:
this kind of new film server control display system, realized booth apart from LED screen broadcast film server content, compare in traditional projection play mode, LED screen self-luminous characteristics, can perfectly restore monochromatic 12 bit's picture, the optical fiber grouping transmission mode who adopts combines DDR's three buffer memory storage techniques, the signal of transmissible 4K 120HZ, and then it is higher to reach video broadcast effect quality, and convenient maintenance in later stage, avoid projecting the head to damage whole change, and then save time and reduce the cost.
Drawings
FIG. 1 is a schematic block diagram of a new motion picture server control display system in accordance with the present invention;
FIG. 2 is a diagram of transmission rates of various links of a movie server control display system according to the present invention;
FIG. 3 is a circuit diagram of a DDR clock circuit of the new motion picture server control display system of the present invention;
FIG. 4 is a circuit diagram of a new SFP interface circuit of the movie server control display system;
FIG. 5 is a schematic diagram of one BANK pin of the FPGA of the present invention;
FIG. 6 is a circuit diagram of a SerDes connection circuit of the present invention;
FIG. 7 shows the DCI authentication color and brightness criteria of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the first embodiment, the first step is,
as shown in fig. 1-7, in the embodiment of the present invention, a new movie server control display system includes a sending end 2 and a receiving end 1, where the sending end 2 includes a front end X ' Y ' Z ' signal receiving and converting module, a DDR signal dividing and processing module, a 12-bit up-to-16-bit module, and an SFP transmission module, and the receiving end 1 includes an SFP receiving module, a signal processing module, a receiving card module, and a box (LED screen);
as shown in fig. 5 and 6, the transmitting end 2 further includes an FPGA, a DDR, a data conversion module, and an optical fiber interface module, where the FPGA includes a plurality of BANKs, one BANK includes a plurality of sets of SerDes, each set of SerDes includes two pins, and a transmission rate of each SerDes pin is not less than 16.3 Gb/s;
wherein, FPGA: the semi-custom circuit belongs to a special integrated circuit, is a programmable logic array, and has a basic structure comprising a programmable input/output unit, a configurable logic block, a digital clock management module, an embedded block RAM, a wiring resource, an embedded special hard core and a bottom embedded functional unit.
DDR: DDR SDRAM, commonly called DDR, is an abbreviation of Double Data Rate SDRAM, which is a Double Rate synchronous dynamic random access memory.
A SerDes: the abbreviation of SERializer (SERializer) or desrializer (DESerializer) is used.
SFP: english is: a Small Form-factor plug is an interface device that converts an electrical signal into an optical signal.
The receiving end 1 further comprises a box body and a connecting plate, the box body comprises a receiving card and a cascade module, and the connecting plate comprises an optical fiber interface module and a DDR for signal data processing.
Wherein, the receiving card is a 16-path receiving card, and the xilinx high-speed SerDes interface is adopted to realize signal transmission.
In this embodiment, as shown in fig. 1, a sending card receives 4K 120Hz video data sent by a server through an 8-channel SerDes, each channel transmits 6.25G of data, 8 channels together are 50G of data, after receiving 50Gbps of video data, an FPGA stores the video data in DDR4 by using a triple-cache storage technology, then reads and divides the video data into 16 groups of data, and simultaneously distributes the data to a receiving card end from 16 optical fiber ports for processing 12-bit image data, or transmits point-by-point correction data of a screen body and module configuration parameters to a corresponding module.
As shown in fig. 2, the front end 50G data, DDR is accessed by 2400MHz 64bit parameter, and is divided into 16 groups of data, which are transmitted to the receiving end 1 by 156MHz 32bit parameter.
As shown in FIG. 3, the DDR clock circuit, the basic clock is 100MHz, and 2400MHz can be reached by means of frequency multiplication.
The sending end 2 receives 4K 120Hz video data sent by a server through an 8-channel SerDes to the FPGA, the FPGA receives 50Gbps video data, then the video data is transmitted to the DDR4 through a data conversion module, the data is cached and read, the data is divided into 16 groups of data and then transmitted to a 12-bit 16-bit module, the 16 groups of data are transmitted to an optical fiber interface module after being 16-bit, and an optical fiber port of the optical fiber interface module is distributed to a receiving card end;
wherein, each channel transmits data of 6.25G, and 8 channels transmit data of 50G in total.
As shown in fig. 4, the front end X ' Y ' Z ' signal receiving and converting module is an FPGA signal receiving source, converts the signal into an RGB signal through the data converting module, and the SFP interface is in communication connection with the SerDes.
The invention uses the small-spacing LED screen to play the film on the film server, replaces the traditional projection mode to play the film, can ensure that the film playing effect of the film server is better, has single color gray scale of 12bit, and is suitable for the field with ultrahigh definition and requirement on the playing effect.
To sum up, this kind of new film server control display system has realized that booth is apart from LED screen broadcast film server content, compares in traditional projection play mode, and the self-luminous characteristics of LED screen can perfect the monochromatic 12 bit's of reduction picture, and the optical fiber grouping transmission mode who adopts combines DDR's three buffer memory storage techniques, but 4K 120 HZ's signal of transmission, and then it is higher to reach the video playback effect quality, and convenient maintenance in later stage, avoids projecting the head to damage whole change, and then saves time and reduce the cost.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (7)
1. A new film server control display system is characterized by comprising a sending end and a receiving end, wherein the sending end comprises a front X ' Y ' Z ' signal receiving and converting module, a DDR signal segmentation processing module, a 12bit 16bit increasing module and an SFP transmission module, and the receiving end comprises an SFP receiving module, a signal processing module, a receiving card module and a box body;
the transmitting end further comprises an FPGA, a DDR, a data conversion module and an optical fiber interface module, wherein the FPGA comprises a plurality of BANKs, one BANK comprises a plurality of groups of SerDes, each group of SerDes comprises two pins, and the transmission rate of each SerDes pin is not less than 16.3 Gb/s;
the receiving end further comprises a box body and a connecting plate, the box body comprises a receiving card and a cascade module, and the connecting plate comprises an optical fiber interface module and a DDR module for signal data processing.
2. The system as claimed in claim 1, wherein the front end 50G data, DDR, is accessed via 2400MHz 64bit parameter, and is divided into 16 groups of data to be transmitted to the receiving end via 156MHz 32bit parameter.
3. The system as claimed in claim 1, wherein the DDR clock circuit, the basic clock 100MHz, is multiplied by 2400 MHz.
4. The system of claim 1, wherein the sending end receives 4K 120Hz video data from the server via an 8-channel SerDes to the FPGA, the FPGA receives 50Gbps video data, then the FPGA sends the video data to the DDR4 for buffering, reading, dividing into 16 groups of data, and sending the data to the 12-bit 16-bit module, the 16 groups of data being 16-bit module, and sending the data to the fiber interface module, and the fiber interface of the fiber interface module is distributed to the receiving card end;
wherein, each channel transmits data of 6.25G, and 8 channels transmit data of 50G in total.
5. The system as claimed in claim 1, wherein the front-end X ' Y ' Z ' signal receiving and converting module is an FPGA signal receiving source, and converts the signal into RGB signal through the data converting module.
6. The system of claim 1, wherein the SFP interface is communicatively coupled to the SerDes.
7. The system as claimed in claim 1, wherein the LED screen display screen is adapted to the DCI standard by the receiving card.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010800735.8A CN111918046A (en) | 2020-08-11 | 2020-08-11 | Novel movie server control display system |
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| CN202010800735.8A CN111918046A (en) | 2020-08-11 | 2020-08-11 | Novel movie server control display system |
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| CN111918046A true CN111918046A (en) | 2020-11-10 |
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Citations (6)
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| KR101357182B1 (en) * | 2013-12-27 | 2014-02-11 | 엘림광통신 주식회사 | High definition serial digital interface video transmission system |
| CN104113740A (en) * | 2014-07-28 | 2014-10-22 | 中国科学院光电技术研究所 | Mixed format signal optical fiber transmission device |
| CN105025277A (en) * | 2015-07-24 | 2015-11-04 | 大连集思特科技有限公司 | Optical fiber transmission system for LED display screen |
| CN105960764A (en) * | 2015-07-09 | 2016-09-21 | 深圳市视捷光电科技有限公司 | High-definition video signal light transmission system, module pin definition method and transmission method |
| CN109947376A (en) * | 2019-04-04 | 2019-06-28 | 上海威固信息技术股份有限公司 | A kind of multi-protocol interface solid-state memory system realized based on FPGA |
| CN111026233A (en) * | 2019-11-18 | 2020-04-17 | 北京空间机电研究所 | High-speed parallel data receiving system based on clock driver and FPGA |
-
2020
- 2020-08-11 CN CN202010800735.8A patent/CN111918046A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101357182B1 (en) * | 2013-12-27 | 2014-02-11 | 엘림광통신 주식회사 | High definition serial digital interface video transmission system |
| CN104113740A (en) * | 2014-07-28 | 2014-10-22 | 中国科学院光电技术研究所 | Mixed format signal optical fiber transmission device |
| CN105960764A (en) * | 2015-07-09 | 2016-09-21 | 深圳市视捷光电科技有限公司 | High-definition video signal light transmission system, module pin definition method and transmission method |
| WO2017004822A1 (en) * | 2015-07-09 | 2017-01-12 | 深圳市视捷光电科技有限公司 | Optical transmission system capable of transmitting high definition video signal, method of defining module pin, and transmission method |
| CN105025277A (en) * | 2015-07-24 | 2015-11-04 | 大连集思特科技有限公司 | Optical fiber transmission system for LED display screen |
| CN109947376A (en) * | 2019-04-04 | 2019-06-28 | 上海威固信息技术股份有限公司 | A kind of multi-protocol interface solid-state memory system realized based on FPGA |
| CN111026233A (en) * | 2019-11-18 | 2020-04-17 | 北京空间机电研究所 | High-speed parallel data receiving system based on clock driver and FPGA |
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Application publication date: 20201110 |
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