CN111916505A - Crystalline silicon solar cell, preparation method and cell module - Google Patents
Crystalline silicon solar cell, preparation method and cell module Download PDFInfo
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- 229910021419 crystalline silicon Inorganic materials 0.000 title claims description 66
- 238000002360 preparation method Methods 0.000 title description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 123
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 122
- 239000010703 silicon Substances 0.000 claims abstract description 122
- 238000002161 passivation Methods 0.000 claims abstract description 100
- 239000000758 substrate Substances 0.000 claims abstract description 93
- 230000005684 electric field Effects 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims description 28
- 230000002093 peripheral effect Effects 0.000 claims description 13
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 11
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 8
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 230000003667 anti-reflective effect Effects 0.000 claims 1
- 238000006243 chemical reaction Methods 0.000 abstract description 21
- 230000005686 electrostatic field Effects 0.000 abstract description 11
- 230000002708 enhancing effect Effects 0.000 abstract description 5
- 210000004027 cell Anatomy 0.000 description 86
- 230000006798 recombination Effects 0.000 description 53
- 238000005215 recombination Methods 0.000 description 51
- 239000000969 carrier Substances 0.000 description 50
- 101001073212 Arabidopsis thaliana Peroxidase 33 Proteins 0.000 description 11
- 101001123325 Homo sapiens Peroxisome proliferator-activated receptor gamma coactivator 1-beta Proteins 0.000 description 11
- 102100028961 Peroxisome proliferator-activated receptor gamma coactivator 1-beta Human genes 0.000 description 11
- 230000004888 barrier function Effects 0.000 description 11
- 230000008569 process Effects 0.000 description 9
- 230000000903 blocking effect Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 210000005056 cell body Anatomy 0.000 description 6
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 238000007650 screen-printing Methods 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 238000003723 Smelting Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000013329 compounding Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 125000004437 phosphorous atom Chemical group 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 239000000370 acceptor Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000006388 chemical passivation reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005421 electrostatic potential Methods 0.000 description 1
- 238000001727 in vivo Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000001846 repelling effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
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- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
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- Y02E10/547—Monocrystalline silicon PV cells
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Abstract
According to the invention, the dielectric layer and the conducting layer are arranged on one side of the traditional battery body, so that after the conducting layer has a preset potential, a potential difference exists between the conducting layer and the first electrode, and the conducting layer is led to the vicinity of the silicon wafer substrate through the dielectric layer, thereby forming electric field passivation on the surface of the silicon wafer substrate, enhancing an electrostatic field formed on the surface of the silicon wafer, and improving the conversion efficiency of the battery without great changes such as arrangement of a through hole on the structure of the battery body.
Description
Technical Field
The invention relates to the field of solar cells, in particular to a crystalline silicon solar cell, a preparation method and a cell module.
Background
With the continuous consumption of traditional energy and the negative impact on the environment, the development and utilization of solar energy as a pollution-free and renewable energy are rapidly developed, and especially the solar cell with higher conversion efficiency is the focus of current research.
At present, a passivation layer such as aluminum oxide is prepared on the back of a battery, so that an electrostatic field is formed on the surface of a silicon wafer to repel non-equilibrium carriers inside the silicon wafer to be close to the surface of the silicon wafer, the concentration of the non-equilibrium carriers on the surface of the silicon wafer is reduced, the recombination rate of the non-equilibrium carriers on the surface of the silicon wafer is further reduced, carriers generated after a semiconductor body of the solar battery absorbs sunlight through a photovoltaic effect are prevented from being recombined at the recombination center of the surface of the silicon wafer to cause electrical loss, the carrier moves directionally under the action of an internal electric field, so that a photovoltaic field is formed, effective current is generated, and the conversion efficiency of the crystalline silicon solar battery is improved. In addition, the passivation layer on the back of the battery is electrically connected with the front electrode on the front of the battery in a mode of arranging the through hole in the PERC battery main body, so that the passivation layer has an electrostatic potential equal to that of the front electrode, an external electric field can be formed, the electrostatic field on the surface of the silicon wafer is enhanced, the recombination rate of non-equilibrium carriers on the surface of the silicon wafer is further reduced, and the conversion efficiency of the solar battery is improved.
However, in the current scheme, in the process of enhancing the electrostatic field formed on the surface of the silicon wafer and improving the conversion efficiency of the PERC cell by applying an electric field to the PERC cell, the major structure of the PERC cell needs to be largely modified by providing through holes, so that the efficiency of the PERC cell body for absorbing sunlight through the photovoltaic effect to generate carriers is affected, and the conversion efficiency of the crystalline silicon solar cell is reduced.
Disclosure of Invention
The invention provides a crystalline silicon solar cell, a preparation method and a cell module, aiming at improving the conversion efficiency of the crystalline silicon solar cell.
In a first aspect, an embodiment of the present invention provides a crystalline silicon solar cell, including:
the battery comprises a battery main body, a dielectric layer and a conductive layer, wherein the dielectric layer and the conductive layer are arranged on one surface of the battery main body;
the battery main body comprises a silicon wafer substrate and a passivation layer arranged on one surface of the silicon wafer substrate;
the dielectric layer is arranged on one surface of the passivation layer, which is far away from the silicon wafer substrate, and the conducting layer is arranged on one surface of the dielectric layer, which is far away from the passivation layer;
the battery main body further comprises a first electrode on one side of the dielectric layer and the conducting layer;
and through the electrical connection, the conducting layer is enabled to have a preset potential, and a potential difference exists between the conducting layer and the first electrode, so that electric field passivation is formed on the surface of the silicon wafer substrate.
Optionally, the relative dielectric constant of the dielectric layer is greater than 3.8.
Optionally, the material of the dielectric layer includes any one or more of alumina, titania and zirconia, and the thickness of the dielectric layer is greater than 50 nm.
Optionally, the first electrode includes a first main gate and a first fine gate, and the first fine gate intersects with the first main gate;
the dielectric layer is provided with a hollow structure, the first main gate is located at the position of the hollow structure, and the width of the hollow structure is larger than that of the first main gate.
Optionally, the area of the conductive layer is smaller than the area of the dielectric layer.
Optionally, the thickness of the conductive layer is greater than 200 nm.
Optionally, a first antireflection layer or a reflective layer is disposed between the passivation layer and the dielectric layer.
Optionally, the battery main body further includes: the PN junction structure layer, the second antireflection layer and the second electrode are arranged on the other surface of the silicon wafer substrate;
the PN junction structure layer is arranged on the other surface of the silicon wafer substrate, and the second antireflection layer is arranged on one surface, deviating from the silicon wafer substrate, of the PN junction structure layer.
Optionally, the electrically connecting to make the conductive layer have a preset potential specifically includes:
the conductive layer is electrically connected with any one of the second electrode, the second electrode of the adjacent cell of the crystalline silicon solar cell and a peripheral circuit independent of the crystalline silicon solar cell;
wherein the second electrode, the second electrode of an adjacent cell of the crystalline silicon solar cell, and the peripheral circuit have the preset potential.
Optionally, the crystalline silicon solar cell further includes a local doping layer;
the local doping layer is arranged at the position where the silicon wafer substrate is contacted with the first electrode.
In a second aspect, an embodiment of the present invention provides a method for preparing a crystalline silicon solar cell, for preparing the crystalline silicon solar cell, where the method includes:
arranging a passivation layer on one surface of a silicon wafer substrate;
preparing a first electrode on one surface of the silicon wafer substrate;
preparing a dielectric layer on the passivation layer, and arranging a conductive layer on one surface of the dielectric layer, which is far away from the passivation layer;
and through electric connection, the conducting layer is enabled to have a preset potential, and a potential difference exists between the conducting layer and the first electrode, so that electric field passivation is formed on the surface of the silicon wafer substrate.
The invention provides a crystalline silicon solar cell module, which comprises the crystalline silicon solar cell.
Based on the crystalline silicon solar cell, the preparation method and the cell module, the application has the following beneficial effects:
the battery body comprises a silicon wafer substrate and a passivation layer which are sequentially arranged, and a first electrode which is arranged at one side close to the conductive layer and the conductive layer, the dielectric layer is arranged on the surface of the passivation layer in the battery body, wherein the passivation layer can form a barrier layer on the surface of the silicon wafer substrate so as to repel non-equilibrium carriers in the silicon wafer from being close to the surface of the silicon wafer substrate, and further reduce the surface recombination rate of the non-equilibrium carriers, the conductive layer is arranged on the surface of the dielectric layer, after the conductive layer has a preset potential through electric connection, a potential difference is generated between the conductive layer and the first electrode, so that an external electric field can be formed in the battery body and is led into the vicinity of the silicon wafer substrate through the dielectric layer, so that electric field passivation is formed on the surface of the silicon wafer substrate, and the electrostatic field passivation can further enhance the electrostatic field of the barrier layer formed on the surface, therefore, the surface recombination rate of non-equilibrium carriers is further reduced, and the conversion efficiency of the battery is improved without great changes such as arrangement of through holes on the main structure of the battery.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
Fig. 1 shows a schematic structural diagram of a crystalline silicon solar cell in an embodiment of the invention;
fig. 2 shows a top view of a battery body in an embodiment of the invention;
fig. 3 shows a top view of a crystalline silicon solar cell in an embodiment of the invention;
fig. 4 shows a top view of another crystalline silicon solar cell in an embodiment of the invention;
fig. 5 shows a flow chart of steps of a method for manufacturing a crystalline silicon solar cell in an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the working process of the crystalline silicon solar cell, the electrical loss caused by the non-equilibrium carrier recombination in the crystalline silicon solar cell is one of the main factors causing the low efficiency of the crystalline silicon solar cell, so that the reduction of the electrical loss caused by the non-equilibrium carrier recombination is an important link needing to be considered for optimizing the cell structure and improving the conversion efficiency.
Specifically, the nonequilibrium carrier recombination in the crystalline silicon solar cell mainly includes various modes such as radiative recombination, auger recombination and indirect recombination. The forbidden band width, the energy band structure and the doping concentration of the silicon are inevitably related to the radiative recombination and the Auger recombination, and the optimal design needs to be carried out by combining the overall photoelectric performance of the battery. Indirect recombination refers to recombination of nonequilibrium carriers through recombination centers, wherein the recombination centers are lattice defect structures in semiconductors, such as impurities, dislocations and the like, the recombination centers can form certain energy levels in forbidden bands of the semiconductors, the nonequilibrium carriers can be recombined by means of the intermediate energy levels, the more lattice defects, the greater the recombination rate and the shorter the life of the nonequilibrium carriers.
Therefore, with the progress of the monocrystalline silicon smelting technology and the battery preparation technology, the electrical property loss of the solar battery caused by indirect recombination can be greatly reduced, which is also an important direction for the development of different types of solar battery technologies.
Further, the indirect recombination of non-equilibrium carriers is divided into in vivo recombination and surface recombination according to the position where the indirect recombination process occurs. The internal compounding of the crystalline silicon solar cell is related to a monocrystalline silicon smelting technology, and impurities in the monocrystalline silicon are removed to the greatest extent by the existing smelting technology on the premise of meeting the requirement of mass production cost, so that the surface compounding is the main reason for reducing the conversion efficiency of the solar cell. The surface recombination is related to a large number of dangling bonds on the surface of a silicon wafer, so that the silicon atoms which are originally periodically arranged lose part of coordination atoms, the dangling bonds are formed after the surface of the silicon-silicon chemical bonds is broken, the dangling bonds are used as one of lattice defects, are between donors and acceptors, can form a certain intermediate energy level in a forbidden band, and become a recombination center of an unbalanced carrier. Therefore, it is necessary to passivate dangling bonds on the surface of the silicon wafer, so as to reduce the surface recombination rate (Us) of the surface recombination of the unbalanced carriers, improve the life of the unbalanced carriers, and thus improve the conversion efficiency of the battery.
Different passivation treatment modes form different technical routes of crystalline silicon solar cells, for example, a Silicon Heterojunction (SHJ) solar cell is passivated by hydrogenated amorphous silicon, and a PERC cell is passivated by preparing aluminum oxide by a high-temperature process to passivate the surface of a silicon wafer. These passivation processes can greatly reduce the surface recombination rate, and are one of the key technologies for high-efficiency solar cells.
Specifically, the calculation process of the surface recombination rate is shown in formula (1):
Us＝s×(Δp)s (1)
wherein Us is the surface recombination rate of surface recombination of non-equilibrium carriers;
s is the surface recombination rate of the surface recombination of the non-equilibrium carriers;
(Δp)sis the concentration of non-equilibrium carriers at the surface.
As can be seen from the formula (1), the recombination velocity s at the surface can be reduced or the concentration of non-equilibrium carriers (Δ p) at the surface can be reducedsThe surface recombination rate of the non-equilibrium carriers is reduced.
Specific examples of the method for reducing the surface recombination rate Us of the nonequilibrium carriers by reducing the surface recombination rate s include: specifically, the number of dangling bonds is reduced by using a silicon-hydrogen bond formed by hydrogen and silicon, and the surface recombination rate s is reduced, so that the surface recombination rate Us of non-equilibrium carriers is reduced, and the passivation mode is called chemical passivation.
For the reduction of the non-equilibrium carrier concentration (Δ p) at the surfacesTo reduce the surface recombination rate Us of the non-equilibrium carriers, specific examples include: for a PERC battery, an alumina passivation layer prepared at high temperature has a large amount of space charges with negative electricity, can attract majority carrier holes in a p-type silicon substrate to gather at the interface of the alumina passivation layer to form a positive barrier layer, and the barrier layer can repel non-equilibrium carriers to be close to the surface of a silicon wafer, so that the concentration (delta p) of the non-equilibrium carriers at the surface is reducedsAnd further reduce the surface recombination rate Us of the non-equilibrium carriers, in a manner known as field passivation.
The present invention provides a crystalline silicon solar cell and a cell module thereof, which are described in detail below by referring to several specific embodiments.
Referring to fig. 1, a schematic structural diagram of a crystalline silicon solar cell provided by an embodiment of the present invention is shown, and as shown in fig. 1, the crystalline silicon solar cell is improved on the basis of a conventional cell, that is, a dielectric layer 20 and a conductive layer 30 are disposed on one side of a cell main body 10.
The cell body 10 may be a PERC cell with high conversion efficiency, the PERC cell includes an alumina passivation layer 60 prepared at a high temperature, the alumina passivation layer 60 has a large amount of negatively charged space charges, and the alumina passivation layer 60 can attract majority carriers in the silicon wafer substrate 40 to gather at an interface of the alumina passivation layer to form a blocking layer, and the blocking layer can repel non-equilibrium carriers to be close to the surface of the silicon wafer, so as to reduce the occurrence of surface recombination, and this passivation mode is called field passivation.
In the embodiment of the present invention, the conductive layer 30 may be a film structure made of a metal material having a high conductive performance, and the conductive layer 30 may have a predetermined potential by being electrically connected to other electrodes; the dielectric layer 20 may be a film structure made of a material with a high relative dielectric constant, and because the dielectric layer 20 has a high relative dielectric constant, the dielectric layer 20 may isolate the conductive layer 30 from the battery main body 10, so as to avoid short circuit with other parts of the battery main body 10, and at the same time, may introduce the preset potential of the conductive layer 30 into the battery main body 10, and enhance the electrostatic field of the blocking layer formed on the surface of the silicon wafer in the battery main body 10, so as to strengthen the blocking layer in the battery main body 10 by forming an external electric field, and further repel the unbalanced carriers from approaching the surface of the silicon wafer, thereby reducing the concentration of the unbalanced carriers on the surface of the silicon wafer, further reducing the surface recombination rate of the unbalanced carriers, enhancing the field passivation strength, and improving the conversion efficiency of the battery.
Specifically, referring to fig. 1, the cell body 10 includes a silicon wafer substrate 40 and a passivation layer 60, the passivation layer 60 being disposed on one side of the silicon wafer substrate 40.
The passivation layer 60 may be an aluminum oxide layer, a large amount of space charges with negative charges contained in the aluminum oxide layer and a majority of carriers contained in the silicon wafer substrate 40 may be gathered at an interface between the passivation layer 60 and the silicon wafer substrate 40 to form a blocking layer, and the blocking layer can repel the non-equilibrium carriers in the silicon wafer substrate 40 to be close to the surface of the silicon wafer substrate 40, so as to reduce the concentration of the non-equilibrium carriers at the surface of the silicon wafer, further reduce the surface recombination rate of the non-equilibrium carriers, and implement field passivation.
In addition, on the side of the cell main body 10 close to the dielectric layer 20 and the conductive layer 30, the cell main body 10 further includes a first electrode 90, the preset potential of the conductive layer 30 is not equal to the potential of the first electrode 90, so that a potential difference exists between the conductive layer 30 and the first electrode 90, and thus an electric field passivation can be formed on the surface of the silicon wafer substrate 40, and the electric field passivation can further enhance the electrostatic field of a barrier layer formed by the passivation layer on the surface of the silicon wafer substrate, thereby further reducing the surface recombination rate of non-equilibrium carriers, and improving the conversion efficiency of the cell without largely changing the structure of the cell main body such as the arrangement of through holes.
It should be noted that, for a p-type silicon wafer substrate, the majority carriers in the silicon wafer substrate are holes, and the majority carrier holes are gathered at the interface of the aluminum oxide passivation layer to form a positive blocking layer, and through electrical connection, the conductive layer can have a higher preset potential, that is, the preset potential is greater than the potential of the first electrode, so that a positive potential difference is generated between the conductive layer and the first electrode, and further an electric field passivation is formed on the surface of the silicon wafer substrate, and the electric field passivation can further enhance the electrostatic field of the positive blocking layer formed on the surface of the silicon wafer substrate, so as to further reduce the surface recombination rate of the unbalanced carrier holes, and improve the conversion efficiency of the battery without largely changing the main structure of the battery such as providing through holes.
For an n-type silicon wafer substrate, majority carriers in the silicon wafer substrate are electrons, the majority carrier electrons are gathered at the interface of an alumina passivation layer to form a negative barrier layer, the conductive layer can have a lower preset potential through electric connection, namely the preset potential is smaller than the potential of the first electrode, so that a negative potential difference is generated between the conductive layer and the first electrode, and further an electric field passivation is formed on the surface of the silicon wafer substrate, the electrostatic field of the negative barrier layer formed on the surface of the silicon wafer substrate can be further enhanced through the electric field passivation, the surface recombination rate of non-equilibrium carrier electrons is further reduced, and the conversion efficiency of the battery is improved without great changes such as arrangement of through holes on the main body structure of the battery.
In the embodiment of the present invention, in order to enhance the field passivation in the battery body 10, the structure of the battery body 10 may not be greatly modified by only providing the dielectric layer 20 and the conductive layer 30 on one side of the battery body 10 based on the original structure of the battery body 10.
Specifically, the dielectric layer 20 is disposed on a side of the passivation layer 60 facing away from the silicon wafer substrate 40, and the conductive layer 30 is disposed on a side of the dielectric layer 20 facing away from the passivation layer 60.
In an embodiment of the present invention, a crystalline silicon solar cell includes: the battery comprises a battery main body, a dielectric layer and a conductive layer, wherein the dielectric layer and the conductive layer are arranged on one surface of the battery main body; the battery main body comprises a silicon wafer substrate and a passivation layer arranged on one surface of the silicon wafer substrate; the dielectric layer is arranged on one surface of the passivation layer, which is far away from the silicon wafer substrate, and the conducting layer is arranged on one surface of the dielectric layer, which is far away from the passivation layer; the battery main body also comprises a first electrode on one side of the dielectric layer and the conducting layer; and through the electric connection, the conducting layer has a preset potential, and a potential difference exists between the conducting layer and the first electrode, so that electric field passivation is formed on the surface of the silicon wafer substrate. In the application, a dielectric layer and a conductive layer are arranged on one side of a traditional battery body, wherein the battery body comprises a silicon wafer substrate and a passivation layer which are sequentially arranged, and a first electrode which is arranged on one side close to the conductive layer and the conductive layer, the dielectric layer is arranged on the surface of the passivation layer in the battery body, the passivation layer can form a barrier layer on the surface of the silicon wafer substrate, so that non-equilibrium carriers in the silicon wafer are repelled to be close to the surface of the silicon wafer substrate, and further the surface recombination rate of the non-equilibrium carriers is reduced, the conductive layer is arranged on the surface of the dielectric layer, after the conductive layer has a preset potential through electric connection, a potential difference is generated between the conductive layer and the first electrode, so that an external electric field can be formed in the battery body and is led into the vicinity of the silicon wafer substrate through the dielectric layer, and further an electric field passivation can be formed on the surface of the, therefore, the surface recombination rate of non-equilibrium carriers is further reduced, and the conversion efficiency of the battery is improved without great changes such as arrangement of through holes on the main structure of the battery.
Optionally, the relative dielectric constant of the dielectric layer may be greater than 3.8, so that the dielectric layer with a higher relative dielectric constant may be disposed between the conductive layer and the battery main body due to better insulating property, so as to isolate the conductive layer from the battery main body, thereby preventing the conductive layer from forming a short circuit with other parts of the battery main body, and on the other hand, the preset potential of the conductive layer may be introduced into the battery main body, thereby enhancing the electrostatic field of the barrier layer formed on the surface of the silicon wafer in the battery main body, and forming an external electric field.
Optionally, the dielectric layer may be made of any one or more of alumina, titania and zirconia, and the thickness of the dielectric layer may be greater than 50 nm, so that the dielectric layer has a higher relative dielectric constant.
Alternatively, referring to fig. 1, the first electrode 90 may include a first main grid 91 and a first fine grid 92, and the first fine grid 92 intersects the first main grid 91, so that the first fine grid 92 may collect the collected effective current to the first main grid 91, and further, when a plurality of cells are assembled into a cell module, the first main grid of a cell may be electrically connected to the second main grid of an adjacent cell, and the second main grid of a cell may be electrically connected to the first main grid of another adjacent cell, so that the plurality of cells are connected in series.
Further, the dielectric layer 20 has a hollow structure, the first main gate 91 is located at the position of the hollow structure in the dielectric layer 20, and the width B of the hollow structure of the dielectric layer 20 is greater than the width a of the first main gate, so that when the dielectric layer 20 is prepared, the dielectric layer 20 is prevented from contacting the first main gate 91 due to the winding degree generated by the dielectric layer 20.
In an embodiment of the present invention, one side of the first fine gate 92 may be interconnected with the silicon substrate 40, and the other side of the first fine gate 92 may be interconnected with the dielectric layer 20.
Optionally, the area of the conductive layer 30 is smaller than the area of the dielectric layer 20, that is, the first main gate 91 and the conductive layer 30 are not in contact with each other, and in order to prevent the conductive layer 30 from contacting with other parts in the battery body 10 due to the winding degree generated by the conductive layer 30 and causing short circuit when the conductive layer 30 is prepared, the dielectric layer 20 also has a hollow structure, and the width C of the hollow structure of the conductive layer 30 is greater than the width B of the hollow structure of the dielectric layer 20.
Optionally, the thickness of the conductive layer may be greater than 200 nm, the conductive layer may be made of any one or more of aluminum, silver and copper, so that the conductive layer has a high conductive performance, and thus, the conductive layer may have a preset potential in an electrical connection manner, so that a potential difference exists between the conductive layer and the first electrode, thereby forming electric field passivation on the surface of the silicon wafer substrate, and strengthening a barrier layer formed in the battery body at an interface between the passivation layer and the silicon wafer substrate due to the passivation layer, thereby further repelling unbalanced carriers from approaching the surface of the silicon wafer, reducing the concentration of the unbalanced carriers on the surface of the silicon wafer, further reducing the surface recombination rate of the unbalanced carriers, enhancing the field passivation strength, and improving the conversion efficiency of the battery.
Optionally, referring to fig. 1, a first antireflection layer or reflection layer 71 is disposed between the passivation layer 60 and the dielectric layer 30, so as to reduce reflection of sunlight on the surface of the crystalline silicon solar cell, reduce or eliminate stray light of the system, increase the light transmittance of the crystalline silicon solar cell element, and improve the photoelectric conversion efficiency of the crystalline silicon solar cell.
Optionally, referring to fig. 1, the cell body 10 further includes a PN junction structure layer 50, a second antireflection layer 70, and a second electrode 80 disposed on the other side of the silicon wafer substrate 40.
The PN junction structure layer 50 is arranged on the other surface of the silicon wafer substrate 40, and the second antireflection layer 70 is arranged on one surface of the PN junction structure layer 50, which is far away from the silicon wafer substrate 40.
In an embodiment of the present invention, the first electrode 90 may pass through the passivation layer 60 and the first anti-reflection layer 71 and protrude out of a surface of the first anti-reflection layer or the reflection layer 71 facing away from the passivation layer 60, one side of the second electrode 80 may be connected with the PN junction structure layer 50, and the second electrode 80 passes through the second anti-reflection layer 70 and protrudes out of a surface of the second anti-reflection layer 70 facing away from the PN junction structure layer 50.
Alternatively, the conductive layer may be electrically connected to any one of the second electrode, the second electrode of the adjacent cell of the crystalline silicon solar cell, and a peripheral circuit independent from the crystalline silicon solar cell, and since the second electrode, the second electrode of the adjacent cell of the crystalline silicon solar cell, and the peripheral circuit have the preset potential, the conductive layer electrically connected to the second electrode and the peripheral circuit also has the preset potential, so that a potential difference is generated between the conductive layer and the first electrode, thereby forming electric field passivation on the surface of the silicon wafer substrate.
Referring to fig. 1, the conductive layer 30 may be electrically connected to the second electrode 80 in the battery body 10 such that the conductive layer 30 forms an equipotential body with the second electrode 80 and a capacitor is formed with the first electrode 90 such that a potential difference is generated between the conductive layer 30 and the first electrode 90.
In the embodiment of the present invention, after the plurality of batteries are assembled into the battery module, the conductive layer may be electrically connected to the second electrode of the adjacent battery, so that the conductive layer and the second electrode of the adjacent battery form an equipotential body, and a capacitor may be formed between the conductive layer and the first electrode, so that a potential difference is generated between the conductive layer and the first electrode.
Furthermore, it is also possible to electrically connect the conductive layer to a peripheral circuit independent of the battery, the peripheral circuit having a predetermined potential such that the conductive layer forms an equipotential with the peripheral circuit and forms a capacitor with the first electrode such that a potential difference is generated between the conductive layer and the first electrode.
In an embodiment of the present invention, the second electrode 80 may include a second main gate 81 and a second fine gate 82, and the second fine gate 82 intersects the second main gate 81.
Referring to fig. 2, which shows a plan view of a battery body according to an embodiment of the present invention, as shown in fig. 2, a second electrode including second main grids and second fine grids may be formed on one side of the battery body 10 by screen printing, so as to collect and conduct an effective current in one side of the battery body, and first main grids 91 and first fine grids 92 may be formed on the other side of the battery body 10, so as to collect and conduct an effective current in the other side of the battery body 10.
Specifically, the second electrode comprises a second main grid and a second fine grid, and the second fine grid intersects with the second main grid, so that the second fine grid can collect the collected effective current to the second main grid.
Referring to fig. 3, which shows a top view of a crystalline silicon solar cell provided in an embodiment of the present invention, as shown in fig. 3, after a first main grid 91 and a first fine grid 92 intersecting with each other are prepared on a first antireflection layer or a reflection layer 71 of a cell main body 10 by a screen printing method, a dielectric layer 20 may be continuously prepared on the first antireflection layer or the reflection layer 71, where the dielectric layer 20 has a hollow structure, and a width of the hollow structure of the dielectric layer 20 is greater than a width of the first main grid 91.
Referring to fig. 4, which shows a top view of another crystalline silicon solar cell provided in the embodiment of the present invention, as shown in fig. 4, after a dielectric layer 20 is prepared on a first antireflection layer or a reflection layer 71, a conductive layer 30 may be continuously prepared on the dielectric layer 20, where the conductive layer 30 also has a hollow structure, and a width of the hollow structure of the conductive layer 30 is greater than a width of the hollow structure of the dielectric layer 20.
Optionally, the cell further includes a local doping layer, and the local doping layer is disposed at a position where the silicon wafer substrate contacts the first electrode.
Referring to fig. 1, a local doping layer 100 is further disposed between a silicon wafer substrate 40 and a first electrode 90 of a cell body 10, if the silicon wafer substrate 40 is a p-type silicon wafer, phosphorus atoms as impurities can be doped into one surface of the silicon wafer substrate 40 by diffusion to form a PN junction structure layer 50, so as to prepare a PN junction, so that the cell body 10 can absorb sunlight by a photovoltaic effect to generate carriers and generate an effective current, and in order to further improve the conversion efficiency of a crystalline silicon solar cell and improve the effective collection of the photogenerated carriers, boron atoms as impurities can be doped into the other surface of the silicon wafer substrate 40, and the local doping layer 100 is formed at a position where the silicon wafer substrate 40 and the first electrode 90 are in contact.
The invention also provides a method for preparing the crystalline silicon solar cell, and referring to fig. 5, a flow chart of steps of a method for preparing a crystalline silicon solar cell provided by the embodiment of the invention is shown, and the method can comprise the following steps:
In this step, a P-type silicon substrate may be selected as a silicon wafer substrate of the crystalline silicon solar cell, and an aluminum oxide film Layer may be prepared on one side of the silicon wafer substrate by Atomic Layer Deposition (ALD), so as to form a passivation Layer on one side of the silicon wafer substrate.
In the embodiment of the present invention, after forming the passivation layer on one side of the silicon wafer substrate, a silicon nitride film layer may be further prepared on the passivation layer by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, so as to form a first anti-reflection layer or a reflective layer on a surface of the passivation layer away from the silicon wafer substrate.
In this step, the first electrode having a pattern structure may be printed on the surface of the passivation layer using a screen printing technique.
In the embodiment of the present invention, if a first antireflection layer or a reflective layer is further disposed on the passivation layer, a first electrode having a pattern structure may be printed on a surface of the first antireflection layer or the reflective layer.
Furthermore, the passivation layer and the first antireflection layer or the reflection layer can be removed by using corrosive silver paste, so that the first electrode is in contact with the silicon wafer substrate, and the first electrode penetrates through the passivation layer and the first antireflection layer or the reflection layer and extends out of the surface of the first antireflection layer or the reflection layer, which is away from the passivation layer.
Optionally, the first electrode includes a first main gate and a first fine gate, and in order to achieve effective collection of photo-generated carriers, a local doping layer may be prepared by heavy doping at a position where the first main gate and the first fine gate are in contact with a silicon wafer substrate.
Before the step, impurity phosphorus atoms can be doped on the other surface of the silicon wafer substrate through diffusion to form a PN junction structure layer, and a silicon nitride film layer is prepared on the PN junction structure layer through PECVD, so that a second anti-reflection layer is formed on the surface of the PN junction structure layer, which is far away from the silicon wafer substrate.
Furthermore, a second electrode with a graphic structure can be printed on the surface of the second antireflection layer by utilizing a screen printing technology, the second antireflection layer is removed by utilizing corrosive silver paste, and the second electrode is in contact with the silicon wafer substrate, so that the second electrode is in contact with the PN junction structure layer and penetrates through the second antireflection layer to extend out of the surface of the second antireflection layer deviating from the PN junction structure layer, and the PERC battery is finally obtained.
In this step, on the basis of the PERC cell prepared in the above step, a dielectric layer may be prepared on the passivation layer through a mask, the dielectric layer may be made of any one or more of alumina, titania, and zirconia, and the thickness of the dielectric layer may be greater than 50 nm, so that the dielectric layer has a higher relative dielectric constant, specifically, the relative dielectric constant of the dielectric layer may be greater than 3.8.
In the embodiment of the present invention, if a first antireflection layer or a reflective layer is further disposed on the passivation layer, a dielectric layer may be prepared on the first antireflection layer or the reflective layer through a mask.
It should be noted that, when the battery is assembled into a module, the first main grid needs to form a good electrical contact with the solder strip, so that when the dielectric layer is deposited, the mask needs to shield the first main grid to prevent the dielectric layer from being deposited on the first main grid, so that the dielectric layer has a hollow structure, the first main grid is located at the position of the hollow structure, and the width of the hollow structure of the dielectric layer is ensured to be greater than the width of the first main grid.
Furthermore, a conducting layer can be prepared on the surface of the dielectric layer, which is away from the passivation layer, through a mask, the conducting layer can be made of any one or more of aluminum, silver and copper, the thickness of the conducting layer can be larger than 200 nanometers, so that the conducting layer has high conducting performance, a preset potential can be provided through electric connection, a potential difference can be generated between the conducting layer and the first electrode, and electric field passivation can be formed on the surface of the silicon chip substrate.
It should be noted that, when the battery is assembled into a module, the first main grid needs to form a good electrical contact with the solder strip, and meanwhile, in order to avoid short circuit with the battery due to the fact that the film layer is wound and plated, when the conductive layer is deposited, the hollowed-out part of the mask needs to be smaller than the pattern of the hollowed-out part of the mask used in the preparation of the dielectric layer, so that the prepared conductive layer also has a hollowed-out structure, the first main grid is located at the hollowed-out structure, and the width of the hollowed-out structure of the conductive layer is ensured to be larger than the width of the hollowed-out structure of the dielectric layer.
And 104, enabling the conducting layer to have a preset potential through electric connection, and enabling the conducting layer and the first electrode to have a potential difference, so that electric field passivation is formed on the surface of the silicon wafer substrate.
In this step, the conductive layer may be brought to a predetermined potential by electrical connection so that a potential difference exists between the conductive layer and the first electrode, whereby electric field passivation may be formed on the surface of the silicon wafer substrate.
Specifically, by electrically connecting a conductive layer with any one of a second electrode, a second electrode of an adjacent cell of the crystalline silicon solar cell, and a peripheral circuit independent from the crystalline silicon solar cell, since the second electrode, the second electrode of the adjacent cell of the crystalline silicon solar cell, and the peripheral circuit have the preset potential, the conductive layer electrically connected with the second electrode and the peripheral circuit also has the preset potential, so that a potential difference is generated between the conductive layer and the first electrode, thereby forming electric field passivation on the surface of the silicon wafer substrate.
In an embodiment of the present invention, a method for manufacturing a crystalline silicon solar cell includes: arranging a passivation layer on one surface of a silicon wafer substrate; preparing a first electrode on one surface of a silicon wafer substrate; preparing a dielectric layer on the passivation layer, and arranging a conductive layer on the surface of the dielectric layer, which is far away from the passivation layer; and through the electric connection, the conducting layer has a preset potential, and a potential difference exists between the conducting layer and the first electrode, so that electric field passivation is formed on the surface of the silicon wafer substrate. In the application, a dielectric layer and a conductive layer are arranged on one side of a traditional battery body, wherein the battery body comprises a silicon wafer substrate and a passivation layer which are sequentially arranged, and a first electrode which is arranged on one side close to the conductive layer and the conductive layer, the dielectric layer is arranged on the surface of the passivation layer in the battery body, the passivation layer can form a barrier layer on the surface of the silicon wafer substrate, so that non-equilibrium carriers in the silicon wafer are repelled to be close to the surface of the silicon wafer substrate, and further the surface recombination rate of the non-equilibrium carriers is reduced, the conductive layer is arranged on the surface of the dielectric layer, after the conductive layer has a preset potential through electric connection, a potential difference is generated between the conductive layer and the first electrode, so that an external electric field can be formed in the battery body and is guided into the vicinity of the silicon wafer substrate through the dielectric layer, so that electric field passivation is formed on the surface of the, therefore, the surface recombination rate of non-equilibrium carriers is further reduced, and the conversion efficiency of the battery is improved without great changes such as arrangement of through holes on the main structure of the battery.
It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the embodiments are not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the embodiments of the application.
In addition, the invention also provides a crystalline silicon solar cell module which is composed of the crystalline silicon solar cell.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (12)
1. A crystalline silicon solar cell, characterized in that the crystalline silicon solar cell comprises:
the battery comprises a battery main body, a dielectric layer and a conductive layer, wherein the dielectric layer and the conductive layer are arranged on one surface of the battery main body;
the battery main body comprises a silicon wafer substrate and a passivation layer arranged on one surface of the silicon wafer substrate;
the dielectric layer is arranged on one surface of the passivation layer, which is far away from the silicon wafer substrate, and the conducting layer is arranged on one surface of the dielectric layer, which is far away from the passivation layer;
the battery main body further comprises a first electrode on one side of the dielectric layer and the conducting layer;
and through the electrical connection, the conducting layer is enabled to have a preset potential, and a potential difference exists between the conducting layer and the first electrode, so that electric field passivation is formed on the surface of the silicon wafer substrate.
2. The crystalline silicon solar cell of claim 1, wherein the dielectric layer has a relative dielectric constant greater than 3.8.
3. The crystalline silicon solar cell of claim 2, wherein the dielectric layer comprises a material comprising any one or more of alumina, titania and zirconia, and has a thickness greater than 50 nm.
4. The crystalline silicon solar cell of claim 1,
the first electrode comprises a first main grid and a first fine grid, and the first fine grid is intersected with the first main grid;
the dielectric layer is provided with a hollow structure, the first main gate is located at the position of the hollow structure, and the width of the hollow structure is larger than that of the first main gate.
5. The crystalline silicon solar cell of claim 4,
the area of the conducting layer is smaller than that of the dielectric layer.
6. Crystalline silicon solar cell according to any one of claims 1 to 5,
the thickness of the conductive layer is greater than 200 nanometers.
7. Crystalline silicon solar cell according to any of claims 1 to 5, a first antireflective or reflective layer being provided between the passivation layer and the dielectric layer.
8. Crystalline silicon solar cell according to any one of claims 1 to 5,
the battery main body further includes: the PN junction structure layer, the second antireflection layer and the second electrode are arranged on the other surface of the silicon wafer substrate;
the PN junction structure layer is arranged on the other surface of the silicon wafer substrate, and the second antireflection layer is arranged on one surface, deviating from the silicon wafer substrate, of the PN junction structure layer.
9. The crystalline silicon solar cell according to any of claims 1 to 5, characterized in that said bringing the conductive layer to a preset potential by means of an electrical connection, in particular comprises:
the conductive layer is electrically connected with any one of the second electrode, the second electrode of the adjacent cell of the crystalline silicon solar cell and a peripheral circuit independent of the crystalline silicon solar cell;
wherein the second electrode, the second electrode of an adjacent cell of the crystalline silicon solar cell, and the peripheral circuit have the preset potential.
10. The crystalline silicon solar cell according to any one of claims 1 to 5, characterized in that it further comprises a local doping layer;
the local doping layer is arranged at the position where the silicon wafer substrate is contacted with the first electrode.
11. A method for manufacturing a crystalline silicon solar cell according to any one of claims 1 to 10, the method comprising:
arranging a passivation layer on one surface of a silicon wafer substrate;
preparing a first electrode on one surface of the silicon wafer substrate;
preparing a dielectric layer on the passivation layer, and arranging a conductive layer on one surface of the dielectric layer, which is far away from the passivation layer;
and through electric connection, the conducting layer is enabled to have a preset potential, and a potential difference exists between the conducting layer and the first electrode, so that electric field passivation is formed on the surface of the silicon wafer substrate.
12. A crystalline silicon solar cell module, characterized in that it comprises a crystalline silicon solar cell according to any one of claims 1 to 10.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09199742A (en) * | 1996-01-19 | 1997-07-31 | Hitachi Ltd | Field effect solar cell |
| JPH11266029A (en) * | 1998-03-18 | 1999-09-28 | Sharp Corp | Solar cell, manufacture and connection thereof |
| JP2011035092A (en) * | 2009-07-31 | 2011-02-17 | Sanyo Electric Co Ltd | Back-junction type solar cell and solar cell module using the same |
| US20120285517A1 (en) * | 2011-05-09 | 2012-11-15 | International Business Machines Corporation | Schottky barrier solar cells with high and low work function metal contacts |
| JP2013229359A (en) * | 2012-04-24 | 2013-11-07 | Sharp Corp | Solar battery panel, solar battery module and photovoltaic power generation system |
| CN105470342A (en) * | 2014-09-10 | 2016-04-06 | 黄清 | Method for enhancing solar cell efficiency |
| US20170092791A1 (en) * | 2014-05-26 | 2017-03-30 | Kyocera Corporation | Solar cell element |
| CN208127216U (en) * | 2018-03-28 | 2018-11-20 | 通威太阳能（成都）有限公司 | A kind of PERC back of solar cell laser slotting structure |
| CN110546768A (en) * | 2017-04-27 | 2019-12-06 | 京瓷株式会社 | Solar cell element and method for manufacturing solar cell element |
| CN111180551A (en) * | 2020-01-02 | 2020-05-19 | 浙江晶科能源有限公司 | Selective emitter solar cell and preparation method thereof |
-
2020
- 2020-07-17 CN CN202010699989.5A patent/CN111916505A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09199742A (en) * | 1996-01-19 | 1997-07-31 | Hitachi Ltd | Field effect solar cell |
| JPH11266029A (en) * | 1998-03-18 | 1999-09-28 | Sharp Corp | Solar cell, manufacture and connection thereof |
| JP2011035092A (en) * | 2009-07-31 | 2011-02-17 | Sanyo Electric Co Ltd | Back-junction type solar cell and solar cell module using the same |
| US20120285517A1 (en) * | 2011-05-09 | 2012-11-15 | International Business Machines Corporation | Schottky barrier solar cells with high and low work function metal contacts |
| JP2013229359A (en) * | 2012-04-24 | 2013-11-07 | Sharp Corp | Solar battery panel, solar battery module and photovoltaic power generation system |
| US20170092791A1 (en) * | 2014-05-26 | 2017-03-30 | Kyocera Corporation | Solar cell element |
| CN105470342A (en) * | 2014-09-10 | 2016-04-06 | 黄清 | Method for enhancing solar cell efficiency |
| CN110546768A (en) * | 2017-04-27 | 2019-12-06 | 京瓷株式会社 | Solar cell element and method for manufacturing solar cell element |
| CN208127216U (en) * | 2018-03-28 | 2018-11-20 | 通威太阳能（成都）有限公司 | A kind of PERC back of solar cell laser slotting structure |
| CN111180551A (en) * | 2020-01-02 | 2020-05-19 | 浙江晶科能源有限公司 | Selective emitter solar cell and preparation method thereof |
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