CN111916426A - Semiconductor device with a plurality of semiconductor chips - Google Patents

Semiconductor device with a plurality of semiconductor chips Download PDF

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Publication number
CN111916426A
CN111916426A CN202010363022.XA CN202010363022A CN111916426A CN 111916426 A CN111916426 A CN 111916426A CN 202010363022 A CN202010363022 A CN 202010363022A CN 111916426 A CN111916426 A CN 111916426A
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China
Prior art keywords
structural
component
semiconductor device
structural member
identification mark
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CN202010363022.XA
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Chinese (zh)
Inventor
岩永広志
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/04—Mounting of components, e.g. of leadless components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54413—Marks applied to semiconductor devices or parts comprising digital information, e.g. bar codes, data matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Supply And Installment Of Electrical Components (AREA)

Abstract

Provided is a semiconductor device which can mount a plurality of laminated structural members on a structural member without creating a process recipe. The semiconductor device includes a structural member and a plurality of stacked structural members mounted on the structural member. The structural member and the plurality of structural members include a1 st structural member and a2 nd structural member mounted on the 1 st structural member. The 1 st structural component has an identification mark showing information related to the 2 nd structural component.

Description

Semiconductor device with a plurality of semiconductor chips
Technical Field
The present invention relates to a semiconductor device.
Background
Semiconductor devices such as power modules often have a structure in which other components such as mounting components are mounted on components such as a base substrate. In the case where other components are mounted on the components by a mounting apparatus in order to manufacture a specific variety of semiconductor devices, a process recipe (recipe) in which the variety, mounting position, mounting angle, mounting conditions, mounting order, and the like of each component are set for each mounting point on which each component is mounted is created for the specific variety of semiconductor devices before the other components are mounted on the components. The mounting conditions include a moving speed, a mounting speed, and the like. The process recipe is also referred to as a procedure. The mounting machine calls a process recipe created for a specific type of semiconductor device in setup for a specific type of semiconductor device, and mounts another component on the component according to the called process recipe.
In the technique described in patent document 1, a conductor of a predetermined circuit pattern is printed on the back surface of a printed wiring board (paragraph 0012). On the surface side of the printed wiring board, the positions of elements such as an IC, a capacitor, and a buzzer are shown as a pattern drawn by lines (paragraph 0012).
In the technique described in patent document 2, the back surface of the semiconductor chip is marked with information unique to mounting conditions required for mounting, information related to manufacturing of the semiconductor chip, an alignment mark as information for alignment required at the time of mounting, and the like (paragraph 0017-. Further, the mother chip is disposed so that the surface of the mother chip faces upward (paragraph 0024). In addition, the sub chip is aligned with respect to the mother chip in a face-down state in which the surface of the sub chip faces down (paragraph 0024). At this time, information unique to the sub-chip is marked on the back surface of the sub-chip (paragraph 0024). Therefore, alignment of the daughter chip with respect to the mother chip is easily performed based on, for example, an alignment mark in the information (paragraph 0024).
Patent document 1: japanese laid-open patent publication No. 7-245455
Patent document 2: japanese patent laid-open No. 2000-228489
When a mounting machine assembles a plurality of varieties of semiconductor devices, a process recipe must be created for each variety of semiconductor device. Therefore, each time a new semiconductor device is manufactured, a process recipe must be created for the new semiconductor device. Therefore, a lot of work and time are required to prepare a new semiconductor device. This problem is remarkable in the case of small-scale production of various species.
Further, in the case where other structural components to be mounted on the structural component are stacked, the above-described process recipes must be created for the plurality of layers, respectively. Therefore, the above problem becomes more serious.
Disclosure of Invention
The present invention has been made in view of the above problems. The present invention addresses the problem of providing a semiconductor device in which a plurality of laminated structural members can be mounted on the structural members without creating a process recipe.
The semiconductor device includes a structural member and a plurality of stacked structural members mounted on the structural member. The structural member and the plurality of structural members include a1 st structural member and a2 nd structural member mounted on the 1 st structural member. The 1 st structural component has an identification mark showing information related to the 2 nd structural component.
ADVANTAGEOUS EFFECTS OF INVENTION
According to the present invention, information relating to the 2 nd structural component can be obtained from the identification mark of the 1 st structural component. Thus, multiple structural components can be automatically mounted on the structural component without creating a process recipe.
The objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.
Drawings
Fig. 1 is an exploded perspective view schematically illustrating a semiconductor device according to embodiment 1.
Fig. 2 is a cross-sectional view schematically illustrating a semiconductor device according to embodiment 1.
Fig. 3 is a flowchart showing an assembly flow of the semiconductor device according to embodiment 1.
Fig. 4 is an exploded perspective view schematically illustrating a semiconductor device according to embodiment 2.
Fig. 5 is a cross-sectional view schematically illustrating a semiconductor device according to embodiment 2.
Fig. 6 is an exploded perspective view schematically illustrating a semiconductor device according to embodiment 3.
Fig. 7 is a sectional view schematically illustrating a semiconductor device according to embodiment 3.
Fig. 8 is an exploded perspective view schematically illustrating a semiconductor device according to embodiment 4 and a jig used in a manufacturing process thereof.
Fig. 9 is a sectional view schematically illustrating a semiconductor device of embodiment 4 and a jig used in a manufacturing process thereof.
Description of the reference numerals
1.2, 3, 4 semiconductor device, 101, 102, 103, 104P, 104Q, 105P, 105Q structural parts, a plurality of structural parts 110, 110P, 110Q, a1, B1 1 st structural part, A2, A2P, A2Q, B2, B2P, B2Q 2 nd structural part, AM, BM, AMP, AMQ, BMP, BMQ identification marks, AJ, BJ clamps, AR, BR openings.
Detailed Description
1 embodiment mode 1
1.1 semiconductor device
Fig. 1 is an exploded perspective view schematically illustrating a semiconductor device according to embodiment 1. Fig. 2 is a cross-sectional view schematically illustrating a semiconductor device according to embodiment 1.
The semiconductor device 1 of embodiment 1 illustrated in fig. 1 and 2 is a power module.
The semiconductor device 1 may be a semiconductor device other than a power module.
The semiconductor device 1 has a structural member 101 and a plurality of structural members 110. The plurality of structural members 110 are mounted on and stacked on the structural member 101.
The structural member 101 is a base substrate serving as a reference. The structural member 101 may be a structural member other than the base substrate.
The plurality of structural members 110 include structural members 103 and structural members 105. The structural member 103 is an insulating substrate. The structural member 103 may be a structural member other than the insulating substrate. The structural member 105 is a power semiconductor element. The structural member 105 may be a structural member other than the power semiconductor element.
The plurality of structural components 101 and 110 include a1 st structural component a1 and a2 nd structural component a2 mounted on the 1 st structural component a1, and include a1 st structural component B1 and a2 nd structural component B2 mounted on the 1 st structural component B1.
The 1 st structural component a1 has structural component 101. The 2 nd structural component a2 has a structural component 103. The 1 st structural component B1 has the structural component 103. The 2 nd structural component B2 has the structural component 105. Component 103 is referred to as component 2 a2 in relation to component 101 and component 1B 1 in relation to component 105.
The 1 st structural component a1 has an identification mark AM representing information relating to the 2 nd structural component a 2. The 1 st structural member B1 has an identification mark BM indicating information relating to the 2 nd structural member B2.
The identification marks AM and BM are respectively a barcode, a two-dimensional code, characters, figures, symbols, and the like, and are preferably a barcode or a two-dimensional code. In the case where the identification mark AM and the identification mark BM are respectively a barcode or a two-dimensional code, the sizes of the identification mark AM and the identification mark BM can be reduced, and the identification mark AM and the identification mark BM can show all necessary information.
The information indicated by the identification marks AM and BM includes at least one selected from the group consisting of the type, mounting position, mounting angle, and mounting condition of the 2 nd structural component a2 and the 2 nd structural component B2, respectively. The mounting conditions include a mounting speed, a mounting order, and the like.
The 2 nd structural member a2 and the 2 nd structural member B2 are mounted on the identification mark AM and the identification mark BM, respectively.
1.2 processing device
The semiconductor device 1 is assembled by a processing apparatus. The processing device is a mounting machine or the like. The processing apparatus can assemble a plurality of types of semiconductor devices including the semiconductor device 1.
The processing apparatus has a holder capable of mounting a structural member constituting a plurality of kinds of semiconductor devices that can be assembled.
The processing apparatus includes a device capable of recognizing the identification mark of the component constituting the plurality of types of semiconductor devices that can be assembled. When the identification mark is a barcode, the device is a barcode reader that reads the barcode and acquires information indicated by the read barcode. In the case where the identification mark is a two-dimensional code, the device is a two-dimensional code reader that reads the two-dimensional code and acquires information represented by the read two-dimensional code. The device may be a combination of a camera that reads the identification mark and an image processing apparatus that acquires information indicated by the read identification mark. A combination of a camera and an image processing device can be employed both in the case where the identification mark is a barcode or a two-dimensional code and in the case where the identification mark is not a barcode or a two-dimensional code.
The processing apparatus includes a conveyor for conveying workpieces constituting a plurality of types of semiconductor devices that can be assembled.
The processing apparatus further includes an adsorption mounting machine that adsorbs a mounting component constituting a plurality of types of semiconductor devices that can be assembled and mounts the adsorbed mounting component on a workpiece.
1.3 Assembly of semiconductor devices
Fig. 3 is a flowchart showing an assembly flow of the semiconductor device according to embodiment 1.
When the semiconductor device 1 is assembled, steps S101 to S108 shown in fig. 3 are performed.
In step S101, the component 103, and the component 105 constituting the semiconductor device 1 are loaded into the processing apparatus. The component 101, the component 103, and the component 105 to be put in are provided in the holder. In addition to the components 101, 103, and 105, components constituting a different type of semiconductor device from the semiconductor device 1 may be provided on the holder. For example, all kinds of components constituting a semiconductor device to be mounted in a day may be provided in the holder.
Next, the machining apparatus starts the automatic operation. Thereby, steps S102 to S108 shown in fig. 3 are performed.
In step S102, the conveyor conveys the component 101 from the rack to a predetermined position inside the processing apparatus, and positions and fixes the component 101 at the predetermined position.
In the next step S103, the device reads the identification mark.
In the next step S104, the device acquires information indicated by the read identification mark.
In the next step S105, the suction mounting machine sucks the mounted component mounted on the rack in accordance with the acquired information. The suction mounting machine sucks the mounted components under suction conditions set for each mounted component in the processing device in advance.
In the next step S106, the suction mounting machine moves the suctioned mounted component shaft to the mounting position in accordance with the acquired information.
In the next step S107, the suction mounting machine mounts the mounting component, the shaft of which has been moved to the mounting position, on the mounting position.
In steps S106 and S107, the suction mounting machine performs the axial movement and mounting of the mounted components in accordance with the mounting conditions set for each mounted component in the machining device in advance.
In the next step S108, it is determined whether or not the mounting of all the mounted components is completed. When all the mounting components have been mounted, the assembly of 1 semiconductor device 1 is completed. In a case where the mounting of all the mounted components has not been completed, steps S103 to S108 are executed again.
In embodiment 1, when steps S103 to S107 are executed the 1 st time, the device reads the identification mark AM and acquires information indicated by the read identification mark AM. Further, the suction-mounting machine sucks the component 103 in accordance with the acquired information, moves the sucked component 103 to a mounting position, and mounts the component 103 at the mounting position after the axial movement. In embodiment 1, when steps S103 to S107 are executed the 2 nd time, the apparatus reads the identification mark BM and acquires information indicated by the read identification mark BM. Further, the suction mounting machine sucks the component 105 in accordance with the acquired information, moves the sucked component 105 to a mounting position, and mounts the component 105 having the moved axis at the mounting position.
2 effects of embodiment 1
According to the invention of embodiment 1, information on the 2 nd structural component a2 and the 2 nd structural component B2 can be acquired from the identification mark AM of the 1 st structural component a1 and the identification mark BM of the 1 st structural component B1, respectively. Therefore, the plurality of structural components 110 can be automatically mounted on the structural component 101 without creating a process recipe.
Therefore, according to the invention of embodiment 1, it is not necessary to create a process recipe relating to each of the plurality of layers for each new type of semiconductor device every time a setup for manufacturing the new type of semiconductor device is performed. This reduces the amount of work and time required for the preparation of a new semiconductor device. The effect is remarkable in the case of carrying out production of various varieties in a small amount.
Further, according to the invention of embodiment 1, it is possible to provide a component constituting a plurality of kinds of semiconductor devices on the holder. Therefore, after the 1 st type of semiconductor device included in the plurality of types of semiconductor devices is assembled, the 2 nd type of semiconductor device included in the plurality of types of semiconductor devices can be assembled without replacing the provided component with another component. Therefore, it is possible to reduce replacement of the component parts when the type of the assembled semiconductor device is changed. Therefore, the operation rate of the processing apparatus is improved, and the productivity of the semiconductor device is improved.
3 embodiment 2
Fig. 4 is an exploded perspective view schematically illustrating a semiconductor device according to embodiment 2. Fig. 5 is a cross-sectional view schematically illustrating a semiconductor device according to embodiment 2.
The semiconductor device 2 of embodiment 2 shown in fig. 4 and 5 is different from the semiconductor device 1 of embodiment 1 shown in fig. 1 and 2 mainly in the following points. The semiconductor device 2 of embodiment 2 also has the same structure as that of the semiconductor device 1 of embodiment 1, except for those not described below.
The plurality of structural members 110 include a structural member 102, a structural member 103, a structural member 104, and a structural member 105.
The 1 st structural component a1 has structural component 101. The 2 nd structural member a2 has 2 or more structural members 102 and 103 stacked. The 1 st structural component B1 has the structural component 103. The 2 nd structural member B2 has 2 or more structural members 104 and 105 stacked.
The structural member 102 is a bonding material. The structural member 103 is an engaged member engaged with the 1 st structural member a1 through the structural member 102. The structural member 104 is a bonding material. The structural member 105 is an engaged member engaged with the 1 st structural member B1 through the structural member 104.
The identification mark AM shows information relating to the structural component 102 and the structural component 103. The information indicated by the identification mark AM includes the mounting order of the structural component 102 and the structural component 103. The identification mark BM shows information relating to the structural component 104 and the structural component 105. The information indicated by the identification mark BM includes the mounting order of the structural component 104 and the structural component 105.
When the semiconductor device 2 is assembled, the device reads the identification mark AM and acquires information indicated by the read identification mark AM. The suction-mounting machine sucks the structural component 102 and the structural component 103 in accordance with the acquired information, moves the sucked structural component 102 and the sucked structural component 103 to a mounting position, and mounts the moved structural component 102 and the moved structural component 103 at the mounting position. The device reads the identification mark BM and acquires information indicated by the read identification mark BM. Further, the suction mounting machine sucks the structural component 104 and the structural component 105 in accordance with the acquired information, moves the sucked structural component 104 and the sucked structural component 105 to a mounting position, and mounts the moved structural component 104 and the moved structural component 105 at the mounting position.
According to the invention of embodiment 2, as in the invention of embodiment 1, the plurality of structural members 110 can be automatically mounted on the structural member 101 without creating a process recipe.
Further, according to the invention of embodiment 2, the stacked 2 or more components 102 and 103 can be automatically mounted at the same mounting position. Further, the stacked 2 or more components 104 and 105 can be automatically mounted at the same mounting position.
Embodiment 3
Fig. 6 is an exploded perspective view schematically illustrating a semiconductor device according to embodiment 3. Fig. 7 is a sectional view schematically illustrating a semiconductor device according to embodiment 3.
The semiconductor device 3 of embodiment 3 shown in fig. 6 and 7 is different from the semiconductor device 1 of embodiment 1 shown in fig. 1 and 2 mainly in the following points. The semiconductor device 3 of embodiment 3 also has the same structure as that of the semiconductor device 1 of embodiment 1, except for those not described below. The semiconductor device 3 according to embodiment 3 may have the same configuration as that of the semiconductor device 2 according to embodiment 2 shown in fig. 4 and 5.
The semiconductor device 3 has a structural component 101, a plurality of structural components 110P, and a plurality of structural components 110Q.
The plurality of structural members 110P and the plurality of structural members 110Q respectively have a structural member 102, a structural member 103, a structural member 104P, a structural member 104Q, a structural member 105P, and a structural member 105Q.
Structural component 101, plurality of structural components 110P, and plurality of structural components 110Q comprise a1 st structural component a1 and a plurality of 2 nd structural components A2P and A2Q mounted over a1 st structural component a1, each of the plurality of structural components 110P and plurality of structural components 110Q comprising a1 st structural component B1 and a plurality of 2 nd structural components B2P and B2Q mounted over a1 st structural component B1.
The 1 st structural component a1 has structural component 101. The plurality of 2 nd structural members A2P and A2Q have 2 or more structural members 102 and 103, respectively, stacked. The 1 st structural component B1 has the structural component 103. The 2 nd structural member B2P has 2 or more structural members 104P and 105P stacked. The 2 nd structural component B2Q has 2 or more structural components 104Q and 105Q stacked.
The structural member 102 is a bonding material. The structural member 103 is an engaged member engaged with the 1 st structural member a1 through the structural member 102. The structural members 104P and 104Q are bonding materials. The structural component 105P and the structural component 105Q are engaged components engaged with the 1 st structural component B1 through the structural component 104P and the structural component 104Q, respectively.
The 1 st structural component a1 has a plurality of identification marks AMP and AMQ showing information relating to a plurality of 2 nd structural components A2P and A2Q, respectively. The 1 st structural component B1 has a plurality of identification marks BMP and BMQ showing information relating to a plurality of 2 nd structural components B2P and B2Q, respectively.
The identification mark AMP shows information on the structural components 102 and the structural components 103 constituting the plurality of structural components 110P. The identification mark AMQ shows information related to the structural component 102 and the structural component 103 constituting the plurality of structural components 110Q. The identification mark BMP shows information relating to the structural part 104P and the structural part 105P. The identification mark BMQ shows information related to the structural component 104Q and the structural component 105Q.
When the semiconductor device 3 is assembled, the device reads the identification mark AMP and acquires information indicated by the read identification mark AMP. Further, the suction mounting machine sucks the components 102 and 103 constituting the plurality of components 110P in accordance with the acquired information, moves the sucked components 102 and 103 to the mounting position, and mounts the components 102 and 103 at the mounting position after the axial movement. The device reads the identification mark AMQ and acquires information indicated by the read identification mark AMQ. Further, the suction mounting machine sucks the components 102 and 103 constituting the plurality of components 110Q in accordance with the acquired information, moves the sucked components 102 and 103 to the mounting position, and mounts the components 102 and 103 at the mounting position after the axial movement. The device reads the identification marker BMP and acquires information indicated by the read identification marker BMP. Further, the suction mounting machine sucks the component 104P and the component 105P in accordance with the acquired information, moves the sucked components 104P and 105P to the mounting position in an axial direction, and mounts the axial-moved components 104P and 105P at the mounting position. The device reads the identification mark BMQ and acquires information indicated by the read identification mark BMQ. Further, the suction mounting machine sucks the component 104Q and the component 105Q in accordance with the acquired information, moves the sucked components 104Q and 105Q to the mounting position, and mounts the moved components 104Q and 105Q at the mounting position.
According to the invention of embodiment 3, as in the invention of embodiment 1, the plurality of structural components 110P and the plurality of structural components 110Q can be automatically mounted on the structural component 101 without creating a process recipe.
Further, according to the invention of embodiment 3, as in the invention of embodiment 2, the stacked 2 or more components 102 and 103 can be automatically mounted at the same mounting position. Further, the stacked 2 or more components 104P and 105P can be automatically mounted at the same mounting position. Further, the stacked 2 or more components 104Q and 105Q can be automatically mounted at the same mounting position.
Further, according to the invention of embodiment 3, the structural members 102 and 103 constituting the plurality of structural members 110P and the structural members 102 and 103 constituting the plurality of structural members 110Q can be automatically mounted at different mounting positions. Further, the component 104P and the component 105P, and the component 104Q and the component 105Q can be automatically mounted at different mounting positions.
5 embodiment 4
Fig. 8 is an exploded perspective view schematically illustrating a semiconductor device according to embodiment 4 and a jig used in a manufacturing process thereof. Fig. 9 is a sectional view schematically illustrating a semiconductor device of embodiment 4 and a jig used in a manufacturing process thereof.
The semiconductor device 4 according to embodiment 4 illustrated in fig. 8 and 9 is different from the semiconductor device 3 according to embodiment 3 illustrated in fig. 6 and 7 mainly in the following points. The semiconductor device 4 of embodiment 4 also has the same structure as that of the semiconductor device 3 of embodiment 3, except for those not described below. The semiconductor device 4 according to embodiment 4 may have the same configuration as that of the semiconductor device 1 according to embodiment 1 illustrated in fig. 1 and 2 or the semiconductor device 2 according to embodiment 2 illustrated in fig. 4 and 5.
When the 2 nd component A2P and the 2 nd component A2Q are mounted on the 1 st component a1, the jig AJ shown in fig. 8 and 9 is mounted on the 1 st component a 1. The jig AJ has an opening ARP and an opening ARQ, which have planar shapes matching the planar shapes of the 2 nd structural component A2P and the 2 nd structural component A2Q, respectively. The opening ARP and the opening ARQ respectively accommodate the 2 nd component A2P and the 2 nd component A2Q. This enables the 2 nd component A2P and the 2 nd component A2Q to be positioned.
When the 2 nd structural component B2P and the 2 nd structural component B2Q are mounted on the 1 st structural component B1, the jig BJ shown in fig. 8 and 9 is mounted on the 1 st structural component B1. The jig BJ has an opening BRP and an opening BRQ having planar shapes matching those of the 2 nd structural component B2P and the 2 nd structural component B2Q, respectively. The 2 nd component B2P and the 2 nd component B2Q are accommodated in the opening BRP and the opening BRQ, respectively. This enables the 2 nd structural member B2P and the 2 nd structural member B2Q to be positioned.
The identification mark AMP and the identification mark AMQ of the 1 st structural component a1 also show information related to the jig AJ.
The identification marks BMP and BMQ of the 1 st structural part B1 also show information relating to the clamp BJ.
According to the invention of embodiment 4, as in the invention of embodiment 1, the plurality of structural components 110P and the plurality of structural components 110Q can be automatically mounted on the structural component 101 without creating a process recipe.
Further, according to the invention of embodiment 4, as in the invention of embodiment 2, the stacked 2 or more components 102 and 103 can be automatically mounted at the same mounting position. Further, the stacked 2 or more components 104P and 105P can be automatically mounted at the same mounting position. Further, the stacked 2 or more components 104Q and 105Q can be automatically mounted at the same mounting position.
Further, according to the invention of embodiment 4, the structural members 102 and 103 constituting the plurality of structural members 110P and the structural members 102 and 103 constituting the plurality of structural members 110Q can be automatically mounted at different mounting positions. Further, the component 104P and the component 105P, and the component 104Q and the component 105Q can be automatically mounted at different mounting positions.
Further, according to the invention of embodiment 4, the jig AJ can be mounted on the 1 st structural member a1 and the jig BJ can be mounted on the 1 st structural member B1 without creating a process recipe. Therefore, the 2 nd component A2P, the 2 nd component A2Q, the 2 nd component B2P, and the 2 nd component B2Q can be positioned, and the accuracy of the mounting positions of the 2 nd component A2P, the 2 nd component A2Q, the 2 nd component B2P, and the 2 nd component B2Q can be improved.
When the semiconductor device 1 according to embodiment 1 and the semiconductor device 2 according to embodiment 2 are assembled, the same jigs as the jigs AJ and BJ may be used.
6 embodiment 5
The semiconductor device according to embodiment 5 differs from the semiconductor device 1 according to embodiment 1 illustrated in fig. 1 and 2, the semiconductor device 2 according to embodiment 2 illustrated in fig. 4 and 5, the semiconductor device 3 according to embodiment 3 illustrated in fig. 6 and 7, or the semiconductor device 4 according to embodiment 4 illustrated in fig. 8 and 9 in the following points. The semiconductor device according to embodiment 5 also has the same configuration as that adopted for the semiconductor device 1 according to embodiment 1, the semiconductor device 2 according to embodiment 2, the semiconductor device 3 according to embodiment 3, or the semiconductor device 4 according to embodiment 4, which will not be described below.
In the semiconductor device according to embodiment 5, the identification mark is formed by laser printing. Thus, the identification mark is formed with the concave-convex portion, and when the structural member is mounted on the identification mark, the structural member is mounted on the concave-convex portion. This improves the bonding strength of the structural member mounted on the irregularities due to the anchor effect.
The identification mark may be formed by metal vapor deposition. This can suppress the influence of the identification mark on the bondability of the structural member mounted on the identification mark, and can obtain the same bonding strength of the structural member as that obtained when the identification mark is not formed.
In addition, the present invention can freely combine the respective embodiments within the scope of the invention, or appropriately modify or omit the respective embodiments.
Although the present invention has been described in detail, the above description is illustrative in all aspects, and the present invention is not limited thereto. It is understood that numerous modifications not illustrated can be devised without departing from the scope of the invention.

Claims (8)

1. A semiconductor device, comprising:
a structural component; and
a plurality of structural members stacked on top of each other,
the structural member and the plurality of structural members include:
1 st structural member; and
a2 nd structural member mounted on the 1 st structural member,
the 1 st structural component has an identification mark showing information related to the 2 nd structural component.
2. The semiconductor device according to claim 1,
the 2 nd structural member has 2 or more structural members stacked.
3. The semiconductor device according to claim 2,
the 2 or more structural members have a joining material and a joined member joined to the 1 st structural member by the joining material.
4. The semiconductor device according to any one of claims 1 to 3,
the structural member and the plurality of structural members include a plurality of 2 nd structural members mounted on the 1 st structural member,
the 1 st structural component has a plurality of identification marks respectively showing information related to the plurality of 2 nd structural components.
5. The semiconductor device according to any one of claims 1 to 4,
the identification mark further shows information on a jig disposed on the 1 st structural member when the 2 nd structural member is mounted on the 1 st structural member.
6. The semiconductor device according to any one of claims 1 to 5,
the identification mark is a bar code or a two-dimensional code.
7. The semiconductor device according to any one of claims 1 to 6,
the information includes at least one selected from the group consisting of a type, a mounting position, a mounting angle, and a mounting condition of the 2 nd component.
8. The semiconductor device according to any one of claims 1 to 7,
the 2 nd structural component is mounted on the identification mark.
CN202010363022.XA 2019-05-08 2020-04-30 Semiconductor device with a plurality of semiconductor chips Withdrawn CN111916426A (en)

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JP2006332507A (en) * 2005-05-30 2006-12-07 Kyocera Corp Package for housing electronic component, substrate for mounting electronic component and electronic device
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JPH02226786A (en) * 1989-02-28 1990-09-10 Nec Corp Printed wiring board
JP2000228489A (en) * 1999-02-08 2000-08-15 Rohm Co Ltd Chip-on-chip semiconductor chip and semiconductor device
JP2012119511A (en) * 2010-12-01 2012-06-21 Hitachi High-Tech Instruments Co Ltd Electronic component mounting device, electronic component mounting system, and electronic component mounting method
WO2016181434A1 (en) * 2015-05-08 2016-11-17 富士機械製造株式会社 Verification method

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Application publication date: 20201110