CN111916357A - 一种利用毛细效应填充tsv的工艺方法 - Google Patents

一种利用毛细效应填充tsv的工艺方法 Download PDF

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CN111916357A
CN111916357A CN202010590082.5A CN202010590082A CN111916357A CN 111916357 A CN111916357 A CN 111916357A CN 202010590082 A CN202010590082 A CN 202010590082A CN 111916357 A CN111916357 A CN 111916357A
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silicon carrier
capillary effect
carrier plate
wafer
filling
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李全兵
顾炯炯
赵励强
缪富军
杨志
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto

Abstract

本发明涉及一种利用毛细效应填充TSV的工艺方法，所述方法包括以下步骤：步骤一、在晶圆表面打孔形成TSV孔，并把打孔后的晶圆通过粘膜放在支撑板上；步骤二、制作硅载板；步骤三、使用硅载板利用毛细效应填充TSV孔；步骤四、在TSV孔中形成金属柱；步骤五、移除支撑板。本发明一种利用毛细效应填充TSV的工艺方法，它利用毛细效应填充TSV过孔可以缩短金属柱形成的时间，提高金属柱高度的一致性。

Description

一种利用毛细效应填充TSV的工艺方法
技术领域
本发明涉及一种利用毛细效应填充TSV的工艺方法，属于半导体封装技术领域。
背景技术
目前常见的制作TSV(Through Silicon Via)的工艺首先需要在晶圆上钻孔，然后利用电镀的方式填充过孔，形成铜柱，导通不同层线路。针对过孔密度高、深度深的情况,电镀工艺需要花费很长的时间，且电镀均匀性也需要特殊卡控。
发明内容
本发明所要解决的技术问题是针对上述现有技术提供一种利用毛细效应填充TSV的工艺方法，它利用毛细效应填充过孔可以缩短金属柱形成的时间，提高金属柱高度的一致性。
本发明解决上述问题所采用的技术方案为：一种利用毛细效应填充TSV的工艺方法，其特征在于所述方法包括以下步骤：
步骤一、在晶圆表面打孔形成TSV孔，并把打孔后的晶圆放在支撑板上；
步骤二、制作硅载板；
在硅载板的上表面依次通过压膜、照UV光、显影及蚀刻的方法形成凸起的图案，然后在硅载板的部分位置打孔，形成上下导通的通道；
步骤三、毛细效应填充TSV孔；
把晶圆倒置，将制作完成的硅载板置于晶圆和金属液体槽之间，硅载板的下表面浸入金属液体槽中，硅载板的上表面的凸起图案直接接触晶圆，硅载板的通道位置对应晶圆TSV孔的位置，金属液体槽中的液体会因为毛细效应经由通道填充进TSV孔中；
步骤四、形成金属柱；
移除硅载板和金属液体槽，将晶圆整体翻转朝上，步骤三中填充进TSV孔内的金属液体经烘烤固化形成金属柱；
步骤五、移除支撑板。
可选的，步骤一中支撑板的材质是玻璃。
可选的，步骤二中硅载板下表面同时通过压膜、照UV光、显影及蚀刻的方法形成凸起或凹陷的图案。
可选的，步骤二中硅载板表面形成的凸起图案是长城形、锯齿形或椭圆形。
可选的，步骤二中硅载板表面的图案是布满硅载板表面的或者是局部分布在硅载板表面的。
可选的，步骤二中通道的开口方式是硅载板下表面单边开口或是双边开口。
可选的，步骤二中通道下端开口的角度是小角度开口或是大角度开口。
可选的，金属液体对TSV孔和硅载板是不浸润的。
可选的，步骤五移除支撑板后对晶圆表面进行打磨和抛光处理。
与现有技术相比，本发明的优点在于：
1、本发明金属液体槽中的液体通过硅载板上的通道，利用毛细效应填充进TSV的过孔中，所有的过孔可以一次性填充，毛细效应的时间与电镀花费的时间相比较，大大缩短，同时提高了金属柱高度的一致性；
2、本发明针对不同直径和深度的TSV过孔，可以调整硅载板的设计，包括厚度、结构、表面的图案现状及分布(硅载板的表面可以制作各种图案，如长城行形、锯齿形、椭圆形；硅载板的结构可以有多种，如单边开口型、双边开口型等；开口的角度也可以根据实际情况调整)，增强毛细效应，改善填充的效果。
附图说明
图1～图5为本发明一种利用毛细效应填充TSV的工艺方法的各工序流程示意图。
图6～图8为硅载板表面图案的几种实施例示意图。
图9为较厚的硅载板采用双边开口的示意图。
图10为硅载板通道采用双边小角度开口的示意图。
图11为硅载板通道采用双边大角度开口的示意图。
图12为图案布满硅载板表面的示意图。
图13为图案局部分布在硅载板表面的示意图。
具体实施方式
以下结合附图实施例对本发明作进一步详细描述。
本发明涉及的一种利用毛细效应填充TSV的工艺方法，它包括以下步骤：
步骤一、如图1所示，在晶圆表面形成TSV孔，并把打孔后的晶圆通过粘膜放置在支撑板上；
孔的位置、直径和数量根据实际的产品需求进行设计；
支撑板的材质可以是玻璃，或者其他不易变形且不影响毛细效应的材质；
步骤二、制作硅载板
如图2所示，在硅载板的上表面依次通过压膜、照UV光、显影及蚀刻的方法形成凸起的图案，然后在硅载板的部分位置打孔，形成上下导通的通道；
硅载板的下表面可形成有凸起或凹陷的图案，可以增加硅载板下表面与金属液体的接触面积，增强毛细效应；
图案可以是长城形(如图6)、锯齿形(如图7)、椭圆形(如图8)等多种形状；
图案可以是布满硅载板表面的，也可以局部分布在硅载板表面(如图12和13)；硅载板表面的图案的目的是为了制造凸点，在晶圆和硅载板之间形成小的缝隙，利于空气的流通，使毛细效应起作用；
硅载板上打孔的方式可以是激光钻孔或者是机械穿孔；如果采用激光打孔，可以一次打孔完成，也可以多次打孔，以形成不同弧度组合的截面；
通道开口的方式可以是硅载板下表面单边开口，如图6～8所示，也可以是硅载板下表面双边开口，如图9～11所示；硅载板下表面开口的角度可以是小角度开口，也可以是大角度开口，硅载板的厚度可以根据实际产品的需求调整。
金属液体对TSV孔和硅载板是不浸润的。为了利用毛细效应把金属液体填充进TSV孔中，硅载板上通道的深度和孔的直径比例是有要求的，同时硅载板孔的直径与TSV孔的直径也有比例关系。假设TSV孔的直径为50um，TSV孔的高度为200um，则硅载板通道的直径为20um，高度为35um，硅载板表面的图案的宽度20um，间距20um，高度10um。
步骤三、毛细效应填充TSV孔
如图3所示，将制作完成的硅载板置于晶圆和金属液体槽之间，硅载板的下表面浸入金属液体槽中，硅载板的上表面的图案直接接触晶圆，硅载板的通道位置对应晶圆TSV孔的位置，金属液体槽中的液体会因为毛细效应经由通道填充进晶圆的TSV孔中；
步骤四、形成金属柱
如图4所示，移除硅载板和金属液体槽，将晶圆整体翻转，步骤三中填充进TSV孔内的金属液体经烘烤固化形成金属柱；
步骤五、移除支撑板
如图5所示，移除支撑板，有必要的话可以对晶圆表面进行一定的打磨和抛光处理。
上述实施例外，本发明还包括有其他实施方式，凡采用等同变换或者等效替换方式形成的技术方案，均应落入本发明权利要求的保护范围之内。

Claims (9)

1.一种利用毛细效应填充TSV的工艺方法，其特征在于所述方法包括以下步骤：
步骤一、在晶圆表面打孔形成TSV孔，并把打孔后的晶圆放在支撑板上；
步骤二、制作硅载板；
在硅载板的上表面依次通过压膜、照UV光、显影及蚀刻的方法形成凸起的图案，然后在硅载板的部分位置打孔，形成上下导通的通道；
步骤三、毛细效应填充TSV孔；
把晶圆倒置，将制作完成的硅载板置于晶圆和金属液体槽之间，硅载板的下表面浸入金属液体槽中，硅载板的上表面的凸起图案直接接触晶圆，硅载板的通道位置对应晶圆TSV孔的位置，金属液体槽中的液体会因为毛细效应经由通道填充进TSV孔中；
步骤四、形成金属柱；
移除硅载板和金属液体槽，将晶圆整体翻转朝上，步骤三中填充进TSV孔内的金属液体经烘烤固化形成金属柱；
步骤五、移除支撑板。
2.根据权利要求1所述的一种利用毛细效应填充TSV的工艺方法，其特征在于：步骤一中支撑板的材质是玻璃。
3.根据权利要求1所述的一种利用毛细效应填充TSV的工艺方法，其特征在于：步骤二中在硅载板下表面同时通过压膜、照UV光、显影及蚀刻的方法形成凸起或凹陷的图案。
4.根据权利要求1或3所述的一种利用毛细效应填充TSV的工艺方法，其特征在于：步骤二中硅载板表面形成的图案是长城形、锯齿形或椭圆形。
5.根据权利要求1或3所述的一种利用毛细效应填充TSV的工艺方法，其特征在于：步骤二中硅载板表面的图案是布满硅载板表面的或者是局部分布在硅载板表面的。
6.根据权利要求1所述的一种利用毛细效应填充TSV的工艺方法，其特征在于：步骤二中通道的开口方式是硅载板下表面单边开口或是双边开口。
7.根据权利要求1所述的一种利用毛细效应填充TSV的工艺方法，其特征在于：步骤二中通道下端开口的角度是小角度开口或是大角度开口。
8.根据权利要求1所述的一种利用毛细效应填充TSV的工艺方法，其特征在于：金属液体对TSV孔和硅载板是不浸润的。
9.根据权利要求1所述的一种利用毛细效应填充TSV的工艺方法，其特征在于：步骤五移除支撑板后对晶圆表面进行打磨和抛光处理。
CN202010590082.5A 2020-06-24 2020-06-24 一种利用毛细效应填充tsv的工艺方法 Pending CN111916357A (zh)

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