CN111916023B - LED display screen and display method thereof - Google Patents
LED display screen and display method thereof Download PDFInfo
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- CN111916023B CN111916023B CN202010760105.2A CN202010760105A CN111916023B CN 111916023 B CN111916023 B CN 111916023B CN 202010760105 A CN202010760105 A CN 202010760105A CN 111916023 B CN111916023 B CN 111916023B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
Abstract
The application provides an LED display screen and a display method thereof. The display method comprises the following steps: receiving 1-bit display data in a group of display data in a complete display period, latching the received 1-bit display data into a first buffer memory and a second buffer memory when a latch enabling signal is a first type valid signal, displaying the 1-bit display data in the first buffer memory in a next complete display period, latching the received 1-bit display data into the first buffer memory when the latch enabling signal is a second type valid signal, displaying the 1-bit display data in the first buffer memory in a next incomplete display period, and transferring the 1-bit display data in the second buffer memory into the first buffer memory when the latch enabling signal is a third type valid signal, and displaying the 1-bit display data in the first buffer memory in a next complete display period. In this way, the refresh efficiency of data is improved without changing the data refresh clock.
Description
Technical Field
The application relates to the field of display, in particular to a LED (Light Emitting Diode) display screen and a display method thereof.
Background
LED displays are now widely used. The LED display screen realizes dynamic display through a large amount of refreshing data. There are two ways in the prior art to achieve a 256-level brightness. One occupies 19 display periods, as shown in fig. 1 and 2, in which 8bits of display data are required in total, wherein the higher-order display data is 4 bits, wherein the first bit of display data occupies 8 display periods, the second bit of display data occupies 4 display periods, the third bit of display data occupies 2 display periods, the fourth bit of display data occupies 1 display period, and the 1 st to 4 th bits of display data are higher-order display data. The 5 th bit of display data occupies 1 display period, but only 1/2 is an effective display period, the rest is always in an invalid state, the 6 th bit of display data occupies 1 display period, but only 1/4 is an effective display period, the rest is always in an invalid state, the 7 th bit of display data occupies 1 display period, but only 1/8 is an effective display period, the rest is always in an invalid state, the 8 th bit of display data occupies 1 display period, but only 1/16 is an effective display period, and the rest is always in an invalid state. Bits 5-8 are low order display data. This 8-bit display data may be referred to as a set of display data. The efficiency (i.e., the ratio of the effective display duration to the overall display duration) in this manner was calculated to be 84%.
The current display mode is inefficient, and thus it is necessary to provide a new scheme to improve the problem.
Disclosure of Invention
The application aims to provide an LED display screen and a display method thereof, which can effectively improve the utilization rate and the refreshing efficiency of data without changing a data refreshing clock.
To achieve the object, according to one aspect of the present application, there is provided a display method of an LED display screen, including: and receiving 1-bit display data in a group of display data and 1-bit display data in a first buffer memory in a complete display period, wherein the group of display data comprises a plurality of high-bit display data and a plurality of low-bit display data, each high-bit display data corresponds to one or more complete display periods, each low-bit display data corresponds to one incomplete display period, when the latch enable signal is a first type valid signal, the received 1-bit display data is latched into the first buffer memory and the second buffer memory, and the 1-bit display data in the first buffer memory and the received lower 1-bit display data are displayed in the next complete display period, when the latch enable signal is a second type valid signal, the received 1-bit display data is latched into the first buffer memory, and the 1-bit display data in the second buffer memory is transferred into the first buffer memory in the next incomplete display period, when the latch enable signal is a third type valid signal, and the 1-bit display data in the next display period is received in the first buffer memory.
According to another aspect of the present application, there is provided an LED display screen comprising: a display module including a plurality of display units; and a display driving module including a plurality of display driving units, each driving one of the display units. Each display driving unit includes a first buffer and a second buffer, each display driving unit and each display unit being configured to: and receiving 1-bit display data in a group of display data and 1-bit display data in a first buffer memory in a complete display period, wherein the group of display data comprises a plurality of high-bit display data and a plurality of low-bit display data, each high-bit display data corresponds to one or more complete display periods, each low-bit display data corresponds to one incomplete display period, when the latch enable signal is a first type valid signal, the received 1-bit display data is latched into the first buffer memory and the second buffer memory, and the 1-bit display data in the first buffer memory and the received lower 1-bit display data are displayed in the next complete display period, when the latch enable signal is a second type valid signal, the received 1-bit display data is latched into the first buffer memory, and the 1-bit display data in the second buffer memory is transferred into the first buffer memory in the next incomplete display period, when the latch enable signal is a third type valid signal, and the 1-bit display data in the next display period is received in the first buffer memory.
To achieve the object, according to one aspect of the present application, there is provided a display method of an LED display screen, including: in a complete display period, 1-bit display data and 1-bit display data are received in a group of display data, in an incomplete display period, 1-bit display data are displayed, wherein the group of display data comprises a plurality of high-bit display data and a plurality of low-bit display data, each high-bit display data corresponds to one or more complete display periods, each low-bit display data corresponds to one incomplete display period, after the 1-bit high-bit display data is received, the 1-bit high-bit display data which is just received in the next complete display period is displayed, and the 1-bit high-bit display data or the 1-bit low-bit display data which is just received in the next incomplete display period is received, after the 1-bit low-bit display data is received, the 1-bit high-bit display data which is just received in the next complete display period is displayed in the next incomplete display period, and the same 1-bit high-bit display data as the previous complete display period is displayed in the next complete display period.
Compared with the prior art, the application adopts an interpolation algorithm, can effectively improve the utilization rate, and can improve the refreshing efficiency of data under the condition of not changing the data refreshing clock.
Drawings
FIG. 1 is a timing diagram of a display method in the prior art;
FIG. 2 is a schematic diagram of a display principle of a conventional display method with 19 display periods;
FIG. 3 is a partially detailed schematic illustration of a schematic illustration of the display principle in bitmap 2;
FIG. 4 is a schematic diagram of a display method according to an embodiment of the present application;
FIG. 5 is a schematic diagram of an LED display screen according to an embodiment of the present application;
fig. 6 is a schematic diagram of a specific display principle of the display method in fig. 4.
Detailed Description
In order to further describe the technical means and effects adopted for achieving the preset aim of the application, the following detailed description is given below of the specific implementation, structure, characteristics and effects according to the application with reference to the attached drawings and the preferred embodiments.
The application provides an LED display screen and a display method thereof, which can effectively improve the utilization rate by adopting an interpolation algorithm, improve the refreshing efficiency of data without changing a data refreshing clock, and further provide the refreshing frequency of the data.
FIG. 4 is a schematic diagram of a display method according to the present application in a first embodiment; fig. 5 is a schematic structural diagram of an LED display screen according to an embodiment of the present application. As shown in fig. 5, the LED display screen includes a display driving module 610 and a display module 620. The display module comprises a plurality of display units 620-1,620-2,620-m, namely m display units, wherein m is a positive integer greater than or equal to 2. The display driving module 610 includes a plurality of display driving units 610-1,610-2,610-m, i.e., m display driving units. Each display driving unit drives one display unit. In a specific embodiment, a communication mode of cascading 16 display driving chips is adopted, each display driving chip supports 16 display driving channels, and each display driving channel comprises a display driving unit. Each display driving unit includes a first buffer and a second buffer. As shown in fig. 5, each display driving unit may input a latch enable signal LE, an output enable signal OE, a clock signal, and a serial input signal SDI. The serial output terminal SDO of each display driving unit is connected to the serial input terminal SDI of the following display driving unit, and the serial input terminal receives the serial input signal SDI.
In connection with fig. 3-6, the display method of the present application includes the following operations.
The method includes receiving 1-bit display data in a set of display data and displaying the 1-bit display data in the first buffer or the second buffer in a complete display period.
For example, as shown in fig. 3, one complete display period is 256 clock periods, in which each display unit may display 1-bit display data, and the display driving units synchronized may receive 1-bit display data in a set of display data in one complete display period. The display driving module 610 may support 256 display channels, and then may need to serially receive 1-bit display data corresponding to each of the 256 display channels in a complete display period. Of course, in other embodiments, a complete display period may be 512 or other numbers of clock periods, and the display driving module 610 may support 512 or other numbers of display channels.
Typically, the display driver module 610 receives 1-bit display data during the same complete display period, and the display module 620 displays the 1-bit display data received during the previous complete display period.
As described above, the set of display data may be 8bits, but may also be other bits, where the set of display data includes a plurality of high-order display data and a plurality of low-order display data, each of the high-order display data corresponds to one or more complete display periods, and each of the low-order display data corresponds to one of the incomplete display periods. In particular, 8bits of data may beIncluding 4-bit high-order display data and 4-bit low-order display data, as in the embodiment shown in fig. 4. The 1 st low-order display data corresponds to 1/2 of a complete display period of the incomplete display period, and the n low-order display data corresponds to 1/2 of the complete display period of the incomplete display period n N is the ranking of the lower display data in the set of display data, n being equal to 4 in the example.
The two concepts of a complete display period and a non-complete display period are mentioned herein, in which 1-bit display data corresponding to all display channels can be received serially in one complete display period, and 1-bit display data corresponding to all display channels cannot be received serially in a non-complete display period. Therefore, in the incomplete display period, only the received 1-bit low-order display data is displayed, and the display data is not received.
For 1-bit high-order display data, such as the 1 st high-order display data in fig. 2 and 4, it corresponds to 8 complete display periods, i.e., the 1-bit high-order display data is displayed for all of the 8 complete display periods. However, in the prior art, the same 1-bit high-order data is still received after the first full display period for display in the next full display period. For the display mode shown in fig. 2, 19 bits of display data need to be received.
As shown in fig. 6, when the latch enable signal LE is the first type valid signal, for example, a CLK pulse is included as the first type valid signal, the received 1-bit display data is latched into the first buffer and the second buffer, and in the next complete display period (i.e., no output enable signalWhen the signal is active, the low level is active, and the enable signal is not output +.>Is an inverse of the output enable signal OE) displays 1-bit display data in the first buffer and receives the next 1-bit display data. In general, the connection is made in one complete display periodWhen 1-bit high-order display data is received, the latch enable signal LE that follows may be a first type of valid signal. The first display period, the third display period, and the fourth display period having 256 clocks shown in fig. 6 are complete display periods, the second display period and the fourth display period are incomplete display periods, the high-order data in fig. 6 may also be referred to as high-order display data, the low-order data may also be referred to as low-order display data, transmitting one set of display data may be referred to as one cycle, and the last display period of the last cycle refers to the last display period of the last set of display data.
As shown in fig. 6, when the latch enable signal is the second type valid signal, for example, two CLK pulses are included as the second type valid signal, the received 1-bit display data is latched into the first buffer, and the 1-bit display data in the first buffer is displayed in the next incomplete display period. In connection with fig. 6, in general, when 1-bit low-order display data is received in one complete display period, the next latch enable signal is a second type valid signal, for example, the latch enable signals next to the low-order data 1 and 2 received in fig. 6 are both a second type valid signal.
As shown in fig. 6, when the latch enable signal is a third type of valid signal, such as a narrow pulse, the data in the second buffer is transferred into the first switch, and the 1-bit display data in the first buffer is displayed and the next 1-bit display data is received in the next complete display period. As shown in fig. 6, in general, after one incomplete display period, new display data cannot be received at this time, so the latch enable signal is the third kind of valid signal. The third display period still displays the already cached high-order display data displayed in the first display period. That is, after one incomplete display period, 1-bit high-order display data identical to the previous complete display period is displayed in the next complete display period.
By the method, the incomplete display period can be inserted into the complete display period of the high-order display data, the utilization rate can be effectively improved, the data refreshing efficiency is improved under the condition that the data refreshing clock is not changed, and the data refreshing frequency is further provided.
As shown in fig. 4, upon receipt of the 1 st high-order display data, the high-order display data occupies 8 display periods, i.e., the 8 display periods all display the same high-order display data. Thus, a 1/2 non-complete display period may be inserted after the first complete display period, while the high-order display data displayed in the first complete display period is buffered, then the buffered high-order display data is again used to display the second complete display period, then a 1/4 non-complete display period may be inserted after the second complete display period, then the buffered high-order display data is again used to display the third complete display period, then a 1/8 non-complete display period may be inserted after the third complete display period, then the buffered high-order display data is again used to display the fourth complete display period, then a 1/16 non-complete display period may be inserted after the fourth complete display period, and finally the received high-order display data may be displayed in the fifth, sixth, seventh and eighth complete display periods. In the subsequent 4 full display periods (9 th to 12 th full display periods), 2 full display periods (13 th to 14 th full display periods), and 1 full display period ((15 th full display period), the received 1-bit high-order display data is displayed, respectively.
Of course, in other embodiments, after each incomplete display period is inserted into other complete display periods, for example, after 1/2 of the incomplete display period is inserted into the 6 th complete display period, 1/4 of the incomplete display period is inserted into the 7 th complete display period, 1/16 of the incomplete display period is inserted into the 19 th complete display period, and the insertion position can be adjusted as required. In the complete display period, 1-bit display data can be received, 1-bit display data can be displayed, and in the incomplete display period, 1-bit display data cannot be received, so that only the cached display content which is the same as the last complete display period can be displayed after the incomplete display period.
As shown in FIG. 4, the incomplete display period may be inserted into any one of the 2 nd-7 th complete display periods, the 9 th-11 th complete display periods, and the 13 th complete display period, at which time the high-order display data has been buffered, so that the same display content as the previous complete display period may be directly displayed after the incomplete display period.
In this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a list of elements is included, and may include other elements not expressly listed.
In this document, terms such as front, rear, upper, lower, etc. are defined with respect to the positions of the components in the drawings and with respect to each other, for clarity and convenience in expressing the technical solution. It should be understood that the use of such orientation terms should not limit the scope of the claimed application.
The embodiments described above and features of the embodiments herein may be combined with each other without conflict.
The foregoing description of the preferred embodiments of the application is not intended to limit the application to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the application are intended to be included within the scope of the application.
Claims (4)
1. A display method of an LED display screen, comprising:
receiving 1-bit display data in a set of display data and displaying the 1-bit display data in a first buffer in a complete display period, the set of display data including a plurality of high-bit display data and a plurality of low-bit display data, each high-bit display data corresponding to one or more complete display periods, each low-bit display data corresponding to one incomplete display period,
when the latch enable signal is a first kind of valid signal, the received 1-bit display data is latched into the first buffer and the second buffer, and the 1-bit display data in the first buffer is displayed and the next 1-bit display data is received in the next complete display period,
when the latch enable signal is the second kind valid signal, the received 1-bit display data is latched into the first buffer memory, and the 1-bit display data in the first buffer memory is displayed in the next incomplete display period,
when the latch enable signal is a third type valid signal, the 1-bit display data in the second buffer memory is transferred to the first buffer memory, the 1-bit display data in the first buffer memory is displayed in the next complete display period and the next 1-bit display data is received,
when 1-bit high-order display data is received in one complete display period, the following latch enable signal is a first type valid signal;
when 1-bit low-order display data is received in one complete display period, the following latch enable signal is a second type valid signal;
after one incomplete display period, the next latch enable signal is a third type of valid signal.
2. The display method according to claim 1, wherein each of the low-order display data corresponds to 1/2 of a complete display period of the non-complete display period n Wherein n relates to the ranking of the lower display data in the set of display data.
3. The display method of claim 1, wherein,
the LED display screen is provided with a plurality of display units, each display unit corresponds to one group of display data, 1-bit display data in one group of display data of each display unit is received in series in one complete display period, the corresponding display unit displays one group of display data of each display unit,
the display unit includes 1 or more LED lamps.
4. The display method of claim 1, wherein,
one set of display data includes 8-bit display data, including 4-bit high-order display data and 4-bit low-order display data,
the 1 st low-order display data corresponds to 1/2 of a complete display period of the incomplete display period, and the n low-order display data corresponds to 1/2 of the complete display period of the incomplete display period n N is the ranking of the lower display data in the set of display data.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010760105.2A CN111916023B (en) | 2020-07-31 | 2020-07-31 | LED display screen and display method thereof |
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| CN202010760105.2A CN111916023B (en) | 2020-07-31 | 2020-07-31 | LED display screen and display method thereof |
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| CN111916023B true CN111916023B (en) | 2023-09-12 |
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| CN114664238B (en) * | 2022-03-23 | 2023-09-19 | 无锡力芯微电子股份有限公司 | PWM data synchronization method for LED display |
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| CN101937643A (en) * | 2010-09-21 | 2011-01-05 | 深圳市中庆微科技开发有限公司 | Method for evenly distributing and increasing display frequency |
| CN101989397A (en) * | 2009-08-07 | 2011-03-23 | 康佳集团股份有限公司 | Method for increasing refresh rate of LED (Light Emitting Diode) display screen |
| CN102044216A (en) * | 2010-09-14 | 2011-05-04 | 杭州士兰微电子股份有限公司 | LED display system and LED driving circuits |
| CN103310733A (en) * | 2013-06-24 | 2013-09-18 | 深圳市明微电子股份有限公司 | LED driving method and LED driving system both supportive of multi-data-packet latching |
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2020
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101989397A (en) * | 2009-08-07 | 2011-03-23 | 康佳集团股份有限公司 | Method for increasing refresh rate of LED (Light Emitting Diode) display screen |
| CN102044216A (en) * | 2010-09-14 | 2011-05-04 | 杭州士兰微电子股份有限公司 | LED display system and LED driving circuits |
| CN101937643A (en) * | 2010-09-21 | 2011-01-05 | 深圳市中庆微科技开发有限公司 | Method for evenly distributing and increasing display frequency |
| CN103310733A (en) * | 2013-06-24 | 2013-09-18 | 深圳市明微电子股份有限公司 | LED driving method and LED driving system both supportive of multi-data-packet latching |
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