CN116312387A

CN116312387A - Gate driving circuit, driving method thereof and display panel

Info

Publication number: CN116312387A
Application number: CN202310341183.2A
Authority: CN
Inventors: 龚奎; 齐栋宇; 卢慧玲
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd
Priority date: 2023-03-31
Filing date: 2023-03-31
Publication date: 2023-06-23

Abstract

The embodiment of the application provides a gate driving circuit, a driving method thereof and a display panel, wherein the gate driving circuit comprises a plurality of cascaded shift registers, and in the shift registers, a first light-emitting control signal output module is used for responding to the conduction level of a control end of the first light-emitting control signal output module and transmitting a first level voltage signal provided by a first level voltage end to a first output end of the shift register; in the first target mode, at least part of the stage that the control end of the first light-emitting control signal output module is at the conducting level, the switch module is conducted, and the scanning signal output module responds to the conducting level of the control end of the first light-emitting control signal output module and transmits the enabling level of the scanning clock signal provided by the first scanning clock signal end to the second output end of the shift register. According to the embodiment of the application, the width of the frame of the display screen can be effectively reduced, and then the narrow frame design of the display screen is fully realized.

Description

Gate driving circuit, driving method thereof and display panel

Technical Field

The application belongs to the technical field of display panels, and particularly relates to a gate driving circuit, a driving method thereof and a display panel.

Background

In the technical field of display panels, a narrow bezel of a display screen is always one of the characteristics sought for in screen design, and the narrow bezel is also popular with users. Therefore, how to realize a narrow frame is always a popular design issue. At present, the design of the narrow frame is always an improved design in the non-circuit direction, and the narrow frame is realized by compressing the packaging width and changing the packaging mode; alternatively, the narrow frame is realized by compressing the frame wiring width, adjusting the circuit wiring space, and the like. The circuit device composition is not changed in practice in the process of realizing the narrow frame. With the rapid development of display technology, currently, under such a narrow frame improvement design scheme based on a non-circuit direction, the display screen basically compresses the width to be close to the limit, and further frame compression cannot be performed by adopting such scheme.

Based on this, how to realize further compression to the display screen frame to the maximum degree satisfies the user's demand to the narrow frame design of display screen, still is the technical problem that needs to be solved in the industry at present.

Disclosure of Invention

The embodiment of the application provides a grid driving circuit, a driving method thereof and a display panel, which can effectively reduce the frame width of a display screen, and further fully realize the narrow frame design of the display screen.

In a first aspect, an embodiment of the present application provides a gate driving circuit, where the gate driving circuit includes a plurality of cascaded shift registers, and the shift registers include a scan signal output module, a switch module, and a first light emitting control signal output module;

the first end of the first light-emitting control signal output module is electrically connected with a first level voltage end, the second end of the first light-emitting control signal output module is electrically connected with a first output end of the shift register, and the first light-emitting control signal output module is used for responding to the conduction level of the control end of the first light-emitting control signal output module and transmitting a first level voltage signal provided by the first level voltage end to the first output end of the shift register;

the first end of the switch module is electrically connected with the control end of the first luminous control signal output module, and the second end of the switch module is electrically connected with the control end of the scanning signal output module;

the first end of the scanning signal output module is electrically connected with the first scanning clock signal end, and the second end of the scanning signal output module is electrically connected with the second output end of the shift register;

in the first target mode, at least part of the stage that the control end of the first light-emitting control signal output module is at the conducting level, the switch module is conducted, and the scanning signal output module responds to the conducting level provided by the first node and transmits the enabling level of the scanning clock signal provided by the first scanning clock signal end to the second output end of the shift register.

In a possible implementation manner of the first aspect, the switch module includes a first control signal end and a second control signal end, and the switch module is specifically configured to, in at least a portion of a stage in which the control end of the first light emitting control signal output module is at a conducting level, respond to the conducting level provided by the first control signal end and the conducting level provided by the second control signal end to conduct, and transmit the conducting level of the control end of the first light emitting control signal output module to the control end of the scanning signal output module, so that the conducting or switching control of the switch module can be more reasonably realized.

In a possible implementation manner of the first aspect, the switching module comprises a first switching unit and a second switching unit; the control end of the first switch unit is electrically connected with the first control signal end, the first end of the first switch unit is electrically connected with the control end of the first light-emitting control signal output module, the second end of the first switch unit is electrically connected with the first end of the second switch unit, and the first switch unit is used for responding to the conduction level provided by the first control signal end and transmitting the electric potential of the control end of the first light-emitting control signal output module to the first end of the second switch unit; the control end of the second switch unit is electrically connected with the second control signal end, the second end of the second switch unit is electrically connected with the second output end of the shift register, and the second switch unit is used for responding to the conduction level provided by the second control signal end and transmitting the level of the first end of the second switch unit to the second output end of the shift register. Therefore, reasonable conduction control of the switch module can be further realized based on the first control signal end and the second control signal end.

In one possible implementation manner of the first aspect, in combination with consideration of an actual operation scenario of the multi-stage shift register in the gate driving circuit, for further achieving the purpose of reducing the frame width, multiplexing the output signals of the first output terminals of the corresponding row shift register may be considered and provided to the first control signal terminal and the second control signal terminal. Based on the above, one of the first control signal end and the second control signal end of any N-th shift register in the gate driving circuit is electrically connected with the first output end of the N-2-th shift register, the other is electrically connected with the first output end of the n+1-th shift register, and N is a positive integer greater than 2. Therefore, the realization of the narrow frame of the display screen is further facilitated through reasonable signal multiplexing of the cascaded shift registers.

In one possible implementation manner of the first aspect, a start time of a disable level of the light emission control signal provided by the first output terminal of the nth stage shift register is separated from a start time of a disable level of the light emission control signal provided by the first output terminal of the n+1th stage shift register by a first duration, and a duration of the enable level of the first scan clock signal provided by the first scan clock signal terminal is a second duration, where the first duration is greater than or equal to the second duration.

In a possible implementation manner of the first aspect, the first period is one half of a period during which the first output terminal of the first stage shift register provides the non-enable level of the light emission control signal.

In a possible implementation manner of the first aspect, in the first target mode, an end time of the non-enable level of the light emission control signal provided by the first output terminal of the N-2 th stage shift register is before a start time of the non-enable level of the light emission control signal provided by the first output terminal of the n+1 th stage shift register, and the interval time is longer than or equal to a duration of the enable level of the first scan clock signal provided by the first scan clock signal terminal; at least part of the stage between the end time of the non-enabling level of the light-emitting control signal provided by the first output end of the N-2 level shift register and the start time of the non-enabling level of the light-emitting control signal provided by the first output end of the N+1th level shift register, the light-emitting control signal provided by the first output end of the N level shift register is the non-enabling level, the control end of the first light-emitting control signal output module in the N level shift register is the conducting level, the switch module is conducted, and the scanning signal output module responds to the conducting level of the control end of the first light-emitting control signal output module and transmits the enabling level of the scanning clock signal provided by the first scanning clock signal end to the second output end of the shift register.

In a possible implementation manner of the first aspect, in the second target mode, a phase of a non-enable level of the light emission control signal provided at the first output terminal of the N-2 th stage shift register overlaps a phase of a non-enable level of the light emission control signal provided at the first output terminal of the n+1th stage shift register, the switching module in the N-th stage shift register is always turned off, and the scan signal output module does not output the scan clock signal provided at the first scan clock signal terminal;

in a possible implementation manner of the first aspect, in a display frame, the first target mode is located before the second target mode.

In a possible implementation manner of the first aspect, a duration of the non-enable level of the trigger signal input at the input terminal of the shift register in the second target mode is longer than a duration of the non-enable level of the trigger signal input at the input terminal of the shift register in the first target mode.

In a possible implementation manner of the first aspect, the first level voltage signal provided by the first level voltage terminal is transmitted to the first output terminal of the shift register as the non-enable level of the light emission control signal.

In a possible implementation manner of the first aspect, one of the first scan clock signal terminals of the shift registers of two adjacent stages is electrically connected to the first scan clock signal line, and the other is electrically connected to the second scan clock signal line; the phase of the scanning clock signal output by the first scanning clock signal line and the phase of the scanning clock signal provided by the second scanning clock signal line are different by a first time length which is one half of the time length of the non-enabling level of the light-emitting control signal provided by the first output end of the first-stage shift register.

In a possible implementation manner of the first aspect, the shift register further includes a first light-emitting clock signal terminal and a second light-emitting clock signal terminal; the first light-emitting clock signal end of the 3M+1 stage shift register is electrically connected with the first light-emitting clock signal line, and the second light-emitting clock signal end of the 3M+1 stage shift register is electrically connected with the second light-emitting clock signal line; the first light-emitting clock signal end of the 3M+2-stage shift register is electrically connected with the second light-emitting clock signal line, and the second light-emitting clock signal end of the 3M+2-stage shift register is electrically connected with the third light-emitting clock signal line; the first light-emitting clock signal end of the 3M+3 stage shift register is electrically connected with the third light-emitting clock signal line, the second light-emitting clock signal end of the 3M+3 stage shift register is electrically connected with the first light-emitting clock signal line, and M is an integer greater than or equal to 0.

In one possible implementation manner of the first aspect, the periods of the first light-emitting clock signal provided by the first light-emitting clock signal line, the second light-emitting clock signal provided by the second light-emitting clock signal line, and the third light-emitting clock signal provided by the third light-emitting clock signal line are all target light-emitting clock signal periods, and phases among the first light-emitting clock signal, the second light-emitting clock signal, and the third light-emitting clock signal are sequentially delayed by 1/3 of the target light-emitting clock signal periods.

In a possible implementation manner of the first aspect, a phase difference between a signal input at an input terminal of the shift register and a light emission control signal output at a first output terminal of the shift register is a first duration, and the first duration is one half of a duration of a non-enable level of the light emission control signal provided at the first output terminal of the first stage shift register.

In a possible implementation manner of the first aspect, an input terminal of the 1 st stage shift register is electrically connected to the trigger signal terminal, and an input terminal of the K stage shift register is electrically connected to the first output terminal of the K-1 st stage shift register, where K is a positive integer greater than or equal to 2.

In a possible implementation manner of the first aspect, the shift register further includes a first light-emitting clock signal terminal and a second light-emitting clock signal terminal; in a second target mode, the input end of the shift register inputs a trigger signal, the target luminous clock signal provided by the target luminous clock signal end at least contains two enabling levels in the phase of non-enabling level of the trigger signal, the switch module is always cut off, and the scanning signal output module does not output a scanning clock signal; the target light-emitting clock signal end is a first light-emitting clock signal end or a second light-emitting clock signal end.

In a possible implementation manner of the first aspect, the shift register further includes a light emission control signal shift control module, where the light emission control signal shift control module includes a first light emission clock signal end, a second light emission clock signal end, and an input end of the shift register, a first output end of the light emission control signal shift control module is electrically connected to a control end of the first light emission control signal output module, and a second output end of the light emission control signal shift control module is electrically connected to a control end of the second light emission control signal output module; the light-emitting control signal shift control module is used for outputting an on level or an off level by a first output end of the light-emitting control signal shift control module and outputting the on level or the off level by a second output end of the light-emitting control signal shift control module under the control of the first light-emitting clock signal end, the second light-emitting clock signal end and the shift register input end.

In a possible implementation manner of the first aspect, the shift register further includes a bootstrap module; the first end of the bootstrap module is electrically connected with the second end of the scanning signal output module, and the second end of the bootstrap module is electrically connected with the control end of the scanning signal output module.

In a possible implementation manner of the first aspect, the bootstrap module includes a bootstrap capacitor, a first pole of the bootstrap capacitor is electrically connected to the second end of the scan signal output module, and a second pole of the bootstrap capacitor is electrically connected to the control end of the scan signal output module.

In a possible implementation manner of the first aspect, the shift register further includes a second light emission control signal output module; the first end of the second light-emitting control signal output module is electrically connected with the second level voltage end, the second end of the second light-emitting control signal output module is electrically connected with the first output end of the shift register, and the second light-emitting control signal output module is used for responding to the conduction level of the control end of the second light-emitting control signal output module and transmitting a second level voltage signal provided by the second level voltage end to the first output end of the shift register.

Based on the same inventive concept, in a second aspect, an embodiment of the present application provides a driving method of a gate driving circuit, where the driving method of the gate driving circuit is applied to the gate driving circuit provided in any one of the foregoing embodiments of the first aspect of the present application, the driving method of the gate driving circuit includes:

in the first target mode, at least part of the stage that the control end of the first light-emitting control signal output module is at the conducting level, the control switch module is conducted, so that the scanning signal output module responds to the conducting level of the control end of the first light-emitting control signal output module, and the enabling level of the scanning clock signal provided by the first scanning clock signal end is transmitted to the second output end of the shift register.

Based on the same inventive concept, in a third aspect, an embodiment of the present application provides a shift register, which includes a scan signal output module, a switch module, and a first light emitting control signal output module;

at least part of the stage that the first node is at the conduction level, the switch module is conducted, and the scanning signal output module responds to the conduction level of the control end of the first light-emitting control signal output module and transmits the scanning clock signal provided by the first scanning clock signal end to the second output end of the shift register.

Based on the same inventive concept, in a fourth aspect, the present embodiment provides a display panel including the gate driving circuit as provided in any one of the foregoing embodiments of the first aspect of the present application.

Based on the same inventive concept, in a fifth aspect, the present embodiment provides a display device including the display panel as provided in the embodiment of the fourth aspect of the present application.

According to the grid driving circuit, the driving method thereof and the display panel, the switch module and the scanning signal output module are added on the basis of a traditional shift register, and the first end of the switch module is electrically connected with the control end of the first light-emitting control signal output module. In this way, when the control end of the first light-emitting control signal output module is at a conduction level, the first light-emitting control signal output module is conducted, and a first level voltage signal provided by a first level voltage end is transmitted to a first output end of the shift register; and at least part of the stage that the control end of the first light-emitting control signal output module is at the conduction level, the switch module is conducted, and the scanning signal output module responds to the conduction level of the control end of the first light-emitting control signal output module and transmits the scanning clock signal provided by the first scanning clock signal end to the second output end of the shift register. According to the grid driving circuit, the driving method thereof and the display panel, the characteristic that the scanning driving signal takes effect when the non-enabling level is output by the light-emitting control signal is utilized, and the grid signal of the non-enabling level output tube in the shift register is used as the grid of the scanning driving signal output tube, so that the existing Scan circuit and the existing EM circuit are combined, the number of devices is greatly reduced, and the effect of reducing the frame width of the display screen can be fully achieved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described, and it is possible for a person skilled in the art to obtain other drawings according to these drawings without inventive effort.

Fig. 1 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a shift register according to an embodiment of the present application;

FIG. 3 is a schematic diagram of another shift register according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a shift register according to another embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of another gate driving circuit according to an embodiment of the present disclosure;

FIG. 6 is a timing diagram of a gate driving circuit according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of another gate driving circuit according to an embodiment of the present disclosure;

fig. 8 is a timing diagram of a gate driving circuit according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of another gate driving circuit according to an embodiment of the present disclosure;

FIG. 10 is a timing diagram of a gate driving circuit according to an embodiment of the present disclosure;

Fig. 11 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present application;

fig. 12 is a timing diagram of a gate driving circuit according to an embodiment of the present disclosure;

fig. 13 is a timing diagram of a gate driving circuit in a second target mode according to an embodiment of the present disclosure;

FIG. 14 is a schematic diagram of simulated output waveforms of a gate driving circuit in a first target mode according to an embodiment of the present disclosure;

FIG. 15 is a schematic diagram of simulated output waveforms of the gate driving circuit in the second target mode according to the embodiment of the present application;

FIG. 16 is a schematic diagram of a shift register according to another embodiment of the present disclosure;

FIG. 17 is a schematic diagram of a shift register according to another embodiment of the present disclosure;

FIG. 18 is a schematic diagram of a shift register according to another embodiment of the present disclosure;

FIG. 19 is a schematic diagram of a shift register according to another embodiment of the present disclosure;

FIG. 20 is a schematic diagram of a shift register according to another embodiment of the present disclosure;

fig. 21 is a schematic flow chart of a driving method of a gate driving circuit according to an embodiment of the present application;

fig. 22 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

Fig. 23 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

Features and exemplary embodiments of various aspects of the present application are described in detail below to make the objects, technical solutions and advantages of the present application more apparent, and to further describe the present application in conjunction with the accompanying drawings and the detailed embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative of the application and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by showing examples of the present application.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of additional identical elements in a process, method, article, or apparatus that comprises the element.

It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

It should be noted that, the transistor in the embodiment of the present application may be an N-type transistor or a P-type transistor. For an N-type transistor, the on level is high and the off level is low. That is, the gate of the N-type transistor is on between the first and second poles when the gate is high, and is off between the first and second poles when the gate is low. For a P-type transistor, the on level is low and the off level is high. That is, the gate of the P-type transistor is on between the first and second poles when the gate is low, and is off between the first and second poles when the gate is high. In a specific implementation, the gate of each transistor is used as a control electrode, and the first electrode of each transistor may be used as a source electrode, the second electrode may be used as a drain electrode, or the first electrode may be used as a drain electrode, and the second electrode may be used as a source electrode, which is not distinguished herein.

In the embodiments herein, the term "electrically connected" may refer to two components being directly electrically connected, or may refer to two components being electrically connected via one or more other components.

In the embodiment of the present application, the first node, the second node, and the third node are defined only for convenience in describing the circuit structure, and the first node, the second node, and the third node are not one actual circuit unit.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Accordingly, this application is intended to cover such modifications and variations of this application as fall within the scope of the appended claims (the claims) and their equivalents. The embodiments provided in the examples of the present application may be combined with each other without contradiction.

Before describing the technical solution provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

as described above, the inventors of the present application have found that, in realizing a narrow frame design, the following are adopted: the display screen width has been compressed to near the limit by means of, for example, compressing the package width, changing the package, etc., or by means of compressing the frame wiring width, adjusting the circuit wiring space, etc., with which the frame has not been further compressed, so that it is possible to consider further compression of the frame by changing the circuit structure.

Based on this, the present inventors have carefully studied and found that a Scan circuit for controlling data writing, resetting, and the like in a pixel circuit and an EM circuit for Gate driving a light emission control tube in the pixel circuit are generally included in GIP (Gate in Panel) in a display Panel. In actual operation, the Scan circuit will only assert the output enable level if the EM circuit outputs a disable level. Therefore, the characteristics can be considered to be utilized, and the grid signals of the non-enabled level output tube in the EM circuit are multiplexed into the grid signals of the output tube of the EM circuit, so that the number of frame devices is reduced, and the purpose of reducing the width of the frame is achieved.

In view of the above-mentioned research of the inventor, in order to solve the problems of the prior art, embodiments of the present application provide a gate driving circuit, a driving method thereof, and a display panel. It should be noted that the examples provided herein are not intended to limit the scope of the disclosure.

The following first describes a gate driving circuit provided in an embodiment of the present application.

Fig. 1 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present application. The gate driving circuit 10 includes a plurality of shift registers 1 in cascade.

The shift register 1 included in the gate driving circuit 10 is described in detail below. Referring to fig. 2, fig. 2 is a schematic structural diagram of a shift register according to an embodiment of the present application. As shown in fig. 2, for any shift register 1 in the gate driving circuit 10, the shift register 1 includes a scanning signal output module 101, a switching module 102, and a first light emission control signal output module 103.

Specifically, the control end of the first light emitting control signal output module 103 is electrically connected to the first node N1, the first end of the first light emitting control signal output module 103 is electrically connected to the first level voltage end VGH, and the second end of the first light emitting control signal output module 103 is electrically connected to the first output end EM of the shift register 1.

The first light emission control signal output module 103 is specifically configured to be turned on under the control of the on level provided by the first node N1, and transmit the first level voltage signal provided by the first level voltage terminal VGH to the first output terminal EM of the shift register 1 as the non-enable level of the light emission control signal.

The first end of the switch module 102 is electrically connected to the first node N1, and the second end of the switch module 102 is electrically connected to the control end of the scan signal output module 101. The first end of the scan signal output module 101 is electrically connected to the first scan clock signal terminal sck, and the second end of the scan signal output module 101 is electrically connected to the second output terminal SN of the shift register 1.

In the first target mode, during at least a portion of the period when the first node N1 is at the on level, the switch module 102 is turned on, and the on level of the first node N1 is transmitted to the control terminal of the scan signal output module 101 through the turned-on switch module 102. The scan signal output module 101 is turned on under the control of the turn-on level provided by the first node N1, and transmits the enable level of the scan clock signal provided by the first scan clock signal terminal sck to the second output terminal SN of the shift register 1. The disable level and enable level may be high and low opposite. For example, the disable level may be a high level and the enable level may be a low level.

It should be understood that the first target mode is specifically an operation mode that allows the shift register 1 in the gate driving circuit 10 to transmit the scan clock signal provided by the first scan clock signal terminal sck to the second output terminal SN of the shift register 1 during at least a portion of the period when the first node N1 is at the on level.

In the gate driving circuit 10 provided in the embodiment of the present application, the switch module 102 and the scan signal output module 101 are added on the basis of a conventional shift register, and the first end of the switch module 102 is electrically connected to the first node N1. Thus, when the first node N1 is at the on level, the first light emitting control signal output module 103 in the EM circuit is turned on, and the first level voltage signal provided by the first level voltage terminal VGH is transmitted to the first output terminal of the shift register 1. And, during at least a portion of the period when the first node N1 is at the on level, the switch module 102 is turned on, and the scan signal output module 103 transmits the enable level of the scan clock signal provided by the first scan clock signal terminal to the second output terminal of the shift register 1 in response to the on level provided by the first node.

According to the grid driving circuit 10, the characteristic that the scanning driving signal takes effect when the non-enabling level is output by the light-emitting control signal is utilized, the grid signal of the non-enabling level output tube in the shift register 1 is used as the grid of the scanning driving signal output tube, so that the existing Scan circuit and the existing EM circuit are combined, the number of devices is greatly reduced, and the effect of reducing the frame width of the display screen can be fully achieved.

Referring to fig. 3, fig. 3 is a schematic structural diagram of another shift register according to an embodiment of the present application. In some more specific embodiments, as shown in fig. 3, in order to more reasonably realize on or off control of the switch module 102, optionally, a control terminal of the switch module 102 may include a first control signal terminal G1 and a second control signal terminal G2.

The switch module 102 may be specifically configured to transmit, at least in a portion of the period when the first node N1 is at the on level, the on level of the first node N1 to the control terminal of the scan signal output module 101 in response to the on level provided by the first control signal terminal G1 and the on level provided by the second control signal terminal G2.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a shift register according to another embodiment of the present application. As shown in fig. 4, in some more specific embodiments, in order to further implement reasonable conduction control of the switch module 102 based on the first control signal terminal G1 and the second control signal terminal G2, the switch module 102 may specifically include a first switch unit 1021 and a second switch unit 1022.

The control terminal of the first switch unit 1021 is electrically connected to the first control signal terminal G1, the first terminal of the first switch unit 1021 is electrically connected to the first node N1, and the second terminal of the first switch unit 1021 is electrically connected to the first terminal of the second switch unit 1022. The first switching unit 1021 may be configured to transmit a node potential of the first node N1 to a first terminal of the second switching unit 1022 in response to an on level provided by the first control signal terminal G1.

The control terminal of the second switch unit 1022 is electrically connected to the second control signal terminal G2, and the second terminal of the second switch unit 1022 is electrically connected to the second output terminal SN of the shift register 1. The control terminal of the second switching unit 1022 may be configured to transmit the on level of the first terminal of the second switching unit 1022 to the second output terminal SN of the shift register 1 in response to the on level provided by the second control signal terminal G2.

It should be understood that only one possible embodiment in which the first switching unit 1021 is electrically connected to the first control signal terminal G1 and the control terminal of the second switching unit 1022 is electrically connected to the second control signal terminal G2 is shown in fig. 4. In other embodiments, the first switch unit 1021 may be electrically connected to the second control signal terminal G2, and the second switch unit 1022 may be electrically connected to the first control signal terminal G1, which is not particularly limited in this application.

Note that, the first switch unit 1021 and the second switch unit 1022 may be transistors, and the control terminals of the first switch unit 1021 and the second switch unit 1022 may be gates of the transistors.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present application. In some more specific embodiments, as shown in fig. 5, in combination with the actual operation scenario of the multi-stage shift register 1 in the gate driving circuit 10, for further achieving the purpose of reducing the frame width, it may be considered to multiplex the output signals of the first output terminals EM of the corresponding row shift registers 1 and provide them to the first control signal terminal G1 and the second control signal terminal G2. Based on this, one of the first control signal terminal G1 and the second control signal terminal G2 connected to any nth stage shift register 1 in the gate driving circuit 10 is electrically connected to the first output terminal EM of the one stage shift register 1 (may be referred to as an xth stage shift register 1) preceding the nth stage shift register 1, and the other is electrically connected to the first output terminal EM of the one stage shift register 1 (may be referred to as a Y stage shift register 1) following the nth stage shift register 1. The end time of the non-enable level of the first output terminal EM of the x-th stage shift register 1 is before the start time of the non-enable level of the first output terminal EM of the Y-th stage shift register 1, and a time interval between the end time of the non-enable level of the first output terminal EM of the x-th stage shift register 1 and the start time of the non-enable level of the first output terminal EM of the Y-th stage shift register 1 is greater than or equal to a duration of the enable level of the first scan clock signal supplied by the first scan clock signal terminal sck. By the arrangement, at least part of the stage between the end time of the non-enabling level of the light-emitting control signal provided by the first output end of the X-th shift register and the start time of the non-enabling level of the light-emitting control signal provided by the first output end of the Y-th shift register can be ensured in the first target mode, the stage is equivalent to the stage, the levels of the first control signal end and the second control signal end of the switch module in the X-th shift register and the Y-th shift register are enabled, the light-emitting control signal provided by the first output end of the N-th shift register is enabled, the control end of the first light-emitting control signal output module of the N-th shift register is enabled, the first control signal end of the X-th shift register and the enabling level of the second control signal end are output to the N-th shift register, the scan signal output module of the N-th shift register is enabled to respond to the first control signal output end of the first light-emitting control signal output end of the first shift register, and the scan signal output end of the scan signal is enabled to be enabled.

In the gate driving circuit 10 shown in fig. 5, one of the first control signal terminal G1 and the second control signal terminal G2, which are connected to any nth stage shift register 1, is electrically connected to the first output terminal EM of the N-2 th stage shift register 1, and the other is electrically connected to the first output terminal EM of the n+1th stage shift register 1, where N is a positive integer greater than 2. Illustratively, the first control signal terminal G1 connected to any nth stage shift register 1 is electrically connected to the first output terminal EM of the N-2 th stage shift register 1, and the second control signal terminal G2 connected to any nth stage shift register 1 is electrically connected to the first output terminal EM of the n+1th stage shift register 1. Illustratively, the first control signal terminal G1 connected to the n+2 stage shift register 1 is electrically connected to the first output terminal EM of the N stage shift register 1, and the second control signal terminal G2 connected to any N stage shift register 1 is electrically connected to the first output terminal EM of the n+3 stage shift register 1.

Referring to fig. 5, the first control signal terminal G1< N > of the nth stage shift register 1 in fig. 5 is actually electrically connected to the EM < N-2>, i.e., the first output terminal EM of the nth-2 stage shift register 1; the second control signal terminal G2< N > is actually electrically connected to the EM < n+1>, i.e. to the first output terminal EM of the n+1th stage shift register 1.

In FIG. 5, the first control signal terminal G1< N+1> of the N+1st stage shift register 1 is actually electrically connected to the EM < N-1>, i.e., to the first output terminal EM of the N-1 st stage shift register 1; the second control signal terminal g2< n+1> is actually electrically connected to EM < n+2>, i.e. to the first output terminal EM of the n+2-th stage shift register 1.

By analogy, in FIG. 5, G1< N+2> is actually electrically connected to EM < N >, G2< N+2> is actually electrically connected to EM < N+3>, G1< N+3> is actually electrically connected to EM < N+1>, and G2< N+3> is actually electrically connected to EM < N+4>, which is not described in detail herein.

It should be understood that the first control signal terminal G1 connected to any nth stage shift register 1 may also be electrically connected to the first output terminal EM of the n+1th stage shift register 1, and accordingly, the second control signal terminal G2 connected to any nth stage shift register 1 is electrically connected to the first output terminal EM of the N-2 th stage shift register 1, which is not particularly limited in this application.

Referring to fig. 6, fig. 6 is a timing diagram of a gate driving circuit according to an embodiment of the present application. As shown in fig. 6, in some more specific embodiments, optionally, in combination with the foregoing signal multiplexing situation of the first control signal terminal G1 and the second control signal terminal G2 to the first output terminal EM of the cascaded shift register 1, in order to more reasonably implement cascading and signal multiplexing of a plurality of rows of shift registers in the gate driving circuit 10, in the gate driving circuit 10 of the present application, a start time of a non-enable level of a light emission control signal provided by the first output terminal EM of the nth stage shift register 1 and a start time of a non-enable level of a light emission control signal provided by the first output terminal EM of the n+1th stage shift register 1 are separated by a first time period t1, and a duration of an enable level of the first scan clock signal provided by the first scan clock signal terminal sck is a second time period t2, where the first time period t1 is greater than or equal to the second time period t2.

Illustratively, the signals EM <1>, S <1> in fig. 6 may be the emission control signal output from the first output terminal EM < N > and the scan signal output from the second output terminal SN < N > of the nth stage shift register 1. The signals EM <2>, S <2> in fig. 6 may be the light emission control signal output from the first output terminal EM < n+1> and the scan signal output from the second output terminal SN < n+1> of the n+1-th shift register 1. The signals EM <3>, S <3> in fig. 6 may be the light emission control signal output from the first output terminal EM < n+2> and the scan signal output from the second output terminal SN < n+2> of the n+2-th shift register 1. The signals EM <4>, S <4> in fig. 6 may be the light emission control signal output from the first output terminal EM < n+3> and the scan signal output from the second output terminal SN < n+3> of the n+3-th stage shift register 1.

With continued reference to fig. 6, in some more specific embodiments, the first period t1 may be, in particular, one half of the period during which the first output terminal EM of the primary shift register 1 provides the non-enable level of the emission control signal.

In the present embodiment, considering a specific implementation scenario, a period of time (half EM high level time in the present embodiment) of a non-enable level of the light emission control signal is set to be different between output signals of the first output terminals EM of the shift registers 1 of adjacent two stages. Thus, in combination with the foregoing example, it is possible to realize that the first output terminal EM of the next stage shift register 1 outputs the disable level in the case where the second output terminal SN of the present stage shift register 1 outputs the enable level. In the stage that the first output end EM of the shift register 1 and the first output end EM of the next shift register 1 output the non-enable level, the second output end SN of the next shift register 1 outputs the enable level, which is beneficial to providing corresponding scanning signals for the corresponding row of pixel circuits in the non-light-emitting stage. The pixel circuit may include a driving transistor, a data writing transistor, a gate initializing transistor, a light emission control transistor, an anode initializing transistor, a threshold compensating transistor, and the like. The emission control signal output from the first output EM of the shift register 1 of this stage can be used for the emission control signal of the emission control transistor in the pixel circuit of this row. The scan signal output by the second output terminal SN of the shift register 1 of the present stage may be used as a scan signal of a gate initialization transistor of the pixel circuit of the present line to control on or off of the gate initialization transistor of the pixel circuit of the present line, and may also be used as a scan signal of a data writing transistor of the pixel circuit of the previous line to control on or off of the data writing transistor of the pixel circuit of the previous line.

In some more specific embodiments, in the first target mode, the end time of the disable level of the light emission control signal provided at the first output terminal of the N-2 th stage shift register is before the start time of the disable level of the light emission control signal provided at the first output terminal of the n+1 th stage shift register, and the interval time is longer than or equal to the duration of the enable level of the first scan clock signal provided at the first scan clock signal terminal.

In some more specific embodiments, in the first target mode (corresponding to the refresh period), at least part of the period between the end time of the disable level of the light emission control signal provided at the first output terminal of the N-2 th stage shift register and the start time of the disable level of the light emission control signal provided at the first output terminal of the n+1th stage shift register corresponds to the level at which the N-2 th stage shift register and the n+1th stage shift register output to the first control signal terminal and the second control signal terminal of the switching module in the N-th stage shift register, the switching module in the N-th stage shift register is turned on, the light emission control signal provided at the first output terminal of the N-th stage shift register is turned on, and the control terminal of the first light emission control signal output module in the N-th stage shift register is turned on, and the scanning signal output module in the N-th stage shift register outputs the enable clock signal provided at the first clock signal terminal to the second output terminal of the second shift register in response to the on level of the control terminal of the first light emission control signal output module.

In some more specific embodiments, in the second target mode (corresponding to the black insertion stage), the stage of the disable level of the light emission control signal provided at the first output terminal of the N-2 th stage shift register overlaps with the stage of the disable level of the light emission control signal provided at the first output terminal of the n+1th stage shift register, corresponding to the level average of the first control signal terminal and the second control signal terminal of the switching module output from the N-2 th stage shift register and the n+1th stage shift register to the N-th stage shift register is the disable level, the switching module in the N-th stage shift register is always turned off, and the scanning signal output module does not output the scanning clock signal provided from the first scanning clock signal terminal.

In some more specific embodiments, the first target mode may be located before the second target mode in a display frame in consideration of an actual display scene.

In some more specific embodiments, in the case where each clock signal in the second target mode is consistent with each clock signal in the first target mode, a duration of the non-enable level of the trigger signal input to the input terminal of the shift register in the second target mode may be greater than a duration of the non-enable level of the trigger signal input to the input terminal of the shift register in the first target mode.

Referring to fig. 7, fig. 7 is a schematic structural diagram of another gate driving circuit according to an embodiment of the present application. As shown in fig. 7, in some more specific embodiments, the gate driving circuit 10 may optionally include a first scan clock signal line SCK1 and a second scan clock signal line SCK2 therein. One of the first scan clock signal terminals SCK of the shift register 1 of two adjacent stages is electrically connected to the first scan clock signal line SCK1, and the other is electrically connected to the second scan clock signal line SCK2. In other words, the first scan clock signal lines SCK1 and the second scan clock signal lines SCK2 described above alternately appear in the cascade of shift registers 1, thereby achieving reasonable multiplexing of the first scan clock signal lines SCK1 and the second scan clock signal lines SCK2 by the plurality of rows of shift registers 1 in the gate driving circuit 10. The first scan clock signal line SCK1 and the second scan clock signal line SCK2 may have the same frequency.

In this embodiment, considering a specific implementation scenario, when the first output terminal EM of each stage of the shift register 1 outputs the disable level, two SCK signals provided by the first scan clock signal line SCK1 and the second scan clock signal line SCK2 are output to the second output terminal SN of the shift register 1 in odd-even rows. The second output terminals SN of the shift registers 1 of two adjacent stages may be electrically connected to corresponding scan signal terminals in the pixel circuit, respectively, for providing corresponding scan signals for the pixel circuit in the working phases such as reset charging in the non-light-emitting phase.

Further, considering that in the case where the above-described first scan clock signal line SCK1 and second scan clock signal line SCK2 alternately appear in the cascade-connected shift register 1, the timing between the first scan clock signal line SCK1 and the second scan clock signal line SCK2 also needs to be correspondingly alternately set.

Based on this, fig. 8 may be specifically combined, and fig. 8 is a timing diagram of another gate driving circuit according to an embodiment of the present application. As shown in fig. 8, the phase of the scan clock signal output by the first scan clock signal line SCK1 and the phase of the scan clock signal provided by the second scan clock signal line SCK2 differ by a first time period t1, where the first time period t1 may be one half of the duration of the non-enable level of the light emission control signal provided by the first output terminal EM of the first shift register 1.

Referring to fig. 9, fig. 9 is a schematic structural diagram of a gate driving circuit according to another embodiment of the present application. As shown in fig. 9, in some more specific embodiments, the gate driving circuit 10 may use three light-emitting clock signal lines, respectively: the first, second and third light-emitting clock signal lines ECK1, ECK2 and ECK3 may have the same frequency. The shift register 1 may further include a first light-emitting clock signal terminal and a second light-emitting clock signal terminal.

In particular, regarding the cascade multiplexing relationship among the first light-emitting clock signal line ECK1, the second light-emitting clock signal line ECK2, and the third light-emitting clock signal line ECK3, please continue to refer to fig. 9. In fig. 9, when the multi-row shift register 1 in the gate driving circuit 10 is operated, the first light-emitting clock signal end of the 3m+1 stage shift register 1 may be electrically connected to the first light-emitting clock signal line ECK1, and the second light-emitting clock signal end of the 3m+1 stage shift register 1 may be electrically connected to the second light-emitting clock signal line ECK2, where M is an integer greater than or equal to 0. Exemplary, an nth stage shift register 1 in fig. 9.

In the gate driving circuit 10, the first light emitting clock signal terminal of the 3m+2 stage shift register 1 may be electrically connected to the second light emitting clock signal line ECK2, and the second light emitting clock signal terminal of the 3m+2 stage shift register 1 may be electrically connected to the third light emitting clock signal line ECK 3. Exemplary is the n+1st stage shift register 1 in fig. 9.

The first light-emitting clock signal terminal of the 3m+3 stage shift register 1 may be electrically connected to the third light-emitting clock signal line ECK3, and the second light-emitting clock signal terminal of the 3m+3 stage shift register 1 may be electrically connected to the first light-emitting clock signal line ECK 1. Exemplary is the n+2-th stage shift register 1 in fig. 9.

The plurality of shift registers 1 are divided into a plurality of groups, every 3 adjacent shift registers 1 are taken as a group, the shift registers 1 are circularly and alternately connected to three light-emitting clock signal lines, and each shift register 1 is connected with two three light-emitting clock signal lines.

In some more specific embodiments, in order to further achieve reasonable multiplexing of signals of the shift register 1 cascaded in the gate driving circuit 10, so as to effectively reduce the number of devices, thereby fully achieving a narrow frame design of the display screen, optionally, an input end of the 1 st stage shift register 1 is electrically connected to a trigger signal end, and an input end of the K stage shift register 1 is electrically connected to the first output end EM of the K-1 st stage shift register 1, where K is a positive integer greater than or equal to 2. Exemplary, as in the figure

Referring to fig. 10, fig. 10 is a timing diagram of a gate driving circuit according to another embodiment of the present disclosure. In some more specific implementations, considering in combination with the cascade multiplexing manner of the first light-emitting clock signal line ECK1, the second light-emitting clock signal line ECK2, and the third light-emitting clock signal line ECK3, in order to more reasonably realize clock control of different row shift registers 1 in the gate driving circuit 10, as shown in fig. 10, the periods of the first light-emitting clock signal provided by the first light-emitting clock signal line ECK1, the second light-emitting clock signal provided by the second light-emitting clock signal line ECK2, and the third light-emitting clock signal provided by the third light-emitting clock signal line ECK3 are all target light-emitting clock signal periods, and the phases among the first light-emitting clock signal, the second light-emitting clock signal, and the third light-emitting clock signal are sequentially delayed by 1/3 target light-emitting clock signal periods.

With continued reference to fig. 10, in some more specific embodiments, optionally, a phase difference between the signal input from the input terminal of the shift register 1 and the light emission control signal output from the first output terminal EM of the shift register 1 is a first time period t1. The first period t1 may be one-half of the period of time during which the first output terminal EM of the first stage shift register 1 supplies the non-enable level of the emission control signal

In order to more intuitively embody the timing arrangement of the gate driving circuit 10 and the cascade structure and signal multiplexing design of the shift register 1 in the present application, please refer to fig. 11 and 12, fig. 11 is a schematic structural diagram of a complete gate driving circuit provided in the embodiment of the present application, and fig. 12 is a schematic timing diagram of a complete gate driving circuit provided in the embodiment of the present application, and fig. 11 corresponds to fig. 12.

In this embodiment, by setting the cascade multiplexing structure in the gate driving circuit 1, the number of frame devices can be reduced to a great extent, and thus the frame size of the display screen can be reduced.

As shown in fig. 12, the cascade multiplexing structure in the gate driving circuit 1 is designed to be matched in terms of the corresponding timing.

Specifically, the start time of the disable level of the light emission control signal provided by the first output terminal EM of the nth stage shift register 1 is separated from the start time of the disable level of the light emission control signal provided by the first output terminal EM of the n+1th stage shift register 1 by a first time period t1, the duration of the enable level of the first scan clock signal provided by the first scan clock signal terminal sck is a second time period t2, and the first time period t1 may be greater than or equal to the second time period t2.

The phase of the scan clock signal outputted from the first scan clock signal line SCK1 is different from the phase of the scan clock signal provided from the second scan clock signal line SCK2 by a first time period t1. The periods of the first light-emitting clock signal provided by the first light-emitting clock signal line ECK1, the second light-emitting clock signal provided by the second light-emitting clock signal line ECK2 and the third light-emitting clock signal provided by the third light-emitting clock signal line ECK3 are all target light-emitting clock signal periods, and the phases among the first light-emitting clock signal, the second light-emitting clock signal and the third light-emitting clock signal are sequentially delayed by 1/3 of the target light-emitting clock signal periods.

The phase difference between the signal input from the input terminal of the shift register 1 and the emission control signal output from the first output terminal EM of the shift register 1 is a first time period t1. The first duration t1 is one half of a duration of the first output terminal EM of the primary shift register 1 providing the disable level of the emission control signal.

In order to more intuitively understand the timing design in this embodiment, the signals will be specifically described below with reference to the target light-emitting clock signal period. The target light-emitting clock signal period is a period of a first light-emitting clock signal provided by the first light-emitting clock signal line ECK1, a second light-emitting clock signal provided by the second light-emitting clock signal line ECK2, and a third light-emitting clock signal provided by the third light-emitting clock signal line ECK3, which will be hereinafter abbreviated as ECK period.

The phases of the first light-emitting clock signal, the second light-emitting clock signal and the third light-emitting clock signal provided by each of the ECK1, the ECK2 and the ECK3 are sequentially delayed by 1/3 ECK periods, the width/duration of the disable level of the signal input from the input end of the shift register 1 is 2/3 ECK periods, the periods of the scan clock signals provided by the SCK1 and the SCK2 are 2/3 ECK periods, and the phase difference between the scan clock signals provided by the SCK1 and the SCK2 is 1/3 ECK periods.

In this embodiment, by performing a matching design on the corresponding time sequence on the cascade multiplexing structure in the gate driving circuit 1, the cascade multiplexing structure can be more reasonably implemented, so that the number of frame devices can be reduced to a great extent, and the frame size of the display screen can be further reduced.

Referring to fig. 13, fig. 13 is a timing diagram of a gate driving circuit in a second target mode according to an embodiment of the present application. In some more specific embodiments, in order to facilitate uniform control of the output of the scan clock signals of the multi-row shift register in the gate driving circuit during practical application, the shift register 1 may further include a first light-emitting clock signal terminal and a second light-emitting clock signal terminal. As shown in fig. 13, in the second target mode, the input terminal of the shift register 1 inputs the trigger signal, and the target light-emitting clock signal provided by the target light-emitting clock signal terminal has at least two enable levels in the stage of the non-enable level of the trigger signal, the switch module 102 is always turned off, and the scan clock signal is not output by the scan signal output module 101. The target light-emitting clock signal end is a first light-emitting clock signal end or a second light-emitting clock signal end.

In some more specific embodiments, in contrast, in the first target mode, the input terminal of the shift register 1 inputs the trigger signal, and the target light-emitting clock signal provided by the target light-emitting clock signal terminal contains an enable level in a phase of a non-enable level of the trigger signal.

When the gate driving circuit 1 is in the second target mode, the target light emitting clock signal provided by the target light emitting clock signal terminal has at least two enable levels, and the switch module 102 is always cut off, so that the scan signal output module 101 is always unable to receive the conduction level of the first node N1 for conduction in the stage of outputting the non-enable level at the first output terminal EM of the shift register 1, and is unable to transmit the scan clock signal provided by the first scan clock signal terminal sck to the second output terminal SN of the shift register 1, and the scan signal output module 101 does not output the scan clock signal in this stage.

Specifically, when the gate driving circuit 1 is in the second target mode, the target light-emitting clock signal provided by the target light-emitting clock signal terminal contains at least two enable levels. In this way, at least one of the output of the first output terminal EM < N > of the N-th shift register 1 is always the disable level/cut-off level between the first output terminal EM < N-2> of the N-2-th shift register 1 and the first output terminal EM < n+1> of the n+1-th shift register 1 in the stage where the disable level is output from the first output terminal EM < N >. In this case, since the first control signal terminal G1< N > and the second control signal terminal G2< N > connected to the nth stage shift register 1 cannot receive the on level at the same time, the switch module 102 is always turned off in this stage, so that the scan signal output module 101 cannot always receive the on level of the first node N1 through the on switch module 102 for conducting, and thus cannot transmit the scan clock signal provided by the first scan clock signal terminal sck to the second output terminal SN of the shift register 1, and finally the scan signal output module 101 does not output the scan clock signal in this stage.

In the present embodiment, when the respective clock signals in the second target mode are identical to the respective clock signals in the first target mode, the full-line black insertion control of the multi-line shift register 1 in the gate driving circuit 10 can be realized by changing the length of the disable level of the trigger signal input at the output terminal of the first stage shift register 1 (controlling at least two enable levels of any ECK of the EIN disable stage across the current line shift register).

Specifically, fig. 14 is a schematic diagram of simulated output waveforms of the gate driving circuit in the first target mode according to the embodiment of the present application, with reference to the specific illustration. In fig. 14, waveforms of the first output terminals EM of the shift registers of consecutive 3 rows and waveforms of the second output terminals SN of the shift register 1 of consecutive 3 rows in the first target mode are shown.

As can be seen from fig. 14, when the gate driving circuit is in the first target mode, each row shift register simultaneously outputs the SN enable level (low level in fig. 14) at least part of the period in which each row shift register 1 outputs the EM disable level (high level in fig. 14).

Fig. 15 is a schematic diagram of simulated output waveforms of the gate driving circuit in the second target mode according to the embodiment of the present application. In fig. 15, waveforms of the first output terminal EM of the shift register 1 of consecutive 3 stages and waveforms of the second output terminal SN of the shift register 1 of consecutive 3 stages in the second target mode are shown, the output of the second output terminal SN of the shift register 1 not following the output of the first output terminal EM of the shift register 1.

As can be seen from fig. 15, when the gate driving circuit is in the second target mode, each row shift register does not output the SN enable level at least in part of the period in which each row shift register outputs the EM disable level (high level in fig. 15).

Referring to fig. 16, fig. 16 is a schematic structural diagram of a shift register according to another embodiment of the present application. In some more specific embodiments, in order to further implement the effective output of the scan clock signal by the scan signal output module 101, the shift register 1 may optionally further include a bootstrap module 104. The first end of the bootstrap module 104 is electrically connected to the second end of the scan signal output module 101, and the second end of the bootstrap module 104 is electrically connected to the control end of the scan signal output module 101.

In some more specific embodiments, the bootstrap module 104 may include a bootstrap capacitor, where a first pole of the bootstrap capacitor is electrically connected to the second terminal of the scan signal output module 101, and a second pole of the bootstrap capacitor is electrically connected to the control terminal of the scan signal output module 101.

In a specific operation, when the scan signal output module 101 is turned on in response to the on level (low level in this example) transmitted by the first node N1, the scan signal output module 101 transmits the scan clock signal (low level in this example) provided by the first scan clock signal terminal sck to the second output terminal SN of the shift register 1, and the second output terminal SN of the shift register 1 is low in potential jump, for example. At this time, the bootstrap module 104 further pulls down the potential of the control end of the scan signal output module 101 by using its own coupling function, so that sufficient conduction of the scan signal output module 101 can be ensured as much as possible, which is beneficial to maintaining the normal output of the scan clock signal.

Referring to fig. 17, fig. 17 is a schematic diagram of a shift register according to another embodiment of the present application. In some more specific embodiments, the shift register 1 may optionally further include a second light emission control signal output module 105. The control end of the second light emission control signal output module 105 is electrically connected to the second node N2, the first end of the second light emission control signal output module 105 is electrically connected to the second level voltage end VGL, and the second end of the second light emission control signal output module 105 is electrically connected to the first output end EM of the shift register 1.

Specifically, the second light emission control signal output module 105 may be turned on under the control of the turn-on level provided by the second node N2, and transmit the second level voltage signal provided by the second level voltage terminal VGL to the first output terminal EM of the shift register 1.

Alternatively, the first level voltage signal provided by the first level voltage terminal VGH may be a high level. Alternatively, the second level voltage signal provided by the second level voltage terminal VGL may be a low level.

Referring to fig. 18, fig. 18 is a schematic diagram of a shift register according to another embodiment of the present application. In some more specific embodiments, the shift register 1 optionally further comprises a light emission control signal shift control module 106. The light-emitting control signal shift control module 106 includes a first light-emitting clock signal end eck1, a second light-emitting clock signal end eck2, and an input end EIN of the shift register 1, a first output end of the light-emitting control signal shift control module 106 is electrically connected with a control end of the first light-emitting control signal output module 103, and a second output end of the light-emitting control signal shift control module 106 is electrically connected with a control end of the second light-emitting control signal output module 105; the light emission control signal shift control module 106 is configured to output an on level or an off level from a first output terminal of the light emission control signal shift control module 106 and output the on level or the off level from a second output terminal of the light emission control signal shift control module 106 under control of the first light emission clock signal terminal eck1, the second light emission clock signal terminal eck2, and the shift register input terminal EIN.

In order to facilitate understanding of the shift register 1 in the gate driving circuit 10 provided in the present application, the following description is made in connection with some specific application embodiments.

Referring to fig. 19, fig. 19 is a schematic structural diagram of a gate driving circuit according to another embodiment of the present application. As shown in fig. 19, in the gate driving circuit 10 according to some embodiments of the present application, optionally, the scan signal output module 101 may be specifically a sixteenth transistor T16, the switch module may be specifically configured by a fourteenth transistor T14 and a fifteenth transistor T15, the first light emitting control signal output module 103 may be specifically a ninth transistor T9, the second light emitting control signal output module 105 may be specifically a tenth transistor T10, and the bootstrap module 104 may be specifically a bootstrap capacitor C4. And, the transistors referred to in this embodiment are P-type driving transistors. It should be noted that, in other embodiments, the channel types of the above transistors may be flexibly adjusted according to practical situations, which is not strictly limited in the present application.

The control terminal of the ninth transistor T9 is electrically connected to the first node N1, the first terminal of the ninth transistor T9 is electrically connected to the first level voltage terminal VGH, and the second terminal of the ninth transistor T9 is electrically connected to the first output terminal EM of the shift register 1. The control terminal of the fourteenth transistor T14 is electrically connected to the first control signal terminal G1, the first terminal of the fourteenth transistor T14 is electrically connected to the first node N1, and the second terminal of the fourteenth transistor T14 is electrically connected to the first terminal of the fifteenth transistor T15. The control terminal of the fifteenth transistor T15 is electrically connected to the second control signal terminal G2, and the second terminal of the fifteenth transistor T15 is electrically connected to the second output terminal SN of the shift register 1. A first terminal of the sixteenth transistor T16 is electrically connected to the first scan clock signal terminal sck, and a second terminal of the sixteenth transistor T16 is electrically connected to the second output terminal SN of the shift register 1. The first pole of the bootstrap capacitor C4 is electrically connected to the second terminal of the sixteenth transistor T16, and the second pole of the bootstrap capacitor C4 is electrically connected to the control terminal of the sixteenth transistor T16. The control terminal of the tenth transistor T10 is electrically connected to the second node N2, the first terminal of the tenth transistor T10 is electrically connected to the second level voltage terminal VGL, and the second terminal of the tenth transistor T10 is electrically connected to the first output terminal EM of the shift register 1.

In particular, when the gate driving circuit is in the first target mode, in the shift register 1, during at least a portion of the stage when the first node N1 is at the on level, the ninth transistor T9 is turned on under the control of the on level provided by the first node N1, and transmits the first level voltage signal provided by the first level voltage terminal VGH to the first output terminal EM of the shift register 1.

The fourteenth transistor T14 is turned on in response to the on level provided by the first control signal terminal G1, and transmits the node potential of the first node N1 to the first terminal of the fifteenth transistor T15. The control terminal of the fifteenth transistor T15 may be configured to transmit the on level of the first terminal of the fifteenth transistor T15 to the second output terminal SN of the shift register 1 in response to the on level provided by the second control signal terminal G2. At this time, the sixteenth transistor T16 transmits the scan clock signal provided from the first scan clock signal terminal sck to the second output terminal SN of the shift register 1 in response to the on level provided from the first node N1.

At this stage, the second node N2 is turned off, and the tenth transistor is turned off in response to the off level provided by the second node N2, so that the second level voltage signal provided by the second level voltage terminal VGL is not transmitted to the first output terminal EM of the shift register 1.

It should be noted that, in addition to the above-listed transistors, the gate driving circuit 10 may further include other transistors, which together form a plurality of types of gate driving circuits, which are not particularly limited in this application.

Referring to fig. 20, fig. 20 is a schematic structural diagram of a gate driving circuit according to another embodiment of the present application. As shown in fig. 20, according to some embodiments of the present application, optionally, a gate signal generating circuit of a front stage EM output pipe in the EM circuit is added to fig. 20 on the basis of fig. 19, and the gate signal generating circuit and the output pipes T9 and T10 of a rear stage together form an existing shift register of 13T3C, where specific device components and connection relationships between devices may be as shown in fig. 20, and the light emission control signal shift control module 106 specifically includes: the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the first capacitor C1, the second capacitor 2, and the third capacitor C3. In this embodiment, the first transistor T1 to the sixteenth transistor may be P-type transistors. It should be understood that in other possible embodiments, the transistors may be of other channel types, and the corresponding timing and the like may be adaptively adjusted when the channel types of some transistors are changed, which is not strictly limited in this application.

The control end of the first transistor T1 is electrically connected to the first light-emitting clock signal end eck1, the first end of the first transistor is electrically connected to the input end EIN of the shift register 1, and the second end of the first transistor T1 is electrically connected to the third node N3. The control terminal of the second transistor T2 is electrically connected to the third node N3, the first terminal of the second transistor T2 is electrically connected to the second terminal of the third transistor T3, and the second terminal of the second transistor T2 is electrically connected to the first light-emitting clock signal terminal eck 1. The control terminal of the third transistor T3 is electrically connected to the first light-emitting clock signal terminal eck1, and the first terminal of the third transistor T3 is electrically connected to the second level voltage terminal VGL. The control terminal of the fourth transistor T4 is electrically connected to the second terminal of the twelfth transistor T12, the first terminal of the fourth transistor T4 is electrically connected to the first level voltage terminal VGH, and the second terminal of the fourth transistor T4 is electrically connected to the first terminal of the fifth transistor T5. The control terminal of the fifth transistor T5 is electrically connected to the second light-emitting clock signal terminal eck2, and the second terminal of the fifth transistor T5 is electrically connected to the third node N3. The control terminal of the sixth transistor T6 is electrically connected to the third node N3, the first terminal of the sixth transistor is electrically connected to the first node N1, and the second terminal of the sixth transistor T6 is electrically connected to the first level voltage terminal VGH. The control terminal of the seventh transistor T7 is electrically connected to the second light-emitting clock signal terminal eck2, the first terminal of the seventh transistor T7 is electrically connected to the second pole of the first capacitor C1, and the second terminal of the seventh transistor T7 is electrically connected to the first node N1. The control terminal of the eighth transistor T8 is electrically connected to the first pole of the first capacitor C1, the first terminal of the eighth transistor T8 is electrically connected to the second light-emitting clock signal terminal eck2, and the second terminal of the eighth transistor T8 is electrically connected to the second pole of the first capacitor C1. The control terminal of the eleventh transistor T11 is electrically connected to the second level voltage terminal VGL, the first terminal of the eleventh transistor T11 is electrically connected to the third node N3, and the second terminal of the eleventh transistor T11 is electrically connected to the second node N2. The control terminal of the twelfth transistor T12 is electrically connected to the second level voltage terminal VGL, and the first terminal of the twelfth transistor T12 is electrically connected to the first pole of the first capacitor C1.

The control terminal of the thirteenth transistor T13 and the control terminal of the twelfth transistor T12 are electrically connected to the second level voltage terminal VGL, the first terminal of the thirteenth transistor T13 is electrically connected to the second terminal of the third transistor T3, and the second terminal of the thirteenth transistor T13 is electrically connected to the first terminal of the twelfth transistor T12. The first pole of the second capacitor C2 is electrically connected to the second node N2, and the second pole of the second capacitor C2 is electrically connected to the second light-emitting clock signal end eck 2. The first pole of the third capacitor C3 is electrically connected to the first level voltage terminal VGH, and the second pole of the third capacitor C3 is electrically connected to the first node N1.

Based on the gate driving circuit provided by any one of the foregoing embodiments, correspondingly, the embodiment of the present application further provides a driving method of the gate driving circuit, where the driving method of the gate driving circuit is applied to the gate driving circuit provided by any one of the foregoing embodiments of the present application.

Next, referring to fig. 21, fig. 21 is a schematic flow chart of a driving method of a gate driving circuit according to an embodiment of the present application.

As shown in fig. 21, the driving method of the gate driving circuit includes:

s2110, in a first target mode, at least part of the stage that the control end of the first light emitting control signal output module is at a conducting level, the control switch module is conducted, so that the scanning signal output module responds to the conducting level of the control end of the first light emitting control signal output module, and the enabling level of the scanning clock signal provided by the first scanning clock signal end is transmitted to the second output end of the shift register.

In particular, in the first target mode, the switch module is controlled to conduct at least part of the stage that the control end of the first light-emitting control signal output module is at the conducting level. In this way, the conduction level of the control end of the first light-emitting control signal output module can be transmitted to the control end of the scanning signal output module through the conduction switch module.

In this way, the scan signal output module can be turned on in response to the turn-on level provided by the control terminal of the first light emitting control signal output module. The enabling level of the scanning clock signal provided by the first scanning clock signal end is finally transmitted to the second output end of the shift register through the conducting scanning signal output module, so that the output of the enabling level of the scanning clock signal in the stage that the control end of the first light-emitting control signal output module is at least at the conducting level is realized.

According to the driving method of the grid driving circuit, the characteristic that the scanning driving signal is effective when the non-enabling level is output by the light-emitting control signal is utilized, the grid signal of the non-enabling level output tube in the shift register is used as the grid of the scanning driving signal output tube, so that the existing Scan circuit and the existing EM circuit are combined, the Scan does not need to generate the potential of the grid of the control output tube, the number of devices is greatly reduced, and the effect of reducing the frame width of the display screen can be fully achieved.

Optionally, the driving method of the gate driving circuit further includes: in the second target mode, the input end of the shift register 1 inputs a trigger signal, and the target light-emitting clock signal provided by the target light-emitting clock signal end at least contains two enable levels in the stage of non-enable level of the trigger signal, the switch module 102 is always cut off, and the scan signal output module 101 does not output the scan clock signal.

Based on the gate driving circuit provided in any of the above embodiments, correspondingly, the present application further provides a display panel, including the gate driving circuit 10 provided in the present application. Referring to fig. 22, fig. 22 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. As shown in fig. 22, the display panel 100 provided in the embodiment of the present application may include the gate driving circuit 10 of any of the embodiments described above. The display panel shown in fig. 22 may be an Organic Light-Emitting Diode (OLED) display panel.

Those skilled in the art will appreciate that in other implementations of the present application, the display panel may also be a Micro light emitting diode (Micro LED) display panel, a quantum dot display panel, or the like.

The display panel provided in the embodiment of the present application has the beneficial effects of the gate driving circuit 10 provided in the embodiment of the present application, and the specific description of the gate driving circuit 10 in the above embodiments may be referred to specifically, and the description of the embodiment is omitted here.

Based on the display panel provided by the embodiment, correspondingly, the application also provides a display device comprising the display panel provided by the application. Referring to fig. 23, fig. 23 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. Fig. 23 provides a display device 1000 including a display panel 100 provided in any of the embodiments described above. The embodiment of fig. 23 is described with respect to the display device 1000 by taking a mobile phone as an example, and it is to be understood that the display device provided in the embodiment of the present application may be a wearable product, a computer, a television, a vehicle-mounted display device, or other display devices having a display function, which is not particularly limited in this application. The display device provided in the embodiment of the present application has the beneficial effects of the display panel 100 provided in the embodiment of the present application, and the specific description of the display panel 100 in the above embodiments may be referred to specifically, and the description of the embodiment is omitted herein.

It should be understood that the specific structures of the circuits and the cross-sectional structures of the display panels provided in the drawings according to the embodiments of the present application are only examples and are not intended to limit the present application. In addition, the above embodiments provided herein may be combined with each other without contradiction.

It should be understood that, in the present specification, each embodiment is described in an incremental manner, and the same or similar parts between the embodiments are all referred to each other, and each embodiment is mainly described in a different point from other embodiments. These embodiments are not exhaustive of all details, nor are they intended to limit the application to the precise embodiments disclosed herein. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. This application is to be limited only by the claims and the full scope and equivalents thereof.

Those skilled in the art will appreciate that the above-described embodiments are exemplary and not limiting. The different technical features presented in the different embodiments may be combined to advantage. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in view of the drawings, the description, and the claims. In the claims, the term "comprising" does not exclude other structures; the amounts refer to "a" and do not exclude a plurality; the terms "first," "second," and the like, are used for designating a name and not for indicating any particular order. Any reference signs in the claims shall not be construed as limiting the scope. The presence of certain features in different dependent claims does not imply that these features are not useful in combination.

Claims

1. The grid driving circuit is characterized by comprising a plurality of cascaded shift registers, wherein each shift register comprises a scanning signal output module, a switch module and a first light-emitting control signal output module;

the first end of the first light-emitting control signal output module is electrically connected with a first level voltage end, the second end of the first light-emitting control signal output module is electrically connected with the first output end of the shift register, and the first light-emitting control signal output module is used for responding to the conduction level of the control end of the first light-emitting control signal output module and transmitting a first level voltage signal provided by the first level voltage end to the first output end of the shift register;

the first end of the switch module is electrically connected with the control end of the first light-emitting control signal output module, and the second end of the switch module is electrically connected with the control end of the scanning signal output module;

in the first target mode, at least part of the stage that the control end of the first light-emitting control signal output module is at the conducting level, the switch module is conducted, and the scanning signal output module responds to the conducting level of the control end of the first light-emitting control signal output module and transmits the enabling level of the scanning clock signal provided by the first scanning clock signal end to the second output end of the shift register.

2. The gate driving circuit according to claim 1, wherein the switching module comprises a first control signal terminal and a second control signal terminal, and the switching module is specifically configured to transmit the conduction level of the control terminal of the first light-emitting control signal output module to the control terminal of the scanning signal output module in response to conduction of the conduction level provided by the first control signal terminal and the conduction level provided by the second control signal terminal during at least a part of the period when the control terminal of the first light-emitting control signal output module is the conduction level;

preferably, the switching module includes a first switching unit and a second switching unit;

the control end of the first switch unit is electrically connected with the first control signal end, the first end of the first switch unit is electrically connected with the control end of the first light-emitting control signal output module, the second end of the first switch unit is electrically connected with the first end of the second switch unit, and the first switch unit is used for responding to the conduction level provided by the first control signal end and transmitting the potential of the control end of the first light-emitting control signal output module to the first end of the second switch unit;

The control end of the second switch unit is electrically connected with the second control signal end, the second end of the second switch unit is electrically connected with the second output end of the shift register, and the second switch unit is used for responding to the conduction level provided by the second control signal end and transmitting the level of the first end of the second switch unit to the second output end of the shift register.

3. The gate driving circuit according to claim 2, wherein,

one of the first control signal end and the second control signal end of any N-th shift register in the grid driving circuit is electrically connected with the first output end of the N-2 th shift register, the other is electrically connected with the first output end of the n+1-th shift register, and N is a positive integer greater than 2; preferably, the start time of the non-enable level of the light-emitting control signal provided by the first output end of the nth stage shift register is separated from the start time of the non-enable level of the light-emitting control signal provided by the first output end of the n+1th stage shift register by a first time period, the duration of the enabling level of the first scan clock signal provided by the first scan clock signal end is a second time period, and the first time period is greater than or equal to the second time period;

Preferably, the first duration is one half of a duration of a non-enable level of the light emission control signal provided by the first output terminal of the first stage shift register;

preferably, in the first target mode, the end time of the non-enable level of the light-emitting control signal provided by the first output terminal of the N-2 th stage shift register is before the start time of the non-enable level of the light-emitting control signal provided by the first output terminal of the n+1 th stage shift register, and the interval time is longer than or equal to the duration of the enable level of the first scan clock signal provided by the first scan clock signal terminal; at least part of the stage between the end time of the non-enabling level of the light-emitting control signal provided by the first output end of the N-2 level shift register and the start time of the non-enabling level of the light-emitting control signal provided by the first output end of the N+1th level shift register, the light-emitting control signal provided by the first output end of the N level shift register is the non-enabling level, the control end of the first light-emitting control signal output module in the N level shift register is the conducting level, the switch module is conducted, and the scanning signal output module responds to the conducting level of the control end of the first light-emitting control signal output module and transmits the enabling level of the scanning clock signal provided by the first scanning clock signal end to the second output end of the shift register;

Preferably, in the second target mode, a phase of a non-enable level of the light emission control signal provided at the first output terminal of the N-2 th stage shift register overlaps with a phase of a non-enable level of the light emission control signal provided at the first output terminal of the n+1 th stage shift register, the switching module in the N-th stage shift register is always turned off, and the scan signal output module does not output the scan clock signal provided at the first scan clock signal terminal;

in a display frame, the first target mode is located before the second target mode;

preferably, the duration of the non-enabling level of the trigger signal input at the input end of the shift register in the second target mode is longer than the duration of the non-enabling level of the trigger signal input at the input end of the shift register in the first target mode;

preferably, the first level voltage signal provided by the first level voltage terminal is transmitted to the first output terminal of the shift register as a non-enable level of the light emission control signal.

4. The gate driving circuit according to claim 1, wherein one of the first scan clock signal terminals of the shift registers of adjacent two stages is electrically connected to the first scan clock signal line, and the other is electrically connected to the second scan clock signal line;

The phase of the scanning clock signal output by the first scanning clock signal line and the phase of the scanning clock signal provided by the second scanning clock signal line differ by a first time length which is one half of the time length of a non-enabling level of a light-emitting control signal provided by a first output end of the first-stage shift register.

5. The gate drive circuit of claim 1, wherein the shift register further comprises a first light-emitting clock signal terminal and a second light-emitting clock signal terminal;

the first light-emitting clock signal end of the 3M+1 stage shift register is electrically connected with the first light-emitting clock signal line, the second light-emitting clock signal end of the 3M+1 stage shift register is electrically connected with the second light-emitting clock signal line, and M is an integer greater than or equal to 0;

the first light-emitting clock signal end of the 3M+2-stage shift register is electrically connected with the second light-emitting clock signal line, and the second light-emitting clock signal end of the 3M+2-stage shift register is electrically connected with the third light-emitting clock signal line;

the first light-emitting clock signal end of the 3M+3 stage shift register is electrically connected with the third light-emitting clock signal line, and the second light-emitting clock signal end of the 3M+3 stage shift register is electrically connected with the first light-emitting clock signal line;

Preferably, the periods of the first light-emitting clock signal provided by the first light-emitting clock signal line, the second light-emitting clock signal provided by the second light-emitting clock signal line and the third light-emitting clock signal provided by the third light-emitting clock signal line are all target light-emitting clock signal periods, and the phases among the first light-emitting clock signal, the second light-emitting clock signal and the third light-emitting clock signal are sequentially delayed by 1/3 of the target light-emitting clock signal periods.

6. The gate driving circuit according to claim 1, wherein,

the phase difference between a signal input by the input end of the shift register and a light-emitting control signal output by the first output end of the shift register is a first duration which is one half of the duration of a non-enabling level of the light-emitting control signal provided by the first output end of the first-stage shift register;

preferably, the input end of the 1 st stage shift register is electrically connected with the trigger signal end, the input end of the K stage shift register is electrically connected with the first output end of the K-1 st stage shift register, and K is a positive integer greater than or equal to 2.

7. The gate drive circuit of claim 1, wherein the shift register further comprises a first light-emitting clock signal terminal and a second light-emitting clock signal terminal;

In a second target mode, a trigger signal is input to the input end of the shift register, a target light-emitting clock signal provided by a target light-emitting clock signal end at least contains two enabling levels in a non-enabling level stage of the trigger signal, the switch module is always cut off, and the scanning signal output module does not output the scanning clock signal;

the target light-emitting clock signal end is the first light-emitting clock signal end or the second light-emitting clock signal end;

preferably, in the first target mode, a trigger signal is input to an input terminal of the shift register, and the target light-emitting clock signal provided by the target light-emitting clock signal terminal contains an enable level in a stage of a non-enable level of the trigger signal.

8. The gate drive circuit of claim 1, wherein the shift register further comprises a bootstrap module;

the first end of the bootstrap module is electrically connected with the second end of the scanning signal output module, and the second end of the bootstrap module is electrically connected with the control end of the scanning signal output module;

preferably, the bootstrap module comprises a bootstrap capacitor, a first pole of the bootstrap capacitor is electrically connected with the second end of the scanning signal output module, and a second pole of the bootstrap capacitor is electrically connected with the control end of the scanning signal output module;

Preferably, the shift register further includes a second light emission control signal output module;

the first end of the second light-emitting control signal output module is electrically connected with a second level voltage end, the second end of the second light-emitting control signal output module is electrically connected with the first output end of the shift register, and the second light-emitting control signal output module is used for responding to the conduction level of the control end of the second light-emitting control signal output module and transmitting a second level voltage signal provided by the second level voltage end to the first output end of the shift register;

preferably, the shift register further includes a light emission control signal shift control module, where the light emission control signal shift control module includes a first light emission clock signal end, a second light emission clock signal end, and an input end of the shift register, a first output end of the light emission control signal shift control module is electrically connected to a control end of the first light emission control signal output module, and a second output end of the light emission control signal shift control module is electrically connected to a control end of the second light emission control signal output module;

the light-emitting control signal shift control module is used for outputting an on level or an off level by a first output end of the light-emitting control signal shift control module and outputting the on level or the off level by a second output end of the light-emitting control signal shift control module under the control of the first light-emitting clock signal end, the second light-emitting clock signal end and the shift register input end.

9. A driving method of a gate driving circuit, characterized by being applied to the gate driving circuit according to any one of claims 1 to 8, the method comprising:

10. A display panel comprising the gate driving circuit according to any one of claims 1 to 8.