CN117095727A

CN117095727A - Shifting register, grid driving circuit, display panel and display device

Info

Publication number: CN117095727A
Application number: CN202311055079.3A
Authority: CN
Inventors: 米磊; 盖翠丽; 高利朋; 丁亚楠
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd; Hefei Visionox Technology Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd; Hefei Visionox Technology Co Ltd
Priority date: 2023-08-21
Filing date: 2023-08-21
Publication date: 2023-11-21

Abstract

The embodiment of the application provides a shift register, a grid driving circuit, a display panel and a display device, and relates to the technical field of display panels. In the shift register, an input module is used for transmitting an initial input signal to a first node under the control of an input end of the shift register; the first control module is used for adjusting the potential of the third node under the control of the first clock signal end and the input end of the shift register; the second control module is used for adjusting the potential of the second node under the control of the third stage and the second clock signal end; the third control module is used for adjusting the potential of the first node under the control of the output end of the post M-stage shift register; the first output module is used for transmitting the first level voltage to the output end of the shift register under the control of the third node; the second output module is used for transmitting a second clock signal to the output end of the shift register under the control of the first node. According to the embodiment of the application, the diversified requirements of the pixel circuit on the scanning pulse waveform can be fully met.

Description

Shifting register, grid driving circuit, display panel and display device

Technical Field

The application belongs to the technical field of display, and particularly relates to a shift register, a grid driving circuit, a display panel and a display device.

Background

With the rapid development of display technology, a display screen is used as a window for interaction between a digital information display carrier and a human-computer system, and is becoming an important port for people to receive visual information, so that the living and economic and social development of people are continuously affected. It is worth mentioning that with the progress of technology and the continuous improvement of information interaction demands of people, commercial displays are being integrated into life at unprecedented speed. Such as applications of various forms of commercial display screens in functions of environment fusion, virtual Reality (VR), enhanced display (Augmented Reality, AR), holographic projection and the like. Under the current and abundant display market demands, various requirements, such as ultra-high frequency, high-low frequency, etc., are put on the display aspect of an Organic Light-Emitting Diode (OLED) display panel, and thus, the screen circuit is required to be diversified.

However, in the prior art, the GIP (Gate in Panel) circuit has relatively single function, and the output scanning pulse waveform is often relatively fixed, so that the requirement of the pixel circuit for diversification of the output scanning signals cannot be met flexibly.

Disclosure of Invention

The embodiment of the application provides a shift register, a grid driving circuit, a display panel and a display device, which can flexibly meet the diversified requirements of a pixel circuit on the scanning pulse waveform output by the pixel circuit.

In a first aspect, an embodiment of the present application provides a shift register, including: the device comprises an input module, a first control module, a second control module, a third control module, a first output module and a second output module;

the input module is used for transmitting an initial input signal provided by the input end of the shift register to the first node under the control of the input end of the shift register;

the first control module is used for adjusting the potential of the third node under the control of the first clock signal end and the input end of the shift register;

the second control module is used for adjusting the potential of the first node under the control of the third node and the second clock signal end;

the third control module is used for adjusting the potential of the first node under the control of the output end of the post M-stage shift register, wherein M is a positive integer;

the first output module is connected with the first level voltage signal end and the shift register output end and is used for transmitting the first level voltage provided by the first level voltage signal end to the shift register output end under the control of the third node;

The second output module is connected with the second clock signal end and the shift register output end and is used for transmitting the second clock signal provided by the second clock signal end to the shift register output end under the control of the first node.

In a possible implementation manner of the first aspect, in order to reasonably realize overlapping or non-overlapping control of the scanning pulse waveforms output by the adjacent stage shift register, so as to more effectively meet the diversified requirements of the pixel circuit on the scanning pulse waveforms, further, the enabling level pulse width of the first clock signal and the enabling level pulse width of the second clock signal meet a first preset condition, and the adjacent stage shift register outputs non-overlapping scanning pulse waveforms; the first clock signal is provided by a first clock signal terminal; the enabling level pulse width of the first clock signal and the enabling level pulse width of the second clock signal meet a second preset condition, and the adjacent stage shift registers output overlapped scanning pulse waveforms. In this embodiment, by controlling and adjusting the enable level pulse width of the first clock signal and the enable level pulse width of the second clock signal, when the enable level pulse width of the first clock signal and the enable level pulse width of the second clock signal meet different conditions, adjacent shift registers cooperate to output scan pulse waveforms with or without overlapping enable level stages.

In a possible implementation manner of the first aspect, further, in order to accurately realize control of overlapping or non-overlapping of the scanning pulse waveforms output by the shift registers of adjacent stages, so as to more reasonably meet the diversified requirements of the pixel circuit on the scanning pulse waveforms, an enabling level start time of the first clock signal and an enabling level start time of the second clock signal are separated by 1/2 clock signal period; when the enabling level pulse width of the first clock signal and the enabling level pulse width of the second clock signal are smaller than 1/4 clock signal period or equal to 1/4 clock signal period, the adjacent stage shift registers output non-overlapping scanning pulse waveforms; the adjacent stage shift registers output overlapping scan pulse waveforms when the enable level pulse widths of the first clock signal and the second clock signal are equal to 1/2 clock signal periods, or greater than 1/4 clock signal periods and less than 1/2 clock signal periods. Therefore, the control of overlapping or non-overlapping of the scanning pulse waveforms output by the adjacent stage shift register can be more accurately realized by adjusting the range of the enabling level pulse widths of the first clock signal and the second clock signal, so that the diversified requirements of the pixel circuit on the scanning pulse waveforms can be more reasonably met.

In one possible implementation manner of the first aspect, when the pulse widths of the enabling level of the first clock signal and the enabling level of the second clock signal are 1/4 clock signal period, the adjacent stage shift registers output non-overlapping scanning pulse waveforms; when the pulse width of the enabling level of the first clock signal and the second clock signal is 1/2 clock signal period, the adjacent stage shift register outputs overlapped scanning pulse waveforms.

In a possible implementation manner of the first aspect, the enable level pulse widths of the first clock signal and the second clock signal are the same, and the clock signal periods of the first clock signal and the second clock signal are the same.

In a possible implementation manner of the first aspect, 1/4 clock signal period is equal to a scanning time of one row of pixel circuits.

In a possible implementation manner of the first aspect, the enable level pulse width of the initial input signal provided at the input end of the shift register is the same as the enable level pulse width of the second clock signal, and the enable level phase of the initial input signal provided at the input end of the shift register is advanced by 1/4 clock signal period compared with one enable level phase of the second clock signal.

In a possible implementation manner of the first aspect, the control end and the first end of the input module are electrically connected to the output end of the shift register, and the second end of the input module is electrically connected to the first node; the first control module is electrically connected with the first control end and the first clock signal end, the second control end of the first control module is electrically connected with the input end of the shift register, the first input end of the first control module is electrically connected with the second level voltage signal end, the second input end of the first control module is electrically connected with the first clock signal end, and the output end of the first control module is electrically connected with the third node; the first control end of the second control module is electrically connected with the third node, the second control end of the second control module is electrically connected with the second clock signal end, the first end of the second control module is electrically connected with the first level voltage signal end, and the second end of the second control module is electrically connected with the second node; the control end of the third control module is electrically connected with the output end of the post M-stage shift register, the first end of the third control module is electrically connected with the first level voltage signal end, and the second end of the third control module is electrically connected with the first node; the control end of the first output module is electrically connected with the third node, the first end of the first output module is electrically connected with the first level voltage signal end, and the second end of the first output module is electrically connected with the output end of the shift register; the control end of the second output module is electrically connected with the second node, the first end of the second output module is electrically connected with the output end of the shift register, and the second end of the second output module is electrically connected with the second clock signal end.

In a possible implementation manner of the first aspect, the input module includes a first transistor, the second control module includes a second transistor and a third transistor, the first control module includes a fourth transistor and a fifth transistor, the first output module includes a sixth transistor, the second output module includes a seventh transistor, and the third control module includes an eighth transistor; the control end and the first end of the first transistor are electrically connected with the input end of the shift register, and the second end of the first transistor is electrically connected with the first node; the control end of the second transistor is electrically connected with the second clock signal end, the first end of the second transistor is electrically connected with the second end of the third transistor, and the second end of the second transistor is electrically connected with the first node; the control end of the third transistor is electrically connected with the third node, and the first end of the third transistor is electrically connected with the first level voltage signal end; the control end of the fourth transistor is electrically connected with the input end of the shift register, the first end of the fourth transistor is electrically connected with the third node, and the second end of the fourth transistor is electrically connected with the second clock signal end; the control end of the fifth transistor is electrically connected with the second clock signal end, the first end of the fifth transistor is electrically connected with the second level voltage signal end, and the second end of the fifth transistor is electrically connected with the third node; the control end of the sixth transistor is electrically connected with the third node, the first end of the sixth transistor is electrically connected with the first level voltage signal end, and the second end of the sixth transistor is electrically connected with the output end of the shift register; the control end of the seventh transistor is electrically connected with the second node, the first end of the seventh transistor is electrically connected with the output end of the shift register, and the second end of the seventh transistor is electrically connected with the second clock signal end; the control end of the eighth transistor is electrically connected with the output end of the post M-stage shift register, the first end of the eighth transistor is electrically connected with the first node, and the second end of the eighth transistor is electrically connected with the first level voltage signal end.

In a possible implementation manner of the first aspect, the value of M is 2.

In a possible implementation manner of the first aspect, the shift register further includes a first storage module, a second storage module, and a first switch module; the first end of the first storage module is electrically connected with the first level voltage signal end, and the second end of the first storage module is electrically connected with the third node and is used for maintaining the node potential stability of the third node; the first end of the second storage module is electrically connected with the output end of the shift register, and the second end of the second storage module is electrically connected with the second node and is used for bootstrapping and maintaining the node potential of the second node; the control end of the first switch module is electrically connected with the second level voltage signal end, the first end of the first switch module is electrically connected with the first node, and the second end of the first switch module is electrically connected with the second node.

In a possible implementation manner of the first aspect, the first memory module includes a first capacitor, the second memory module includes a second capacitor, and the first switch module includes a ninth transistor; the first electrode of the first capacitor is electrically connected with the first level voltage signal end, and the second electrode of the first capacitor is electrically connected with the third node; the first end of the second capacitor is electrically connected with the output end of the shift register, and the second end of the second capacitor is electrically connected with the second node; the control terminal of the ninth transistor is electrically connected to the second level voltage signal terminal, the first terminal of the ninth transistor is electrically connected to the first node, and the second terminal of the ninth transistor is electrically connected to the second node.

In a possible implementation manner of the first aspect, the first level voltage is a non-enabling level, and the second level voltage is an enabling level; if the shift registers of adjacent stages output overlapped scanning pulse waveforms, in the first stage, the input end of the shift register provides a non-enabling level, the first clock signal end provides an enabling level, and the second clock signal end provides a non-enabling level; the first control module is conducted, the second level voltage provided by the second level voltage signal end is transmitted to the third node, the first output module is conducted, and the non-enabling level provided by the first level voltage signal end is transmitted to the output end of the shift register; in the second stage, the shift register input terminal provides an enabling level, the first clock signal terminal provides an enabling level, and the second clock signal terminal provides a non-enabling level; the first control module is conducted, and the third node is an enabling level; the first output module responds to the conduction of the enabling level of the third node and transmits the enabling level of the first level voltage signal end to the output end of the shift register; the input module is conducted, and the enabling level provided by the input end of the shift register is transmitted to the first node; the second output module responds to the conduction of the enabling level of the second node and transmits the non-enabling level provided by the second clock signal end to the output end of the shift register; in the third stage, the shift register input terminal provides an enabling level, the first clock signal terminal provides a non-enabling level, and the second clock signal terminal provides an enabling level; the node potential of the second node is lower than the enabling level; the second output module is conducted and transmits the enabling level provided by the second clock signal end to the output end of the shift register; in the fourth stage, the shift register input terminal provides a non-enabling level, the first clock signal terminal provides a non-enabling level, and the second clock signal terminal provides an enabling level; the input module is turned off, and the second node maintains an enabling level; the second output module is conducted and transmits the enabling level provided by the second clock signal end to the output end of the shift register; in the fifth stage, the shift register input terminal provides a non-enabling level, the first clock signal terminal provides an enabling level, and the second clock signal terminal provides a non-enabling level; the first control module is conducted and transmits the second level voltage provided by the second level voltage signal end to the third node; the first output module is conducted and transmits the non-enabling level provided by the first level voltage signal end to the output end of the shift register; in the sixth stage, the shift register output provides a non-enable level; the first control module is turned off, and the third node maintains an enabling level; the first output module is conducted and transmits the non-enabling level provided by the first level voltage signal end to the output end of the shift register; or if the adjacent stage shift registers output non-overlapping scanning pulse waveforms, in the first stage, the input end of the shift register provides a non-enabling level, the first clock signal end provides an enabling level, and the second clock signal end provides a non-enabling level; the first control module is conducted, the second level voltage provided by the second level voltage signal end is transmitted to the third node, the first output module is conducted, and the non-enabling level provided by the first level voltage signal end is transmitted to the output end of the shift register; in the second stage, the shift register input terminal provides an enabling level, the first clock signal terminal provides a non-enabling level, and the second clock signal terminal provides a non-enabling level; the input module is conducted, and the enabling level provided by the input end of the shift register is transmitted to the first node; the second output module responds to the conduction of the enabling level of the second node and transmits the non-enabling level provided by the second clock signal end to the output end of the shift register; in the third stage, the shift register input terminal provides a non-enabling level, the first clock signal terminal provides a non-enabling level, and the second clock signal terminal provides an enabling level; the node potential of the second node is lower than the enabling level; the second output module is conducted and transmits the enabling level provided by the second clock signal end to the output end of the shift register; in the fourth stage, the shift register input terminal provides a non-enabling level, the first clock signal terminal provides a non-enabling level, and the second clock signal terminal provides a non-enabling level; the second node maintains an enable level; the second output module is conducted and transmits the non-enabling level provided by the second clock signal end to the output end of the shift register; in the fifth stage, the shift register input terminal provides a non-enabling level, the first clock signal terminal provides an enabling level, and the second clock signal terminal provides a non-enabling level; the first control module is conducted and transmits the second level voltage provided by the second level voltage signal end to the third node; the first output module is conducted and transmits the non-enabling level provided by the first level voltage signal end to the output end of the shift register; in the sixth stage, the shift register output provides a non-enable level; the first control module is turned off, and the third node maintains an enabling level; the first output module is conducted and transmits the non-enabling level provided by the first level voltage signal end to the output end of the shift register.

Based on the same inventive concept, in a second aspect, an embodiment of the present application provides a gate driving circuit, where the gate driving circuit includes a plurality of shift registers as provided in any of the foregoing embodiments of the first aspect of the present application, and the plurality of shift registers are cascade-connected.

In a possible implementation manner of the second aspect, the first clock signal and the second clock signal in the n+1th stage shift register have a preset phase difference from the first clock signal and the second clock signal in the N stage shift register, and N is a positive integer.

In one possible implementation manner of the second aspect, the gate driving circuit includes a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line; the clock signals provided by the first clock signal line, the second clock signal line, the third clock signal line and the fourth clock signal line are sequentially separated by 1/4 clock signal period; the first clock signal end in the N-th shift register is electrically connected with the second clock signal wire, and the second clock signal end in the N-th shift register is electrically connected with the fourth clock signal wire; the first clock signal end in the N+1st shift register is electrically connected with the third clock signal line, and the second clock signal end in the N+1st shift register is electrically connected with the first clock signal line; the first clock signal end in the N+2-stage shift register is electrically connected with the fourth clock signal line, and the second clock signal end in the N+2-stage shift register is electrically connected with the second clock signal line; the first clock signal end in the N+3 stage shift register is electrically connected with the first clock signal line, and the second clock signal end in the N+3 stage shift register is electrically connected with the third clock signal line.

In a possible implementation manner of the second aspect, clock signal periods of clock signals provided by the first clock signal line, the second clock signal line, the third clock signal line and the fourth clock signal line are identical.

In a possible implementation manner of the second aspect, the shift register output terminal of the N-1 th stage shift register is multiplexed into the shift register input terminal of the N-th stage shift register; the shift register output of the nth shift register is multiplexed as the shift register input of the n+1th shift register.

In a possible implementation manner of the second aspect, the enable level stage of the signal output by the shift register output terminal of the N-1 st stage shift register coincides with one enable level stage of the clock signal provided by the first clock signal line.

Based on the same inventive concept, in a third aspect, an embodiment of the present application provides a display panel, which includes the gate driving circuit provided in any of the foregoing embodiments of the second aspect of the present application.

Based on the same inventive concept, in a fourth aspect, an embodiment of the present application provides a display panel including the display panel as provided in the third aspect of the present application.

The embodiment of the application provides a shift register, a grid driving circuit, a display panel and a display device, wherein an input module, a first control module, a second control module, a third control module, a first output module and a second output module are arranged in the shift register, wherein the second control module can be used for adjusting the potential of a third node so as to control the conduction of the first output module; the input module, the second control module and the third control module can be used for adjusting the potential of the first node, so that the conduction of the second output module can be controlled. Therefore, the first output module and the second output module are flexibly controlled to be conducted, so that the shift register can output corresponding scanning pulse waveforms according to the requirements of actual pixel circuits. According to the shift register, the grid driving circuit, the display panel and the display device, based on the improved circuit structure and the control of the clock signal, scanning pulse waveforms which can be overlapped and not overlapped by the adjacent stage shift register can be effectively output, so that the diversified requirements of the pixel circuit on the scanning pulse waveforms can be fully met.

Drawings

In order to more clearly illustrate the technical solution of the embodiments of the present application, the drawings that are needed to be used in the embodiments of the present application will be briefly described, and it is possible for a person skilled in the art to obtain other drawings according to these drawings without inventive effort.

Fig. 1 is a schematic diagram of a shift register in the related art according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a shift register according to an embodiment of the present application;

FIG. 3 is a schematic diagram of another shift register according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a shift register according to another embodiment of the present application;

FIG. 5 is a schematic diagram of a shift register according to another embodiment of the present application;

FIG. 6 is a timing diagram of a shift register according to an embodiment of the present application;

FIG. 7 is a timing diagram of another shift register according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a shift register according to another embodiment of the present application;

fig. 9 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present application;

FIG. 10 is a timing diagram of a gate driving circuit according to an embodiment of the present application;

FIG. 11 is a timing diagram of another gate driving circuit according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present application;

fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings and the detailed embodiments. It should be understood that the particular embodiments described herein are meant to be illustrative of the application only and not limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the application by showing examples of the application.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

It should be noted that, the transistor in the embodiment of the present application may be an N-type transistor or a P-type transistor. For an N-type transistor, the on level is high and the off level is low. That is, the gate of the N-type transistor is on between the first and second poles when the gate is high, and is off between the first and second poles when the gate is low. For a P-type transistor, the on level is low and the off level is high. That is, when the control of the P-type transistor is at a very low level, the first pole and the second pole are turned on, and when the control of the P-type transistor is at a high level, the first pole and the second pole are turned off. In a specific implementation, the gate of each transistor is used as a control electrode, and the first electrode of each transistor may be used as a source electrode, the second electrode may be used as a drain electrode, or the first electrode may be used as a drain electrode, and the second electrode may be used as a source electrode, which is not distinguished herein.

In embodiments of the present application, the term "electrically connected" may refer to two components being directly electrically connected, or may refer to two components being electrically connected via one or more other components.

In the embodiment of the present application, the first node, the second node, and the third node are defined only for convenience in describing the circuit structure, and the first node, the second node, and the third node are not one actual circuit unit.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Accordingly, it is intended that the present application covers the modifications and variations of this application provided they come within the scope of the appended claims (the claims) and their equivalents. The embodiments provided by the embodiments of the present application may be combined with each other without contradiction.

Before describing the technical solution provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application firstly specifically describes the problems existing in the related art:

the present inventors have studied and found that, under the current and abundant display market demands, various requirements are put on the display of the OLED display panel, such as ultra-high frequency, high-low frequency, etc., which requires that the panel circuit can be diversified. However, in the prior art, the GIP circuit has a relatively single function, and the output scanning pulse waveform is often relatively fixed, so that the requirement of the pixel circuit for diversifying the output scanning signals cannot be met flexibly.

Further research by the inventor of the present application shows that the function of the GIP circuit in the prior art is relatively single, and in particular, the existing Scan GIP circuit can only output Scan pulse waveforms with enabling levels not overlapping between two adjacent rows. However, the current pixel circuits tend to have multiple requirements for each signal waveform, and the current Scan GIP circuit cannot meet the requirements when the pixel circuits need the Scan pulse waveforms overlapped by two adjacent rows of enable levels.

Fig. 1 is a schematic diagram of a shift register in the related art according to an embodiment of the present application. As shown in fig. 1, the shift register/Scan GIP circuit in the prior art includes transistors M1, M2, M3, M4, M5, M6, M7, and M8, a capacitor C1, and a capacitor C2. Limited to this 8T2C circuit configuration, the existing Scan GIP circuit is often only capable of outputting Scan pulse waveforms that are not overlapped by two adjacent rows of enable level stages.

In order to solve the problems, the application provides a novel shift register circuit structure based on the improvement of the conventional 8T2C circuit, so as to achieve the technical effect of outputting up-down overlapped scanning pulse waveforms and non-overlapped scanning pulse waveforms based on the improved circuit structure.

Specifically, the embodiment of the application provides a shift register, a gate driving circuit, a display panel and a display device. It should be noted that the examples provided by the present application are not intended to limit the scope of the present disclosure.

The shift register provided by the embodiment of the application is first described below.

Fig. 2 is a schematic structural diagram of a shift register according to an embodiment of the present application. As shown in fig. 2, the shift register 1 includes an input module 101, a first control module 102, a second control module 103, a third control module 104, a first output module 105, and a second output module 106.

Specifically, the input module 101 may be configured to transmit the initial input signal provided by the shift register input terminal SIN to the first node N1 under the control of the shift register input terminal SIN.

In particular, if the initial input signal provided by the shift register output terminal SIN is an enable level, the input module may transmit the enable level of the shift register input terminal SIN to the first node N1 in response to the enable level of the shift register input terminal SIN being turned on.

The first control module 102 is configured to adjust the potential of the third node N3 under the control of the first clock signal terminal sck1 and the shift register input terminal SIN. The second control module 103 is configured to adjust the potential of the first node N1 under the control of the third node N3 and the second clock signal terminal sck 2. The third control module 104 is configured to adjust the potential of the first node N1 under the control of the output terminal gout_n+m of the shift register of the next M stages, where M is a positive integer.

In a specific implementation, the first control module 102, the second control module 103, and the third control module 104 can implement flexible control of the node potentials of the first node N1 and the third node N3 by matching with different clock signal timings.

The first output module 105 is connected to the first level voltage signal terminal VGH and the shift register output terminal gout_n, and is configured to transmit the first level voltage provided by the first level voltage signal terminal VGH to the shift register output terminal gout_n under the control of the third node N3.

Specifically, when the node potential of the third node is the enable level, the first output module 105 is turned on to transmit the first level voltage provided by the first level voltage signal terminal VGH to the shift register output terminal gout_n.

The second output module 106 is connected to the second clock signal terminal sck2 and the shift register output terminal gout_n, and is configured to transmit the second clock signal provided by the second clock signal terminal sck2 to the shift register output terminal gout_n under the control of the first node N1. For example, when the node potential of the first node N1 is at the enable level, the second output module 106 is turned on to supply the second clock signal provided by the second clock signal terminal sck2 to the shift register output terminal gout_n.

In some possible embodiments, the second output module 106 is connected to the second clock signal terminal sck2 and the shift register output terminal gout_n, and may be specifically configured to transmit the second clock signal provided by the second clock signal terminal sck2 to the shift register output terminal gout_n under the control of the first node N1 and the second node N2.

Specifically, when the node potential of the second node N2 is at the enable level, the second output module 106 is turned on to supply the second clock signal provided by the second clock signal terminal sck2 to the shift register output terminal gout_n.

In this embodiment, when the node potential of the second node N2 is greater than the threshold voltage, the node potential of the second node N2 follows the node potential of the first node N1. For example, when the node potential of the first node N1 is at the enable level, the node potential of the second node N2 is also changed to the enable level.

When the node potential of the second node N2 is less than or equal to the preset threshold, the node potential of the second node N2 is not affected by the potential of the first node N1. For example, when the node potential of the second node N2 is smaller than the preset threshold value and the node potential of the first node N1 becomes high level, the node potential of the second node N2 does not change along with the first node N1.

In this embodiment, the shift register 1 is provided with an input module 101, a first control module 102, a second control module 103, a third control module 104, a first output module 105, and a second output module 106, where the first control module 102 may be used to adjust a node potential of the third node N3, so as to control conduction of the first output module 105; the input module 101, the second control module 103 and the third control module 104 may be configured to adjust the node potential of the first node N1, so as to control the conduction of the second output module 106. In this way, by flexibly controlling the conduction of the first output module 105 and the second output module 106, the shift register can output a corresponding scanning pulse waveform according to the actual pixel circuit requirement.

According to the shift register 1 provided by the embodiment of the application, based on the improved circuit structure and in combination with the control of corresponding clock signals, scanning pulse waveforms which can be overlapped and not overlapped by the shift registers of adjacent stages can be effectively output, so that the diversified requirements of pixel circuits in a display panel on the scanning pulse waveforms can be fully met.

In some more specific embodiments, in order to reasonably realize the control of overlapping or non-overlapping of the scanning pulse waveforms output by the adjacent stage shift register, so as to more effectively meet the diversified requirements of the pixel circuit on the scanning pulse waveforms, further, the enabling level pulse width of the first clock signal and the enabling level pulse width of the second clock signal meet the first preset condition, and the adjacent stage shift register 1 outputs the non-overlapping scanning pulse waveforms.

The enable level pulse width of the first clock signal and the enable level pulse width of the second clock signal satisfy a second preset condition, and the adjacent stage shift register 1 outputs overlapping scan pulse waveforms. The first clock signal is provided by a first clock signal terminal sck1, and the second clock signal is provided by a second clock signal terminal sck 2.

In this embodiment, by controlling and adjusting the enable level pulse width of the first clock signal and the enable level pulse width of the second clock signal, when the enable level pulse width of the first clock signal and the enable level pulse width of the second clock signal meet different conditions, adjacent shift registers cooperate to output scan pulse waveforms with or without overlapping enable level stages.

Note that, in this embodiment, specific development is not performed for the first preset condition and the second preset condition. The first preset condition may, for example, be that the enable level pulse width of the first clock signal is within a first preset range, and the enable level pulse width of the second clock signal is within a second preset range, where the first preset range may be consistent or inconsistent with the second preset range. The second preset condition may, for example, be that the enable level pulse width of the first clock signal is within a third preset range, and the enable level pulse width of the second clock signal is within a fourth preset range, where the third preset range may be consistent or inconsistent with the fourth preset range, and the application is not limited thereto strictly.

In some more specific embodiments, further, in order to accurately control the overlapping or non-overlapping of the scan pulse waveforms output by the shift registers of adjacent stages, so as to more reasonably meet the diversified requirements of the pixel circuit on the scan pulse waveforms, an enable level start time of the first clock signal and an enable level start time of the second clock signal are separated by 1/2 clock signal period.

When the enable level pulse width of the first clock signal and the enable level pulse width of the second clock signal are smaller than 1/4 clock signal period or equal to 1/4 clock signal period, the adjacent stage shift registers 1 output scan pulse waveforms that do not overlap. When the enable level pulse width of the first clock signal and the second clock signal is equal to 1/2 clock signal period, or more than 1/4 clock signal period and less than 1/2 clock signal period, the adjacent stage shift registers 1 output overlapping scan pulse waveforms.

In this embodiment, based on the foregoing circuit structure of the shift register 1, by matching the control of the corresponding first clock signal and the second clock signal, the adjacent stage shift register can effectively output scan pulse waveforms that may overlap or not overlap. Specifically, by controlling the enable level pulse width of the first clock signal and the enable level pulse width of the second clock signal to be equal to or smaller than 1/4 clock signal period, the shift registers of adjacent stages can output scan pulse waveforms that do not overlap under the control of the first clock signal and the second clock signal. By controlling the pulse width of the enabling level of the first clock signal and the second clock signal to be equal to 1/2 clock signal period or more than 1/4 clock signal period and less than 1/2 clock signal period, the shift registers of adjacent stages can output overlapped scanning pulse waveforms under the control of the first clock signal and the second clock signal.

Therefore, the control of overlapping or non-overlapping of the scanning pulse waveforms output by the adjacent stage shift register can be more accurately realized by adjusting the range of the enabling level pulse widths of the first clock signal and the second clock signal, so that the diversified requirements of the pixel circuit on the scanning pulse waveforms can be more reasonably met.

In some embodiments, as a specific example, when the enable level pulse widths of the first clock signal and the second clock signal are each 1/4 clock signal period, the adjacent stage shift registers output scan pulse waveforms that do not overlap. When the pulse widths of the enabling level of the first clock signal and the second clock signal are 1/2 clock signal period, the adjacent stage shift register 1 outputs overlapped scanning pulse waveforms.

In some more specific embodiments, the enable level pulse widths of the first clock signal and the second clock signal are the same, and the clock signal periods of the first clock signal and the second clock signal are the same.

In this way, when the time sequence adjustment of the first clock signal and the second clock signal is performed, the pulse widths of the enabling levels of the first clock signal and the second clock signal are uniformly adjusted by referring to the clock signal periods of the first clock signal and the second clock signal, so that the adjacent stage shift register can output overlapping or non-overlapping scanning pulse waveforms by adjusting the pulse widths of the enabling levels of the first clock signal and the second clock signal.

In some more specific embodiments, in connection with a specific circuit operation in the display panel, in order to more reasonably set the timing of the clock signals, the 1/4 clock signal period is equal to the scanning time of a row of pixel circuits.

The display panel comprises a plurality of rows of pixel circuits, and each pixel circuit is connected with a light-emitting element. In display operation, it is generally necessary to scan pixel circuits line by each stage of shift registers so that each row of pixel circuits is sequentially initialized, written with data, and the like. In this way, when the light emission stage corresponding to each row of pixel circuits arrives, the light emitting element can be smoothly driven to emit light.

In this embodiment, in combination with the operating characteristics of the pixel circuits in the display panel, the 1/4 clock signal period may be set equal to the scanning time of one row of pixel circuits, so as to more reasonably match the scanning time of the pixel circuits, thereby implementing efficient operation of each circuit in the display panel.

In some more specific embodiments, further, in the above shift register 1, the enable level pulse width of the initial input signal provided by the shift register input terminal SIN is the same as the enable level pulse width of the second clock signal, and the enable level phase of the initial input signal provided by the shift register input terminal SIN is advanced by 1/4 clock signal period compared to one enable level phase of the second clock signal.

In some more specific embodiments, the specific connection relation of the modules in the shift register 1 according to the present application will be described in detail with reference to fig. 2.

Specifically, as shown in fig. 2, the control terminal and the first terminal of the input module 101 are electrically connected to the shift register output terminal gout_n, and the second terminal of the input module 101 is electrically connected to the first node N1. If the initial input signal provided by the shift register output terminal SIN is the enable level, the input module 101 may transmit the enable level of the shift register input terminal SIN to the first node N1 in response to the enable level of the shift register input terminal SIN being turned on.

The first control module 102 is electrically connected to the first control end and the first clock signal end sck1, the second control end of the first control module 102 is electrically connected to the input end SIN of the shift register, the first input end of the first control module 102 is electrically connected to the second level voltage signal end VGL, the second input end of the first control module 102 is electrically connected to the first clock signal end sck1, and the output end of the first control module 102 is electrically connected to the third node N3. The first control module 102 may transmit the level voltage provided by the second level voltage signal terminal VGL or the clock signal provided by the first clock signal terminal sck1 to the third node N3 in response to the level signals provided by the first clock signal terminal sck1 and the shift register input terminal SIN, so as to implement adjustment of the node potential of the third node N3.

The first control end of the second control module 103 is electrically connected to the third node N3, the second control end of the second control module 103 is electrically connected to the second clock signal end sck2, the first end of the second control module 103 is electrically connected to the first level voltage signal end VGH, and the second end of the second control module 103 is electrically connected to the second node N2. Specifically, the second control module 103 may be turned on when the node potential of the third node N3 is the enable level and the second clock signal terminal sck2 provides the enable level, and transmit the first level voltage provided by the first level voltage signal terminal VGH to the first node N1, so as to implement adjustment of the potential of the first node N1.

The control end of the third control module 104 is electrically connected to the output end gout_n+m of the shift register of the subsequent M stages, the first end of the third control module 104 is electrically connected to the first level voltage signal end VGH, and the second end of the third control module 104 is electrically connected to the first node N1. Specifically, when the output terminal gout_n+m of the shift register of the subsequent M stages outputs the on level, the third control module 104 transmits the first level voltage provided by the first level voltage signal terminal VHG to the first node N1 in response to the on level, thereby implementing the adjustment of the node potential of the first node N1.

It should be noted that, in fig. 2, only one case where the value of M is 2 is shown, and in other possible embodiments, the value of M may also be other values, which is not strictly limited by the present application.

The control terminal of the first output module 105 is electrically connected to the third node N3, the first terminal of the first output module 105 is electrically connected to the first level voltage signal terminal VGH, and the second terminal of the first output module 105 is electrically connected to the shift register output terminal gout_n. When the node potential of the third node is at the enable level, the first output module 105 is turned on to transmit the first level voltage provided by the first level voltage signal terminal VGH to the shift register output terminal gout_n.

The control end of the second output module 106 is electrically connected to the second node N2, the first end of the second output module 106 is electrically connected to the shift register output end gout_n, and the second end of the second output module 106 is electrically connected to the second clock signal end sck 2. When the node potential of the second node N2 is at the enable level, the second output module 106 is turned on to provide the second clock signal from the second clock signal terminal sck2 to the shift register output terminal gout_n.

Referring to fig. 3, fig. 3 is a schematic diagram of another shift register according to an embodiment of the application. As shown in fig. 3, in some embodiments, in conjunction with a specific device structure, in order to better implement functions performed by each module in the shift register 1, optionally, the input module 101 may include a first transistor M1, the second control module 103 may include a second transistor M2 and a third transistor M3, the first control module 102 may include a fourth transistor M4 and a fifth transistor M5, the first output module 105 may include a sixth transistor M6, the second output module 106 may include a seventh transistor M7, and the third control module 104 may include an eighth transistor M8.

When the specific circuit is connected, the control end and the first end of the first transistor M1 are electrically connected to the input end SIN of the shift register, and the second end of the first transistor M1 is electrically connected to the first node N1. The control terminal of the second transistor M2 is electrically connected to the second clock signal terminal sck2, the first terminal of the second transistor M2 is electrically connected to the second terminal of the third transistor M3, and the second terminal of the second transistor M2 is electrically connected to the first node N1. The control terminal of the third transistor M3 is electrically connected to the third node N3, and the first terminal of the third transistor M3 is electrically connected to the first level voltage signal terminal VGH. The control terminal of the fourth transistor M4 is electrically connected to the shift register input terminal SIN, the first terminal of the fourth transistor M4 is electrically connected to the third node N3, and the second terminal of the fourth transistor M4 is electrically connected to the second clock signal terminal sck 2. The control terminal of the fifth transistor M5 is electrically connected to the second clock signal terminal sck2, the first terminal of the fifth transistor M5 is electrically connected to the second level voltage signal terminal VGL, and the second terminal of the fifth transistor M5 is electrically connected to the third node N3. The control terminal of the sixth transistor M6 is electrically connected to the third node N3, the first terminal of the sixth transistor M6 is electrically connected to the first level voltage signal terminal VGH, and the second terminal of the sixth transistor M6 is electrically connected to the shift register output terminal gout_n. The control terminal of the seventh transistor M7 is electrically connected to the second node N2, the first terminal of the seventh transistor M7 is electrically connected to the shift register output terminal gout_n, and the second terminal of the seventh transistor M7 is electrically connected to the second clock signal terminal sck 2. The control terminal of the eighth transistor M8 is electrically connected to the output terminal gout_n of the shift register of the subsequent M stages, the first terminal of the eighth transistor M8 is electrically connected to the first node N1, and the second terminal of the eighth transistor M8 is electrically connected to the first level voltage signal terminal VGH. And, the transistors referred to in this embodiment are P-type driving transistors. It should be noted that, in other embodiments, the channel types of the above transistors may be flexibly adjusted according to practical situations, which is not strictly limited by the present application.

In some more specific embodiments, optionally, M has a value of 2. In other possible embodiments, the value of M may be other values, which is not strictly limited by the present application.

Referring to fig. 4, fig. 4 is a schematic diagram illustrating a structure of a shift register according to another embodiment of the application. As shown in fig. 4, in order to better be able to effectively output scan pulse waveforms that can be overlapped and not overlapped by the shift registers of adjacent stages based on the improved circuit structure, so as to more fully satisfy the requirement of the pixel circuit for diversifying the scan pulse waveforms, optionally, in some more specific embodiments, the shift register 1 may further include a first storage module 107, a second storage module 108, and a first switch module 109.

Specifically, a first end of the first memory module 107 is electrically connected to the first level voltage signal terminal VGH, and a second end of the first memory module 107 is electrically connected to the third node N3 for maintaining the node potential of the third node N3 stable. The first end of the second memory module 108 is electrically connected to the output terminal gout_n of the shift register, and the second end of the second memory module 108 is electrically connected to the second node N2, so as to bootstrap and maintain the node potential of the second node N2. The control terminal of the first switch module 109 is electrically connected to the second level voltage signal terminal VGL, the first terminal of the first switch module 109 is electrically connected to the first node N1, and the second terminal of the first switch module 109 is electrically connected to the second node N2.

Referring to fig. 5, fig. 5 is a schematic diagram of a shift register according to another embodiment of the application. As shown in fig. 5, in some embodiments, in order to better implement the functions performed by the respective modules in the shift register 1 shown in fig. 4 in connection with a specific device structure, optionally, in some more specific embodiments, the first storage module 107 may include a first capacitor C1, the second storage module 108 may include a second capacitor C2, and the first switch module 109 may include a ninth transistor M9.

Specifically, the first pole of the first capacitor C1 may be electrically connected to the first level voltage signal terminal VGH, and the second pole of the first capacitor C1 may be electrically connected to the third node N3. The first end of the second capacitor C2 is electrically connected to the shift register output terminal gout_n, and the second end of the second capacitor C2 is electrically connected to the second node N2. The control terminal of the ninth transistor M9 is electrically connected to the second level voltage signal terminal VGL, the first terminal of the ninth transistor M9 is electrically connected to the first node N1, and the second terminal of the ninth transistor M9 is electrically connected to the second node N2. And, the transistors referred to in this embodiment are P-type driving transistors. It should be noted that, in other embodiments, the channel types of the above transistors may be flexibly adjusted according to practical situations, which is not strictly limited by the present application.

In order to facilitate understanding of the shift register 1 provided by the present application, the following description will be made with reference to some specific application embodiments. Please refer to fig. 6 and 7. FIG. 6 is a timing diagram of a shift register according to an embodiment of the present application; fig. 7 is a timing diagram of another shift register according to an embodiment of the present application.

The operation of the shift register 1 shown in fig. 5 will be described in detail with reference to the timings shown in fig. 6 and 7, respectively. Before the description, it should be noted that, in the present embodiment, the first level voltage provided by the first level voltage signal terminal VGH may be a non-enable level, and the second level voltage provided by the second level voltage signal terminal VHL may be an enable level.

Referring to the timing arrangement shown in fig. 6, the enable level pulse widths of the first clock signal and the second clock signal in fig. 6 are 1/2 clock signal period. Specifically, if the adjacent stage shift register 1 outputs overlapped scan pulse waveforms, in the first stage t1, the shift register input terminal SIN provides a disable level, the first clock signal terminal sck1 provides an enable level, and the second clock signal terminal sck2 provides a disable level; the first control module 102 is turned on to transmit the second level voltage provided by the second level voltage signal terminal VGL to the third node N3, and the first output module 105 is turned on to transmit the disable level provided by the first level voltage signal terminal VGH to the shift register output terminal gout_n.

In connection with the specific device structure of fig. 5: in the first stage, the shift register input SIN provides a disable level, the first clock signal sck1 provides an enable level, and the second clock signal sck2 provides a disable level. The fifth transistor M5 is turned on to transmit the enable level provided by the second level voltage signal terminal VGL to the third node N3. The sixth transistor M6 transmits the disable level provided by the first level voltage signal terminal VGH to the shift register output terminal gout_n in response to the on level of the third node N3. At this stage, the shift register output gout_n outputs a disable level.

In the second stage t2, the shift register input terminal SIN provides an enable level, the first clock signal terminal sck1 provides an enable level, and the second clock signal terminal sck2 provides a disable level; the first control module is conducted, and the third node is an enabling level; the first output module responds to the conduction of the enabling level of the third node and transmits the enabling level of the first level voltage signal end to the output end of the shift register; the input module 101 is turned on to transmit the enable level provided by the input terminal SIN of the shift register to the first node N1; the second output module 106 transmits the disable level provided by the second clock signal terminal sck2 to the shift register output terminal gout_n in response to the enable level of the second node N2 being turned on.

In connection with the specific device structure of fig. 5: in the second stage, the shift register input SIN provides an enable level, the first clock signal sck1 provides an enable level, and the second clock signal sck2 provides a disable level. The first transistor M1 is turned on in response to the enable level provided at the shift register input terminal SIN, and transmits the enable level provided at the shift register input terminal SIN to the first node N1. The control terminal of the ninth transistor M9 is electrically connected to the second level voltage terminal VGL, and may be normally equivalent to a normally open transistor. In this stage, the enable level at the first node N1 is transmitted to the second node N2 through the turned-on ninth transistor M, and the node potential of the second node N2 becomes the enable level. The seventh transistor M7 is turned on in response to the enable level of the second node N2, and transmits the disable level provided by the second clock signal terminal sck2 to the shift register output terminal gout_n. The fifth transistor M5 is turned on in response to the enable level provided by the first clock signal terminal sck1, and transmits the enable level of the second level voltage signal terminal VGL to the third node N3, the fourth transistor M5 is turned on in response to the enable level provided by the shift register input terminal SIN, and transmits the enable level of the first clock signal terminal sck1 to the third node N3, and the sixth transistor M6 is turned on, and transmits the enable level of the first level voltage signal terminal VGH to the shift register output terminal gout_n. At this stage, the shift register output terminal gout_n also outputs the disable level.

In the third stage t3, the shift register input terminal SIN provides an enable level, the first clock signal terminal sck1 provides a disable level, and the second clock signal terminal sck2 provides an enable level; the node potential of the second node N2 is lower than the enable level; the second output module 106 is turned on to transmit the enable level provided by the second clock signal terminal sck2 to the shift register output terminal gout_n.

In connection with the specific device structure of fig. 5: in the third stage, the shift register input SIN provides an enable level, the first clock signal sck1 provides a disable level, and the second clock signal sck2 provides an enable level. The fifth transistor M5 is turned off in response to the disable level of the first clock signal terminal sck1, the fourth transistor M4 is turned on in response to the enable level provided by the shift register input terminal SIN, the disable level provided by the first clock signal terminal sck1 is transferred to the third node N3, and the sixth transistor M6 is turned off in response to the disable level of the third node N3. The second clock signal terminal sck2 jumps from the non-enable level of the previous stage to the enable level, and the second node N2 is continuously pulled down to be lower than the enable level of the previous stage due to the bootstrap effect of the second capacitor C2, at this time, the ninth transistor M9 is turned off, and the node potential of the first node N1 does not affect the node potential of the second node N2. The seventh transistor M7 is turned on to transmit the enable level provided by the second clock signal terminal sck2 to the shift register output terminal gout_n. At this stage, the shift register output terminal gout_n outputs an enable level.

In the fourth stage t4, the shift register input terminal SIN provides a disable level, the first clock signal terminal sck1 provides a disable level, and the second clock signal terminal sck2 provides an enable level; the input module 101 is turned off, and the second node N2 maintains an enable level; the second output module 106 is turned on to transmit the enable level provided by the second clock signal terminal sck2 to the shift register output terminal gout_n.

In connection with the specific device structure of fig. 5: in the fourth stage, the shift register input SIN provides a disable level, the first clock signal sck1 provides a disable level, and the second clock signal sck2 provides an enable level. The first transistor M1 is turned off in response to a disable level provided at the shift register input SIN. Due to the memory maintaining effect of the second capacitor C2, the seventh transistor M7 can keep on, and transmit the enable level provided by the second clock signal sck2 to the shift register output terminal gout_n. At this stage, the shift register output terminal gout_n outputs an enable level.

In the fifth stage t5, the shift register input terminal SIN provides a disable level, the first clock signal terminal sck1 provides an enable level, and the second clock signal terminal sck2 provides a disable level; the first control module 102 is turned on to transmit the second level voltage provided by the second level voltage signal terminal VGL to the third node N3; the first output module 105 is turned on to transmit the disable level provided by the first level voltage signal terminal VGH to the shift register output terminal gout_n.

In connection with the specific device structure of fig. 5: the shift register input SIN provides a disable level, the first clock signal sck1 provides an enable level, and the second clock signal sck2 provides a disable level. The first transistor M1 and the fourth transistor M4 are turned off in response to the disable level provided at the shift register input terminal SIN, the fifth transistor M5 is turned on in response to the enable level provided at the first clock signal terminal sck2, the enable level provided at the second level voltage signal terminal VGL is transmitted to the third node N3, and the sixth transistor M6 is turned on in response to the enable level of the third node N3, and the disable level provided at the first level voltage signal terminal VGH is transmitted to the shift register output terminal gout_n. Meanwhile, the output terminal gout_n+2 of the shift register of the latter 2 stages outputs an enable level, and the eighth transistor M8 is turned on to transmit the disable level provided by the first level voltage signal terminal VGH to the first node N1. The ninth transistor M9 is turned on, the node potential of the second node N2 becomes a non-enable level with the node potential of the first node N1, and the seventh transistor M7 is turned off. At this stage, the shift register output gout_n outputs a disable level.

In the sixth stage t6, the shift register output terminal gout_n provides the disable level; the first control module 102 is turned off, and the third node N3 maintains an enable level; the first output module 105 is turned on to transmit the disable level provided by the first level voltage signal terminal VGH to the shift register output terminal gout_n.

In connection with the specific device structure of fig. 5: at this stage, the shift register output gout_n provides a disable level, and the first transistor M1 remains turned off. Under the maintaining action of the first capacitor C1, the node potential of the third node N3 maintains the enabling level of the previous stage, the sixth transistor M6 is continuously turned on, and the third transistor M3 is turned on.

The second clock signal terminal sck2 provides an enable level, and the second transistor M2 is turned on. The third transistor M3 transmits the disable level provided by the first level voltage signal terminal VGH to the first terminal of the second transistor M2, the second transistor M2 transmits the disable level of the first terminal thereof to the first node N1, the first node N1 becomes the disable level, the ninth transistor M9 is turned on, the node potential of the second node N2 becomes the disable level along with the first node N1, and the seventh transistor remains turned off. If the second clock signal sck2 provides the disable level, the working process can be the same as that of the first stage, and the present application will not be described herein.

Alternatively, referring to the timing arrangement shown in fig. 7, the enable level pulse widths of the first clock signal and the second clock signal in fig. 7 are 1/4 clock signal period. Specifically, if the adjacent stage shift registers 1 output non-overlapping scan pulse waveforms, in the first stage t1, the shift register input terminal SIN provides a disable level, the first clock signal terminal sck1 provides an enable level, and the second clock signal terminal sck2 provides a disable level; the first control module 102 is turned on to transmit the second level voltage provided by the second level voltage signal terminal VGL to the third node N3, and the first output module 105 is turned on to transmit the disable level provided by the first level voltage signal terminal VGH to the shift register output terminal gout_n.

In the second stage t2, the shift register input terminal SIN provides an enable level, the first clock signal terminal sck1 provides a disable level, and the second clock signal terminal sck2 provides a disable level; the input module 101 is turned on to transmit the enable level provided by the input terminal SIN of the shift register to the first node N1; the second output module 106 transmits the disable level provided by the second clock signal terminal sck2 to the shift register output terminal gout_n in response to the enable level of the second node N2 being turned on.

In connection with the specific device structure of fig. 5: in the second stage, the shift register input SIN provides an enable level, the first clock signal sck1 provides a disable level, and the second clock signal sck2 provides a disable level. The first transistor M1 is turned on in response to the enable level provided at the shift register input terminal SIN, and transmits the enable level provided at the shift register input terminal SIN to the first node N1. The control terminal of the ninth transistor M9 is electrically connected to the second level voltage terminal VGL, and may be normally equivalent to a normally open transistor. In this stage, the enable level at the first node N1 is transmitted to the second node N2 through the turned-on ninth transistor M, and the node potential of the second node N2 becomes the enable level. The seventh transistor M7 is turned on in response to the enable level of the second node N2, and transmits the disable level provided by the second clock signal terminal sck2 to the shift register output terminal gout_n. At this stage, the shift register output terminal gout_n also outputs the disable level.

In the third stage t3, the shift register input terminal SIN provides a disable level, the first clock signal terminal sck1 provides a disable level, and the second clock signal terminal sck2 provides an enable level; the node potential of the second node N2 is lower than the enable level; the second output module 106 is turned on to transmit the enable level provided by the second clock signal terminal sck2 to the shift register output terminal gout_n.

In the fourth stage t4, the shift register input terminal SIN provides a disable level, the first clock signal terminal sck1 provides a disable level, and the second clock signal terminal sck2 provides a disable level; the second node N2 maintains an enable level; the second output module 106 is turned on to transmit the disable level provided by the second clock signal terminal sck2 to the shift register output terminal gout_n.

In connection with the specific device structure of fig. 5: in the fourth stage, the shift register input SIN provides a disable level, the first clock signal sck1 provides a disable level, and the second clock signal sck2 provides a disable level. The first transistor M1 is turned off in response to a disable level provided at the shift register input SIN. Due to the memory maintaining effect of the second capacitor C2, the seventh transistor M7 can keep on, and the disable level provided by the second clock signal sck2 is transmitted to the shift register output terminal gout_n. At this stage, the shift register output gout_n outputs a disable level.

In the sixth stage t6, the shift register output gout_n provides the disable level; the first control module 102 is turned off, and the third node N3 maintains an enable level; the first output module 105 is turned on to transmit the disable level provided by the first level voltage signal terminal VGH to the shift register output terminal gout_n.

Please note that, please refer to fig. 8, fig. 8 is a schematic diagram illustrating a structure of another shift register according to an embodiment of the present application. Fig. 8 is substantially identical to the circuit configuration shown in fig. 5 above, except that: in fig. 5, the control terminal of the fourth transistor M4 is electrically connected to the shift register input terminal SIN; in fig. 8, the control terminal of the fourth transistor M4 is directly electrically connected to the first node N1, i.e., the fourth transistor M4 is directly controlled by the node potential change of the first node N1.

It should be understood that in practice the node potential of the first node N1 is also affected by the signal provided at the input SIN of the shift register. Therefore, in the shift register 1 shown in fig. 8, the fourth transistor M4 may be indirectly controlled by the shift register input SIN, and the scheme should also be included in the protection scope of the present application.

Based on the same inventive concept, the embodiment of the application provides a gate driving circuit. Referring to fig. 9, fig. 9 is a schematic diagram of a gate driving circuit according to an embodiment of the application. As shown in fig. 9, the gate driving circuit 10 may include a plurality of shift registers 1 provided in any of the foregoing embodiments of the present application, and in the gate driving circuit 10, the plurality of shift registers 1 are cascade-connected.

The gate driving circuit 10 of the embodiment of the application comprises a plurality of cascaded shift registers 1. Based on the improved circuit structure of the shift register 1 and the control of corresponding clock signals, the adjacent stage shift registers in the gate driving circuit 10 can output overlapping and non-overlapping scanning pulse waveforms, so that the diversified requirements of the pixel circuits in the display panel on the scanning pulse waveforms can be fully met.

In some more specific embodiments, the first clock signal and the second clock signal in the n+1th stage shift register 1 have a predetermined phase difference from the first clock signal and the second clock signal in the N-th stage shift register 1, and N is a positive integer.

In some more specific embodiments, optionally, the gate driving circuit 10 may include the first clock signal line SCK1, the second clock signal line SCK2, the third clock signal line SCK3 and the fourth clock signal line SCK4 in consideration of a cascade multiplexing arrangement of clock signals in the gate driving circuit.

Specifically, the clock signals supplied from the first clock signal line SCK1, the second clock signal line SCK2, the third clock signal line SCK3, and the fourth clock signal line SCK4 are sequentially separated by 1/4 clock signal period. The first clock signal terminal SCK1 in the nth stage shift register 1 is electrically connected to the second clock signal line SCK2, and the second clock signal terminal SCK2 in the nth stage shift register 1 is electrically connected to the fourth clock signal line SCK4. The first clock signal terminal SCK1 in the n+1th stage shift register 1 is electrically connected to the third clock signal line SCK3, and the second clock signal terminal SCK2 in the n+1th stage shift register 1 is electrically connected to the first clock signal line SCK 1. The first clock signal terminal SCK1 in the n+2stage shift register 1 is electrically connected to the fourth clock signal line SCK4, and the second clock signal terminal SCK2 in the n+2stage shift register 1 is electrically connected to the second clock signal line SCK 2. The first clock signal terminal SCK1 in the n+3rd stage shift register 1 is electrically connected to the first clock signal line SCK1, and the second clock signal terminal SCK2 in the n+3rd stage shift register 1 is electrically connected to the third clock signal line SCK 3.

In this way, the shift multiplexing of the clock signals of the shift register 1 in the gate driving circuit 10 is realized based on the first clock signal line SCK1, the second clock signal line SCK2, the third clock signal line SCK3, and the fourth clock signal line SCK 4.

In some more specific embodiments, the clock signal periods of the clock signals provided by the first clock signal line SCK1, the second clock signal line SCK2, the third clock signal line SCK3, and the fourth clock signal line SCK4 are identical. Further, in connection with practical implementation scenario, the clock signal period may be the same as the scanning time of four consecutive rows of pixel circuits.

In some more specific embodiments, in order to more reasonably implement cascading and signal multiplexing of the multi-stage shift registers in the gate driving circuit 10, in the gate driving circuit 10 of the present application, the shift register output terminal gout_n of the N-1 stage shift register 1 may be multiplexed into the shift register input terminal of the N-1 stage shift register 1; the shift register output terminal gout_n of the nth stage shift register 1 is multiplexed as the shift register input terminal of the n+1th stage shift register 1.

In some more specific embodiments, in connection with the operation of the actual shift register in the gate driving circuit, the enable level stage of the signal output by the shift register output terminal gout_n of the N-1 st stage shift register 1 is consistent with one enable level stage of the clock signal provided by the first clock signal line SCK 1.

In order to more intuitively embody the timing arrangement of the gate driving circuit 10 in the present application, please refer to fig. 10 and 11. Fig. 10 is a timing diagram of a gate driving circuit according to an embodiment of the present application, and fig. 11 is a timing diagram of another gate driving circuit according to an embodiment of the present application.

Specifically, in fig. 10, the clock signal waveforms supplied from the first, second, third, and fourth clock signal lines SCK1, SCK2, SCK3, and SCK4 overlap, and may correspond to a case where the adjacent stage shift registers output overlapping scan pulse waveforms. The first clock signal terminal SCK1 in the nth stage shift register 1 is electrically connected to the second clock signal line SCK2, and the second clock signal terminal SCK2 in the nth stage shift register 1 is electrically connected to the fourth clock signal line SCK 4. The specific working stage of the nth shift register can be referred to the previous embodiments, and the present application is not described herein. And, the operation of the n+1st shift register, the n+2nd shift register, and the n+3rd shift register is similar to that of the N-th shift register, and the present application is not described in detail herein. Finally, under the clock signal setting shown in fig. 10, adjacent stage shift registers output scan pulse waveforms that overlap.

In fig. 11, the waveforms of the clock signals supplied from the first clock signal line SCK1, the second clock signal line SCK2, the third clock signal line SCK3, and the fourth clock signal line SCK4 do not overlap, and the waveforms of the scan pulses which do not overlap can be outputted corresponding to the shift registers of adjacent stages. The first clock signal terminal SCK1 in the nth stage shift register 1 is electrically connected to the second clock signal line SCK2, and the second clock signal terminal SCK2 in the nth stage shift register 1 is electrically connected to the fourth clock signal line SCK 4. The specific working stage of the nth shift register can be referred to the previous embodiments, and the present application is not described herein. And, the operation of the n+1st shift register, the n+2nd shift register, and the n+3rd shift register is similar to that of the N-th shift register, and the present application is not described in detail herein. Finally, under the clock signal setting shown in fig. 11, scan pulse waveforms which do not overlap occur in adjacent stage shift register outputs.

Fig. 10 and 11 are only examples of the timing relationship of the clock signals provided by the first clock signal line SCK1, the second clock signal line SCK2, the third clock signal line SCK3, and the fourth clock signal line SCK 4. When the gate driving circuit needs the adjacent stage shift register to output scan pulse waveforms that overlap or do not overlap, the clock signals provided by the first clock signal line SCK1, the second clock signal line SCK2, the third clock signal line SCK3, and the fourth clock signal line SCK4 may have other arrangements, which are not particularly limited in the present application.

Based on the gate driving circuit provided in any of the above embodiments, correspondingly, the present application also provides a display panel, including the gate driving circuit 10 provided in the present application. Referring to fig. 12, fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the application. As shown in fig. 12, the display panel 100 according to the embodiment of the present application may include the gate driving circuit 10 according to any of the above embodiments. The display panel shown in fig. 12 may be an Organic Light-Emitting Diode (OLED) display panel.

Those skilled in the art will appreciate that in other implementations of the application, the display panel may also be a Micro light emitting diode (Micro LED) display panel, a quantum dot display panel, or the like.

The display panel provided by the embodiment of the present application has the beneficial effects of the gate driving circuit 10 provided by the embodiment of the present application, and the specific description of the gate driving circuit 10 in the above embodiments may be referred to in the embodiments, and the description of the embodiment is omitted herein.

Based on the display panel provided by the embodiment, correspondingly, the application also provides a display device comprising the display panel provided by the application. Referring to fig. 13, fig. 13 is a schematic structural diagram of a display device according to an embodiment of the application. Fig. 13 provides a display device 1000 including a display panel 100 according to any of the above embodiments of the present application. The embodiment of fig. 13 is described with respect to the display device 1000 by taking a mobile phone as an example, and it is to be understood that the display device provided in the embodiment of the present application may be a wearable product, a computer, a television, a vehicle-mounted display device, or other display devices having a display function, which is not particularly limited in the present application. The display device provided by the embodiment of the present application has the beneficial effects of the display panel 100 provided by the embodiment of the present application, and the specific description of the display panel 100 in the above embodiments may be referred to in the embodiments, and the description of the embodiment is omitted herein.

It should be understood that the specific structures of the circuits and the cross-sectional structures of the display panels provided in the drawings according to the embodiments of the present application are only examples, and are not intended to limit the present application. In addition, the above embodiments provided by the present application may be combined with each other without contradiction.

It should be understood that, in the present specification, each embodiment is described in an incremental manner, and the same or similar parts between the embodiments are all referred to each other, and each embodiment is mainly described in a different point from other embodiments. These examples are not intended to be exhaustive or to limit the application to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated. The application is limited only by the claims and the full scope and equivalents thereof.

Those skilled in the art will appreciate that the above-described embodiments are exemplary and not limiting. The different technical features presented in the different embodiments may be combined to advantage. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in view of the drawings, the description, and the claims. In the claims, the term "comprising" does not exclude other structures; the amounts refer to "a" and do not exclude a plurality; the terms "first," "second," and the like, are used for designating a name and not for indicating any particular order. Any reference signs in the claims shall not be construed as limiting the scope. The presence of certain features in different dependent claims does not imply that these features cannot be combined to advantage.

Claims

1. The shift register is characterized by comprising an input module, a first control module, a second control module, a third control module, a first output module and a second output module;

the first output module is connected with a first level voltage signal end and a shift register output end and is used for transmitting a first level voltage provided by the first level voltage signal end to the shift register output end under the control of the third node;

the second output module is connected with the second clock signal end and the shift register output end and is used for transmitting a second clock signal provided by the second clock signal end to the shift register output end under the control of the first node.

2. The shift register of claim 1, comprising:

the enabling level pulse width of the first clock signal and the enabling level pulse width of the second clock signal meet a first preset condition, and the adjacent stage shift registers output non-overlapping scanning pulse waveforms; the first clock signal is provided by the first clock signal terminal;

the enabling level pulse width of the first clock signal and the enabling level pulse width of the second clock signal meet a second preset condition, and the adjacent stage shift registers output overlapped scanning pulse waveforms.

3. The shift register of claim 2, comprising:

an enabling level starting time of the first clock signal and an enabling level starting time of the second clock signal are separated by 1/2 clock signal period;

when the enabling level pulse width of the first clock signal and the enabling level pulse width of the second clock signal are smaller than 1/4 clock signal period or equal to 1/4 clock signal period, the adjacent stage shift registers output non-overlapped scanning pulse waveforms;

when the pulse width of the enabling level of the first clock signal and the second clock signal is equal to 1/2 clock signal period, or more than 1/4 clock signal period and less than 1/2 clock signal period, the adjacent stage shift registers output overlapped scanning pulse waveforms;

Preferably, when the pulse widths of the enabling level of the first clock signal and the second clock signal are 1/4 clock signal period, the adjacent stage shift registers output non-overlapping scanning pulse waveforms;

when the pulse widths of the enabling level of the first clock signal and the second clock signal are 1/2 clock signal period, the adjacent stage shift registers output overlapped scanning pulse waveforms;

preferably, the enable level pulse widths of the first clock signal and the second clock signal are the same, and the clock signal periods of the first clock signal and the second clock signal are the same;

preferably, 1/4 clock signal period is equal to the scanning time of one row of pixel circuits;

preferably, the enable level pulse width of the initial input signal provided by the shift register input terminal is the same as the enable level pulse width of the second clock signal, and the enable level phase of the initial input signal provided by the shift register input terminal leads one enable level phase of the second clock signal by 1/4 clock signal period.

4. The shift register of claim 1, comprising:

the control end and the first end of the input module are electrically connected with the output end of the shift register, and the second end of the input module is electrically connected with the first node;

The first control module is electrically connected with the first clock signal end, the second control end of the first control module is electrically connected with the input end of the shift register, the first input end of the first control module is electrically connected with the second level voltage signal end, the second input end of the first control module is electrically connected with the first clock signal end, and the output end of the first control module is electrically connected with the third node;

the first control end of the second control module is electrically connected with the third node, the second control end of the second control module is electrically connected with the second clock signal end, the first end of the second control module is electrically connected with the first level voltage signal end, and the second end of the second control module is electrically connected with the second node;

the control end of the third control module is electrically connected with the output end of the post-M-stage shift register, the first end of the third control module is electrically connected with the first level voltage signal end, and the second end of the third control module is electrically connected with the first node;

the control end of the first output module is electrically connected with the third node, the first end of the first output module is electrically connected with the first level voltage signal end, and the second end of the first output module is electrically connected with the output end of the shift register;

The control end of the second output module is electrically connected with the second node, the first end of the second output module is electrically connected with the output end of the shift register, and the second end of the second output module is electrically connected with the second clock signal end.

5. The shift register of claim 1, wherein the input module comprises a first transistor, the second control module comprises a second transistor and a third transistor, the first control module comprises a fourth transistor and a fifth transistor, the first output module comprises a sixth transistor, the second output module comprises a seventh transistor, and the third control module comprises an eighth transistor;

the control end and the first end of the first transistor are electrically connected with the input end of the shift register, and the second end of the first transistor is electrically connected with the first node;

the control end of the second transistor is electrically connected with the second clock signal end, the first end of the second transistor is electrically connected with the second end of the third transistor, and the second end of the second transistor is electrically connected with the first node;

the control end of the third transistor is electrically connected with the third node, and the first end of the third transistor is electrically connected with the first level voltage signal end;

The control end of the fourth transistor is electrically connected with the input end of the shift register, the first end of the fourth transistor is electrically connected with the third node, and the second end of the fourth transistor is electrically connected with the second clock signal end;

the control end of the fifth transistor is electrically connected with the second clock signal end, the first end of the fifth transistor is electrically connected with the second level voltage signal end, and the second end of the fifth transistor is electrically connected with the third node;

the control end of the sixth transistor is electrically connected with the third node, the first end of the sixth transistor is electrically connected with the first level voltage signal end, and the second end of the sixth transistor is electrically connected with the output end of the shift register;

the control end of the seventh transistor is electrically connected with the second node, the first end of the seventh transistor is electrically connected with the output end of the shift register, and the second end of the seventh transistor is electrically connected with the second clock signal end;

the control end of the eighth transistor is electrically connected with the output end of the post-M-stage shift register, the first end of the eighth transistor is electrically connected with the first node, and the second end of the eighth transistor is electrically connected with the first level voltage signal end;

Preferably, M has a value of 2;

preferably, the shift register further comprises a first storage module, a second storage module and a first switch module; the first end of the first storage module is electrically connected with the first level voltage signal end, and the second end of the first storage module is electrically connected with the third node and is used for maintaining the node potential stability of the third node;

the first end of the second storage module is electrically connected with the output end of the shift register, and the second end of the second storage module is electrically connected with the second node and is used for bootstrapping and maintaining the node potential of the second node;

the control end of the first switch module is electrically connected with the second level voltage signal end, the first end of the first switch module is electrically connected with the first node, and the second end of the first switch module is electrically connected with the second node;

preferably, the first memory module includes a first capacitor, the second memory module includes a second capacitor, and the first switch module includes a ninth transistor;

a first pole of the first capacitor is electrically connected with the first level voltage signal end, and a second pole of the first capacitor is electrically connected with the third node;

The first end of the second capacitor is electrically connected with the output end of the shift register, and the second end of the second capacitor is electrically connected with the second node;

the control end of the ninth transistor is electrically connected with the second level voltage signal end, the first end of the ninth transistor is electrically connected with the first node, and the second end of the ninth transistor is electrically connected with the second node.

6. The shift register of claim 4, wherein the first level voltage is a disable level and the second level voltage is an enable level;

if the shift registers of adjacent stages output overlapped scanning pulse waveforms, in a first stage, the input end of the shift register provides a non-enabling level, the first clock signal end provides an enabling level, and the second clock signal end provides a non-enabling level; the first control module is conducted to transmit the second level voltage provided by the second level voltage signal end to the third node, and the first output module is conducted to transmit the non-enabling level provided by the first level voltage signal end to the output end of the shift register;

in a second stage, the shift register input terminal provides an enable level, the first clock signal terminal provides an enable level, and the second clock signal terminal provides a disable level; the first control module is conducted, and the third node is an enabling level; the first output module responds to the conduction of the enabling level of the third node and transmits the enabling level of the first level voltage signal end to the output end of the shift register; the input module is conducted and transmits the enabling level provided by the input end of the shift register to the first node; the second output module responds to the conduction of the enabling level of the second node and transmits the non-enabling level provided by the second clock signal end to the output end of the shift register;

In a third stage, the shift register input provides an enable level, the first clock signal terminal provides a disable level, and the second clock signal terminal provides an enable level; the node potential of the second node is lower than the enabling level; the second output module is conducted and transmits the enabling level provided by the second clock signal end to the output end of the shift register;

in a fourth stage, the shift register input provides a disable level, the first clock signal provides a disable level, and the second clock signal provides an enable level; the input module is turned off, and the second node maintains an enabling level; the second output module is conducted and transmits the enabling level provided by the second clock signal end to the output end of the shift register;

in a fifth stage, the shift register input provides a disable level, the first clock signal provides an enable level, and the second clock signal provides a disable level; the first control module is conducted and transmits the second level voltage provided by the second level voltage signal end to the third node; the first output module is conducted and transmits the non-enabling level provided by the first level voltage signal end to the output end of the shift register;

In a sixth stage, the shift register output provides a disable level; the first control module is turned off, and the third node maintains an enable level; the first output module is conducted and transmits the non-enabling level provided by the first level voltage signal end to the output end of the shift register;

or if the adjacent stage shift registers output non-overlapping scan pulse waveforms, in the first stage, the shift register input end provides a non-enabling level, the first clock signal end provides an enabling level, and the second clock signal end provides a non-enabling level; the first control module is conducted to transmit the second level voltage provided by the second level voltage signal end to the third node, and the first output module is conducted to transmit the non-enabling level provided by the first level voltage signal end to the output end of the shift register;

in a second stage, the shift register input terminal provides an enable level, the first clock signal terminal provides a disable level, and the second clock signal terminal provides a disable level; the input module is conducted and transmits the enabling level provided by the input end of the shift register to the first node; the second output module responds to the conduction of the enabling level of the second node and transmits the non-enabling level provided by the second clock signal end to the output end of the shift register;

In a third stage, the shift register input terminal provides a disable level, the first clock signal terminal provides a disable level, and the second clock signal terminal provides an enable level; the node potential of the second node is lower than the enabling level; the second output module is conducted and transmits the enabling level provided by the second clock signal end to the output end of the shift register;

in a fourth stage, the shift register input provides a disable level, the first clock signal provides a disable level, and the second clock signal provides a disable level; the second node maintains an enable level; the second output module is conducted and transmits the non-enabling level provided by the second clock signal end to the output end of the shift register;

In a sixth stage, the shift register output provides a disable level; the first control module is turned off, and the third node maintains an enable level; the first output module is conducted and transmits the non-enabling level provided by the first level voltage signal end to the output end of the shift register.

7. A gate driving circuit comprising a plurality of shift registers according to any one of claims 1 to 6, wherein a plurality of the shift registers are cascade-connected.

8. The gate driving circuit according to claim 7, wherein the first clock signal and the second clock signal in the n+1th stage shift register each have a predetermined phase difference from the first clock signal and the second clock signal in the N-th stage shift register, N being a positive integer;

preferably, the gate driving circuit includes a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line;

the clock signals provided by the first clock signal line, the second clock signal line, the third clock signal line and the fourth clock signal line are sequentially separated by 1/4 clock signal period;

A first clock signal end in the N-th shift register is electrically connected with the second clock signal line, and a second clock signal end in the N-th shift register is electrically connected with the fourth clock signal line;

a first clock signal end in the N+1th stage shift register is electrically connected with the third clock signal line, and a second clock signal end in the N+1th stage shift register is electrically connected with the first clock signal line;

a first clock signal end in the N+2-stage shift register is electrically connected with the fourth clock signal line, and a second clock signal end in the N+2-stage shift register is electrically connected with the second clock signal line;

a first clock signal end in the N+3 stage shift register is electrically connected with the first clock signal line, and a second clock signal end in the N+3 stage shift register is electrically connected with the third clock signal line;

preferably, clock signal periods of clock signals provided by the first clock signal line, the second clock signal line, the third clock signal line and the fourth clock signal line are identical;

preferably, the shift register output end of the N-1 stage shift register is multiplexed as the shift register input end of the N stage shift register;

The shift register output end of the N-th shift register is multiplexed into the shift register input end of the (n+1) -th shift register;

preferably, the enable level stage of the signal outputted from the shift register output terminal of the N-1 th stage shift register coincides with one enable level stage of the clock signal supplied from the first clock signal line.

9. A display panel comprising the shift register of claim 7 or 8.

10. A display device comprising the display panel according to claim 9.