CN102044216A - LED display system and LED driving circuits - Google Patents
LED display system and LED driving circuits Download PDFInfo
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- CN102044216A CN102044216A CN2010102815511A CN201010281551A CN102044216A CN 102044216 A CN102044216 A CN 102044216A CN 2010102815511 A CN2010102815511 A CN 2010102815511A CN 201010281551 A CN201010281551 A CN 201010281551A CN 102044216 A CN102044216 A CN 102044216A
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Abstract
The invention provides a light emitting diode (LED) display system. An LED controller is connected in series with LED driving circuits in a plurality of LED unit plates in turn; control signals generated by a group of output ends of the LED controller are acquired by a group of input ends of a first-level LED driving circuit and transmitted to a group of input ends of a next-level LED driving circuit through a group of output ends of the first-level LED driving circuit in turn until all the LED driving circuits receive the control signals in turn and perform corresponding operation; each LED driving circuit comprises two or more output register groups; and the group of output ends of the LED controller send various control signals, so that (1) values of the two or more output register groups of each of the LED driving circuits which are connected in series in turn on the LED unit plates are set, or (2) each LED driving circuit outputs the control signals to an LED driving output end through a certain output register group. The LED display system realizes display switching and data latch asynchronization.
Description
Technical field
The present invention relates to LED display technique field.
Background technology
The extensive at present LED display system that exists as shown in Figure 1, comprises a led controller and several LED cell boards that are connected in series successively:
The LED cell board comprises BUFFER circuit and several led drive circuits that are connected in series successively (11) of an enhancing signal driving force;
One group of output signal that led controller sends comprises clock signal output CLKI, data-signal output DIN, latch signal output LATI and enable signal output ENI;
The clock signal that led controller sends, latch signal and enable signal drive corresponding clock signals input end, latch signal input end and the enable signal input end that offers all led drive circuits in this LED cell board after the enhancing through the BUFFER circuit of the LED cell board of each serial connection successively;
The data-signal that led controller sends offers the BUFFER circuit of first order LED cell board, after driving enhancing, export to first led drive circuit data-signal input end of first order LED cell board, and under clock signal control, export to the data-signal input end of next led drive circuit by the internal displacement register of first led drive circuit, transmit successively, last led drive circuit outputs to the BUFFER circuit of next stage LED cell board; Data-signal transmits successively through each LED cell board, and upper level LED cell board outputs to the BUFFER circuit of LED cell board at the corresponding levels, and last led drive circuit of LED cell board at the corresponding levels outputs to the BUFFER circuit of next stage LED cell board; Last led drive circuit output of last LED cell board is unsettled.
The LED cell board also comprises several LED lamps, and each drive output of led drive circuit connects LED lamp one end respectively, and the LED lamp other end connects power vd D, when the drive end of led drive circuit has drop-down continuous current, is effective demonstration time, and the LED lamp is lighted; During LED display system acceptance criteria vision signal, the field frequency of video standard signal can be 50HZ or other, as field frequency is 50HZ, and then the LED lamp of a pixel in each corresponding vision signal need the gray scale according to this pixel obtain the corresponding effectively demonstration time in a field time 20ms.
Traditional led drive circuit inner structure as shown in Figure 2, each drive end of led drive circuit has or not drop-down continuous current controlled by output register and enable signal, the output register class value latchs from shift register group.
Be that example describes with following LED display system below: one group of output of a led controller is connected in series 8 LED cell boards successively, comprise 2 led drive circuits on the every LED cell board, each led drive circuit comprises 16 grades of shift registers, then to post device be 256 in Chuan Jie displacement, and the LED drive output adds up to 256, and LED lamp gray shade scale is 4096 grades, and promptly gray scale is 12, and the gray-scale value lowest order is corresponding, and effectively the demonstration time is a clock period; With two-dimensional array D[0:255] 12 gray-scale values of 256 LED drive output of [0:11] expression LED lamp that will drive, as D[0] [0:11] promptly represent 12 gray-scale values of the LED lamp that the 1st LED drive output OUT will drive, as D[0] [0] promptly represent the lowest-order values of 12 gray scales of the LED lamp that the 1st LED drive output OUT will drive.
The control signal that led controller sends as shown in Figure 3.T represents the cycle of CLKI, and T_FRAM represents 12 gray-scale value required times of 256 LED drive output of run-down, and a field time is made up of a plurality of T_FRAM; The LED lamp of a pixel in each corresponding vision signal need the gray scale according to this pixel obtain the corresponding effectively demonstration time in a T_FRAM.
, need 12 times altogether and show and displacement in the time at as shown in Figure 3 T_FRAM, the demonstration time need be guaranteed next time the video data required effective shift time that is shifted at every turn; Effectively shift time is 256T, provides to the 256T before the led drive circuit latch signal, and when latch signal arrived, shift register value was latched into output register; After each displacement, a certain bit data of gray scale is latched into output register, the enable signal corresponding with this, be shifted next time latch before this effective demonstration time of each drive end be: the effective time of a certain place value * enable signal of gray scale; High 3 D[0:255 of gray scale] [9:11] corresponding enable signal effective time is greater than the required effective shift time 256T that once is shifted, be respectively 2*256T, 4*256T, 8*256T, gray scale is hanged down 9 D[0:255] [0:8] corresponding enable signal is not more than 256T effective time, enable signal need be filled ineffective time and satisfy the required effective shift time 256T that once is shifted, so T_FRAM is about 23*256T; In current T_FRAM, a certain i holds the brightness of a LED lamp that drives relevant with its effective demonstration time in 256 LED drive output, is calculated as follows:
D[i][0]*1T+D[i][1]*2T+D[i][2]*4T+D[i][3]*8T+D[i][4]*16T+D[i][5]*32T+D[i][6]*64T+D[i][7]*128T+D[i][8]*256T+D[i][9]*2*256T+D[i][10]*4*256T+D[i][11]*8*256T。
If a LED lamp that needs the i end to drive is the brightest, then D[i] [0:11] be complete 1, according to above-mentioned formula, its effectively the demonstration time be (16*256-1) T, less than the 23*256T of T_FRAM; T_FRAM means that greatly a field time can only be made up of less T_FRAM, and display quality is poor; The brightest effective demonstration time means the luminance loss less than T_FRAM, and the luminance loss is about 30% in this example.
Also can do following the variation to example: the first, reduce the shift register number, promptly reduce once effectively shift time, but this means that the screen of control same pixel need increase the number of led controller, will increase system cost like this; The second, increase the corresponding effectively demonstration time of gray-scale value lowest order, promptly reduce in the gray scale enable signal and need fill the figure place of ineffective time, strengthened the ratio of the brightest effective demonstration time and T_FRAM, the luminance loss diminishes, but has strengthened T_FRAM, reduces display quality; The 3rd, shorten the corresponding effectively demonstration time of gray-scale value lowest order, can reduce T_FRAM, need fill the figure place of ineffective time but increased in the gray scale enable signal, reduced the ratio of the brightest effective demonstration time and T_FRAM, promptly strengthen the luminance loss.
For better display effect, can also be with D[0:255] 12 gray-scale values of [0:11] on average sort, as shown in Figure 4, corresponding enable signal effective time is greater than high 3 D[0:255 of gray scale of the required effective shift time that once is shifted] [9:11], split into 2 respectively, 4, show and displacement for 8 times, gray scale is hanged down 9 D[0:255] [0:8] still 1 demonstration and displacement, needing 23 times altogether shows and displacement, as in the following order: D[0:255] [11], D[0:255] [0], D[0:255] [10], D[0:255] [11], D[0:255] [4], D[0:255] [9], D[0:255] [11], D[0:255] [2], D[0:255] [10], D[0:255] [11], D[0:255] [6], D[0:255] [8], D[0:255] [11], D[0:255] [1], D[0:255] [10], D[0:255] [11], D[0:255] [5], D[0:255] [9], D[0:255] [11], D[0:255] [3], D[0:255] [10], D[0:255] [11], D[0:255] [7], but brightness calculation is constant, and same problem is still arranged.
The main cause of contradiction is to have only an output register group in the led drive circuit between existing mode cost, display quality, the brightness, show to switch can only with data shift after latch synchronously, if led drive circuit has a plurality of output register groups, and show to switch can with data shift after latch asynchronously, then can solve above contradiction.
Summary of the invention
The present invention is intended to solve the deficiencies in the prior art, provide a kind of can realize showing switch and data shift after latch asynchronous LED display system.
The invention allows for a kind of led drive circuit.
The LED display system comprises a led controller and several LED cell boards;
Described led controller comprises as lower port: one group of output terminal;
Described LED cell board comprises several led drive circuits;
Described led drive circuit comprises as lower port: one group of input end, one group of output terminal and one group of LED drive output;
Described LED display system, led drive circuit in led controller and several LED cell boards is connected in series successively, the control signal that one group of output terminal of led controller produces obtains and passes to by one group of output terminal of first order led drive circuit one group of input end of next stage led drive circuit through one group of input end of first order led drive circuit, transmit successively, all led drive circuits all receive control signal successively and carry out corresponding operating.
Described led drive circuit comprises two or more output register groups;
Described LED display system, one group of output terminal of led controller sends various control signals, can be to two or more output register group values of putting of led drive circuit on the LED cell board that is connected in series successively, also can make led drive circuit select a certain output register group to output to the LED drive output, realize the LED Display System Function; Various control signals produce successively, and it can be asynchronous that output register group value of putting and selection output to the LED drive output.
Described LED display system, one group of output terminal of led controller sends various control signals and comprises following instruction type:
IR_DATA (i): to i output register group value of putting in two or more of led drive circuit;
IR_SEL (i): i output register group value of putting outputs to the LED drive output in two or more of selection led drive circuit.
Described LED display system, one group of output terminal of led controller comprises: clock signal output terminal CLKI, data-signal output terminal DIN, latch signal output terminal LATI and enable signal output terminal ENI;
Described LED display system, one group of output terminal of led controller sends an a kind of instruction of control signal, form by clock signal, data-signal, latch signal and enable signal cooperation, instruction begins with the latch signal low level, after being high level, finishes with the latch signal low level again latch signal, the end of this instruction can be the beginning of next bar instruction, between continuous two instructions is low level, its time length can be any, and rising edge clock signal quantity showed its instruction type when latch signal was high level; Article one, under the instruction, described led drive circuit receive clock signal, data-signal, latch signal and enable signal carry out corresponding operating, and described led drive circuit receives the corresponding data of data-signal;
Described IR_DATA (i): the LED drive output quantity of the driving circuit of serial connection is M, M is greater than the number of output register group in the led drive circuit, and rising edge clock signal quantity is M+i-1 during the latch signal high level, when latch signal when high level finishes to become low level, data-signal is latched into i output register group by the corresponding data of clock signal;
Described IR_SEL (i): rising edge clock signal quantity is i during the latch signal high level, and i output register group value of putting outputs to the LED drive output in two or more output register groups of selection led drive circuit.
Beneficial effect of the present invention is: the LED display system and the led drive circuit that adopt the present invention to propose, led drive circuit has two or more output register groups, latching behind demonstration switching and the data shift can be asynchronous, taken into account contradiction between display quality, the brightness, and new LED display system cost increases few.
Description of drawings
Fig. 1 is traditional LED display system architectures figure
Fig. 2 is traditional led drive circuit structural drawing
The signal timing diagram of the control tradition led drive circuit that Fig. 3 sends for led controller
The signal timing diagram of control tradition led drive circuit after average ordering that Fig. 4 sends for led controller
Fig. 5 is a led drive circuit cut-away view of the present invention
The signal timing diagram of the control led drive circuit of the present invention that Fig. 6 sends for led controller
Embodiment
Below in conjunction with accompanying drawing content of the present invention is further specified.
The led drive circuit that the present invention proposes, as shown in Figure 5, comprise as lower port: input end of clock CLK, output enable input end EN, data latching input end LAT, shifted data input end DIN, shifted data output terminal DOUT and 16 LED drive output OUT, and a control module and 16 LED driver modules;
The control module of described led drive circuit comprises as lower port: input end of clock CLK, data latching input end LAT, selector switch control output end CTRL0, the first output register control output end CTRL1, the second output register control output end CTRL2;
Each LED driver module of described led drive circuit comprises as lower port: input end of clock CLK, output enable input end EN, data latching input end LAT, selector switch control input end CTRL0, the first output register control input end CTRL1, the second output register control input end CTRL2, data input pin D, data output end Q and LED drive output OUT, and shift register, first output register, second output register, No. two selector switchs and constant current output module; The selector switch control input end CTRL0 of all LED driver modules, the first output register control input end CTRL1 and the second output register control input end CTRL2 be selector switch control output end CTRL0, the first output register control output end CTRL1 and the second output register control output end CTRL2 of link control module respectively; The data input pin D of first LED driver module connects the shifted data input end DIN of the led drive circuit of input shifted data signal, the data output end Q of first order LED driver module connects the data input pin D of next stage LED driver module, by that analogy, the data output end Q of previous stage LED driver module connects the data input pin D of back one-level LED driver module, and the data output end Q of the 16th grade of LED driver module connects the shifted data output terminal DOUT of led drive circuit; The LED drive output OUT of 16 LED driver modules connects 16 LED drive output OUT of led drive circuit respectively;
Shift register, first output register and second output register in the LED driver module of described led drive circuit, structure is identical, comprise as lower port: input end of clock CLK, control input end TR, data input pin D and data output end Q, when control input end TR is low level, data output end Q kept initial value when input end of clock CLK was rising edge, when control input end TR is high level, when data output end CLK is rising edge with the data latching of data input pin D to data output end Q; The control input end TR of shift register, first output register and second output register is connected data latching input end LAT, the first output register control input end CTRL1 and the second output register control input end CTRL2 of LED driver module respectively; The data input pin D of first output register and second output register is connected the data output end Q of shift register;
No. two selector switchs in the LED driver module of described led drive circuit, comprise as lower port: select input end S, data input pin A, data input pin B and data output end Y, when selecting input end S to be high level, the data of data output end Y output data input end A, when selecting input end S to be low level, the data of data output end Y output data input end B; The selection input end S of No. two selector switchs connects the selector switch control input end CTRL0 of LED driver module, and the data input pin A of No. two selector switchs and data input pin B are connected the data output end Q of first output register and second output register respectively;
Constant current output module in the LED driver module of described led drive circuit comprises as lower port: output enable input end EN, data input pin Y and LED drive output OUT; When output enable input end EN is high level, LED drive output OUT does not have constant current output, when output enable input end EN is low level, data input pin Y be high level then LED drive output OUT have constant current output, data input pin Y be low level then LED drive output OUT do not have constant current output; The data input pin Y of constant current output module connects the data output end Y of No. two selector switchs.
Shift register in 16 LED driver modules of described led drive circuit is formed shift register group, first output register in 16 LED driver modules is formed the first output register group, and second output register in 16 LED driver modules is formed the second output register group.
The LED display system that the present invention proposes comprises: a led controller and several LED cell boards that are connected in series successively; The LED cell board comprises: the BUFFER circuit of an enhancing signal driving force and several described led drive circuits; With legacy system shown in Figure 1 relatively, described led drive circuit is different with led drive circuit (11) function in the legacy system, but the pin unanimity can directly substitute, only a need controller send new control signal.
Be that example describes with following LED display system below: 8 LED cell boards of one group of output control of a led controller, comprise 2 described led drive circuits on the every LED cell board, each led drive circuit comprises 16 grades of shift register group, then Chuan Jie shift register is 256, LED drive output OUT adds up to 256, and LED lamp gray shade scale is 4096 grades, and promptly gray scale is 12, and the gray-scale value lowest order is corresponding, and effectively the demonstration time is a clock period; With two-dimensional array D[0:255] 12 gray-scale values of 256 LED drive output OUT of [0:11] expression LED lamp that will drive.
The control signal that led controller sends as shown in Figure 6.T represents the cycle of CLKI, and T_FRAM represents a gray scale required time of 256 LED drive output of run-down, and a field time is made up of a plurality of T_FRAM.
In time, the control signal that led controller sends as shown in Figure 6 is made up of instruction at T_FRAM; Article one, instruction is made up of clock signal, data-signal, latch signal and enable signal cooperation; Article one, instruction begins with the latch signal low level, finishes with the latch signal low level after latch signal is high level again; The end of this instruction can be the beginning of next bar instruction, is low level between continuous two instructions, and its time length can be any; Rising edge clock signal quantity showed its instruction type when latch signal was high level; Article one, under the instruction, control module receive clock signal, data-signal, latch signal and the enable signal of described led drive circuit carry out corresponding operating, and the shift register group of received data-signal of described led drive circuit moves into data;
Described instruction includes but not limited to following several:
IR_DATA (1): under the instruction, during the latch signal high level, rising edge clock signal quantity is 256, when latch signal when high level finishes to become low level, the control module of led drive circuit produces the CTRL1 high level of a clock, will be moved into the data latching of shift register to first output register from data-signal;
IR_DATA (2): under the instruction, during the latch signal high level, rising edge clock signal quantity is 257, when latch signal when high level finishes to become low level, the control module of led drive circuit produces the CTRL2 high level of a clock, will be moved into the data latching of shift register to second output register from data-signal;
IR_SEL (1): under the instruction, during the latch signal high level, rising edge clock signal quantity is 1, when latch signal when high level finishes to become low level, the CTRL0 that the control module of led drive circuit produces is changed to high level, selects first output register group value of putting of led drive circuit to output to the LED drive output;
IR_SEL (2): under the instruction, during the latch signal high level, rising edge clock signal quantity is 2, when latch signal when high level finishes to become low level, the CTRL0 that the control module of led drive circuit produces is changed to low level, selects second output register group value of putting of led drive circuit to output to the LED drive output;
In the control signal as shown in Figure 6 that led controller sends, instruction order and function declaration are as follows in the T_FRAM:
1.IR_SEL (1): accept former frame, select the first output register group value of putting D[0:255] [9] output to the LED drive output;
2.IR_DATA (1): with D[0:255] [11] insert each led drive circuit first output register;
3.IR_SEL (1): select the first output register group value of putting D[0:255] [11] output to the LED drive output;
4.IR_DATA (2): with D[0:255] [0] inserts each led drive circuit second output register;
5.IR_SEL (2): select the second output register group value of putting D[0:255] [0] outputs to the LED drive output;
6.IR_SEL (1): select the first output register group value of putting D[0:255] [11] output to the LED drive output;
7.IR_DATA (2): with D[0:255] [1] inserts each led drive circuit second output register;
8.IR_SEL (2): select the second output register group value of putting D[0:255] [1] outputs to the LED drive output;
9.IR_SEL (1): select the first output register group value of putting D[0:255] [11] output to the LED drive output;
10.IR_DATA (2): with D[0:255] [2] insert each led drive circuit second output register;
11.IR_SEL (2): select the second output register group value of putting D[0:255] [2] output to the LED drive output;
12.IR_SEL (1): select the first output register group value of putting D[0:255] [11] output to the LED drive output;
13.IR_DATA (2): with D[0:255] [3] insert each led drive circuit second output register;
14.IR_SEL (2): select the second output register group value of putting D[0:255] [3] output to the LED drive output;
15.IR_SEL (1): select the first output register group value of putting D[0:255] [11] output to the LED drive output;
16.IR_DATA (2): with D[0:255] [4] insert each led drive circuit second output register;
17.IR_SEL (2): select the second output register group value of putting D[0:255] [4] output to the LED drive output;
18.IR_SEL (1): select the first output register group value of putting D[0:255] [11] output to the LED drive output;
19.IR_DATA (2): with D[0:255] [5] insert each led drive circuit second output register;
20.IR_SEL (2): select the second output register group value of putting D[0:255] [5] output to the LED drive output;
21.IR_SEL (1): select the first output register group value of putting D[0:255] [11] output to the LED drive output;
22.IR_DATA (2): with D[0:255] [6] insert each led drive circuit second output register;
23.IR_SEL (2): select the second output register group value of putting D[0:255] [6] output to the LED drive output;
24.IR_SEL (1): select the first output register group value of putting D[0:255] [11] output to the LED drive output;
25.IR_DATA (2): with D[0:255] [10] insert each led drive circuit second output register;
26.IR_SEL (2): select the second output register group value of putting D[0:255] [10] output to the LED drive output;
27.IR_DATA (1): with D[0:255] [7] insert each led drive circuit first output register;
28.IR_SEL (1): select the first output register group value of putting D[0:255] [7] output to the LED drive output;
29.IR_SEL (2): select the second output register group value of putting D[0:255] [10] output to the LED drive output;
30.IR_DATA (1): with D[0:255] [8] insert each led drive circuit first output register;
31.IR_SEL (1): select the first output register group value of putting D[0:255] [8] output to the LED drive output;
32.IR_SEL (2): select the second output register group value of putting D[0:255] [10] output to the LED drive output;
33.IR_DATA (1): with D[0:255] [9] insert each led drive circuit first output register;
34.IR_SEL (1): select the first output register group value of putting D[0:255] [9] output to the LED drive output;
35.IR_SEL (2): select the second output register group value of putting D[0:255] [10] output to the LED drive output;
In the above-mentioned instruction order, an IR SEL (i) instruction expression once shows variation, the demonstration time of a certain gray level bit of time representation between adjacent twice IR_SEL (i) instruction, can satisfy a certain gray level bit required demonstration time to the control that is used for enable signal effective time between adjacent twice IR_SEL (i) instruction, when demonstration time between adjacent twice IR_SEL (i) instruction during greater than effective shift time, can carry out the value of putting of output register group simultaneously, when time between adjacent twice IR_SEL (i) instruction during less than effective shift time, not to the output register group value of putting.
In the control signal as shown in Figure 6 that described led controller sends, adjacent twice IR_SEL (i) instructs when identical, and a back IR_SEL (i) instruction can also be removed, and does not promptly need to reselect the output register group that outputs to the LED drive output.
By above-mentioned instruction order, T_FRAM be (77+16*256-1) T, in 256 LED drive output the brightness of a LED lamp of i LED drive output driving relevant with its effective demonstration time, be calculated as follows:
D[i][0]*1T+D[i][1]*2T+D[i][2]*4T+D[i][3]*8T+D[i][4]*16T+D[i][5]*32T+D[i][6]*64T+D[i][7]*128T+D[i][8]*256T+D[i][9]*2*256T+D[i][10]*4*256T+D[i][11]*8*256T。
If a LED lamp that needs the i end to drive is the brightest, then D[i] [0:11] be complete 1, according to above-mentioned formula, effectively the demonstration time is (16*256-1) T to the LED drive output, consistent with traditional scheme, T_FRAM is much smaller than traditional scheme, and the luminance loss is also much smaller than traditional scheme.
Described led drive circuit, the first output register group and the second output register group exist simultaneously, can make to latch respectively behind data presentation and the data shift two output register groups are operated, demonstration can be selected front latched data, not necessarily needs to wait for firm displacement back latched data, thereby can make enable signal effective in the most of the time, reduced T_FRAM, improve display quality, reduce the luminance loss again, and cost increases few.
What should be understood that is, the foregoing description is just to explanation of the present invention, rather than limitation of the present invention, and any innovation and creation that do not exceed in the connotation scope of the present invention all fall within the protection domain of the present invention.
Claims (5)
1.LED display system comprises a led controller and several LED cell boards:
Described led controller comprises as lower port: one group of output terminal;
Described LED cell board comprises several led drive circuits;
Described led drive circuit comprises as lower port: one group of input end, one group of output terminal and one group of LED drive output; Described LED display system, led drive circuit in led controller and several LED cell boards is connected in series successively, the control signal that one group of output terminal of led controller produces obtains and passes to by one group of output terminal of first order led drive circuit one group of input end of next stage led drive circuit through one group of input end of first order led drive circuit, transmit successively, all led drive circuits all receive control signal successively and carry out corresponding operating;
It is characterized in that described led drive circuit comprises two or more output register groups;
One group of output terminal of described led controller sends various control signals, realize: (1) is to two or more output register group values of putting of led drive circuit on the LED cell board that is connected in series successively, or (2) make led drive circuit select a certain output register group to output to the LED drive output, realizes the LED Display System Function;
Described various control signal produces successively, and it can be asynchronous that output register group value of putting and selection output to the LED drive output.
2. LED display system according to claim 1, the one group of output terminal that it is characterized in that described led controller sends various control signals and comprises following instruction type:
IR_DATA (i): to i output register group value of putting in two or more of led drive circuit;
IR_SEL (i): i output register group value of putting outputs to the LED drive output in two or more of selection led drive circuit.
3. as LED display system as described in the claim 2, the one group of output terminal that it is characterized in that described led controller comprises: clock signal output terminal CLKI sends clock signal, data-signal output terminal DIN sends data-signal, latch signal output terminal LATI sends latch signal and enable signal output terminal ENI sends enable signal, one group of output terminal of led controller sends an a kind of instruction of control signal, by clock signal, data-signal, latch signal and enable signal cooperate to be formed, instruction begins with the latch signal low level, after being high level, finishes with the latch signal low level again latch signal, the end of this instruction can be the beginning of next bar instruction, between continuous two instructions is low level, its time length can be any, and rising edge clock signal quantity showed its instruction type when latch signal was high level; Article one, under the instruction, described led drive circuit receive clock signal, data-signal, latch signal and enable signal carry out corresponding operating, and described led drive circuit receives the corresponding data of data-signal.
Described IR_DATA (i): the LED drive output quantity of the driving circuit of serial connection is M, M is greater than the number of output register group in the led drive circuit, and rising edge clock signal quantity is M+i-1 during the latch signal high level, when latch signal when high level finishes to become low level, data-signal is latched into i output register group by the corresponding data of clock signal;
Described IR_SEL (i): rising edge clock signal quantity is i during the latch signal high level, and i output register group value of putting outputs to the LED drive output in two or more output register groups of selection led drive circuit.
4. led drive circuit according to claim 1, it is characterized in that comprising as lower port: input end of clock, output enable input end, data latching input end, shifted data input end, shifted data output terminal and N LED drive output, and a control module and N LED driver module:
The control module of described led drive circuit comprises as lower port: input end of clock, data latching input end, selector switch control output end, a L output register control output end;
Each LED driver module of described led drive circuit comprises as lower port: input end of clock, output enable input end, data latching input end, selector switch control input end, a L output register control input end, data input pin, data output end and LED drive output, and shift register, a L output register, MUX and constant current output module; The selector switch control input end of all LED driver modules, a L output register control input end be selector switch control output end, a L output register control output end of link control module respectively; The data input pin of first LED driver module connects the shifted data input end of the led drive circuit of input shifted data signal, the data output end of first order LED driver module connects the data input pin of next stage LED driver module, by that analogy, the data output end of previous stage LED driver module connects the data input pin of back one-level LED driver module, and the data output end of N level LED driver module connects the shifted data output terminal of led drive circuit; The LED drive output of N LED driver module connects N LED drive output of led drive circuit respectively;
Shift register, a L output register comprise as lower port: input end of clock, control input end, data input pin and data output end in the LED driver module; The control input end of shift register, a L output register connects data latching input end, a L output register control input end of LED driver module respectively; The data input pin of L output register connects the data output end of shift register;
MUX in the LED driver module of described led drive circuit comprises as lower port: select input end, L data input end and data output end, under the control of selecting side, MUX is selected in L data input end of output; The selection input end of MUX connects the selector switch control input end of LED driver module, and the L of MUX data input end connects the data output end of L output register respectively;
Constant current output module in the LED driver module of described led drive circuit comprises as lower port: output enable input end, data input pin and LED drive output; The data input pin of constant current output module connects the data output end of MUX.
5.LED driving circuit, it is characterized in that comprising as lower port: input end of clock, output enable input end, data latching input end, shifted data input end, shifted data output terminal and N LED drive output, and a control module and N LED driver module:
The control module of described led drive circuit comprises as lower port: input end of clock, data latching input end, selector switch control output end, a L output register control output end;
Each LED driver module of described led drive circuit comprises as lower port: input end of clock, output enable input end, data latching input end, selector switch control input end, a L output register control input end, data input pin, data output end and LED drive output, and shift register, a L output register, MUX and constant current output module; The selector switch control input end of all LED driver modules, a L output register control input end be selector switch control output end, a L output register control output end of link control module respectively; The data input pin of first LED driver module connects the shifted data input end of the led drive circuit of input shifted data signal, the data output end of first order LED driver module connects the data input pin of next stage LED driver module, by that analogy, the data output end of previous stage LED driver module connects the data input pin of back one-level LED driver module, and the data output end of N level LED driver module connects the shifted data output terminal of led drive circuit; The LED drive output of N LED driver module connects N LED drive output of led drive circuit respectively;
Shift register, a L output register comprise as lower port: input end of clock, control input end, data input pin and data output end in the LED driver module; The control input end of shift register, a L output register connects data latching input end, a L output register control input end of LED driver module respectively; The data input pin of L output register connects the data output end of shift register;
MUX in the LED driver module of described led drive circuit comprises as lower port: select input end, L data input end and data output end, under the control of selecting side, MUX is selected in L data input end of output; The selection input end of MUX connects the selector switch control input end of LED driver module, and the L of MUX data input end connects the data output end of L output register respectively;
Constant current output module in the LED driver module of described led drive circuit comprises as lower port: output enable input end, data input pin and LED drive output; The data input pin of constant current output module connects the data output end of MUX.
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