CN111902936A - Qfn射频芯片封装 - Google Patents

Qfn射频芯片封装 Download PDF

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CN111902936A
CN111902936A CN201880091418.4A CN201880091418A CN111902936A CN 111902936 A CN111902936 A CN 111902936A CN 201880091418 A CN201880091418 A CN 201880091418A CN 111902936 A CN111902936 A CN 111902936A
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李相动
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Weibaopia Co ltd
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Abstract

本发明作为由包括匹配电路或无源器件的周边电路芯片、射频芯片及安装所述周边电路芯片和所述射频芯片的QFN基片构成的射频芯片封装，提供一种射频芯片封装，其在所述QFN基片的边缘区域形成有垫板，在未形成有所述垫板的中央的一部分区域形成有ロ凹陷形状的空腔，在所述QFN基片的空腔安装所述射频芯片，所述周边电路芯片的垫板中一部分与所述QFN基片的垫板重叠地配置，并通过导电体物质的连接销电性连接，所述周边电路芯片的垫板中另一部分与所述射频芯片的垫板重叠地配置，并通过所述导电体物质的连接销电性连接。

Description

QFN射频芯片封装
技术领域
本发明涉及QFN射频芯片封装，更详细地，涉及一种在射频芯片与周边电路芯片之间存在阶梯差时，在QFN基片预先形成
Figure BDA0002688742540000011
形状的空腔，在上述的空腔安装射频芯片，并通过连接销将周边电路芯片的垫板与射频芯片的垫板电性连接，从而，能够有效地抑制在射频芯片与周边电路芯片之间的阶梯差而发生的副作用的QFN射频芯片封装。
背景技术
因信息通信技术(ICT，Information and Communications Technologies)技术的扩散，以往在室外空间进行的各种活动逐渐地在室内进行。因此，在日常生活中室内空间所占据的比率逐渐增加，并且，导航仪等以室外空间为对象提供的服务逐渐以室内空间为对象进行扩张。
为了满足上述的服务需求，提供一种具有高性能的射频(RF；Radio Frequency)产品。
如上述地，为了提供高性能，射频产品需在一个封装内配置包括匹配电路或无源器件的周边电路芯片和射频芯片后焊接。并且，为了射频产品的高密度化，逐步形成采用方形扁平无引脚(QFN，Quad Flat Non-leaded)封装的趋势。
并且，包括匹配电路或无源器件的周边电路芯片和射频芯片的厚度相互不同而存在阶梯差，因此，如果在一个QFN封装内焊接包括匹配电路或无源器件的周边电路芯片和射频芯片，因上述的阶梯差而存在焊接工艺复杂或降低频率特性的问题。
本发明的背景技术在韩国公开专利公报10-2012-0098556号中公开。
发明内容
发明要解决的技术问题
因此，为了解决以往技术的问题点，本发明提供一种在射频芯片与周边电路芯片之间存在阶梯差时，在QFN基片预先形成
Figure BDA0002688742540000012
形状的空腔，在上述的空腔安装射频芯片，并通过连接销将周边电路芯片的垫板和射频芯片的垫板电性连接，从而，能够有效地抑制因射频芯片与周边电路芯片之间的阶梯差而发生的副作用的QFN射频芯片封装。
本发明要解决的技术问题并非限定于以上说明的技术问题，本发明的技术领域的普通技术人员应当通过如下说明明确理解未说明的其他技术问题。
解决问题的技术方案
为了实现上述的目的，根据本发明的一实施例的QFN射频芯片封装，作为由包括匹配电路或无源器件的周边电路芯片、射频芯片及安装所述周边电路芯片和所述射频芯片的QFN基片构成的射频芯片封装，在所述QFN基片的边缘区域形成有垫板，在未形成有所述垫板的中央的一部分区域形成有
Figure BDA0002688742540000021
形状的空腔，所述QFN基片的空腔安装所述射频芯片，所述周边电路芯片的垫板中一部分与所述QFN基片的垫板重叠地配置，并通过导电体物质的连接销电性连接，所述周边电路芯片的垫板中另一部分与所述射频芯片的垫板重叠地配置，并通过所述导电体物质的连接销电性连接。
优选地，根据本发明的实施例的QFN射频芯片封装，所述空腔的深度为所述射频芯片的厚度的约1倍～1.3倍。
附图说明
图1为适用于本发明的一实施例的QFN射频芯片封装的QFN基片的平面图；
图2为图1的截面图；
图3为根据本发明的一实施例的QFN射频芯片封装的截面图。
具体实施方式
后述的有关本发明的详细说明是示例能够实施本发明的特征实施例，其参照图示的参照附图。该实施例进行充分详细的说明，以便本发明的技术领域的技术人员实施本发明。应当理解虽然本发明的各种实施例相互不同，但，并非相互排他性。例如，在此记载的一实施例的特征形状、结构及特性在不脱离本发明的思想和范围的前提下可以其他实施例实施。并且，在各个公开的实施例中的个别构成要素的位置或配置在不脱离本发明的思想和范围的前提下可进行变更。
因此，后述的说明并非为了限定意义，本发明的范围只通过权利要求书的主张和与其均等的所有范围内的附加的权利要求而被定义。在附图中类似的参照符号从各个侧面指称相同或类似的功能，为了方便长度及面积、厚度等和其形状可夸张表示。
如图1、图2及图3图示，本发明的一实施例的QFN射频芯片封装包括如下结构而构成：包括匹配电路或无源器件的周边电路芯片210,220、射频芯片300及安装所述周边电路芯片210,220和所述射频芯片300的QFN基片100。
在此，所述QFN基片100可由硅QFN基片或铜QFN基片构成，并且，如图1所示，在所述QFN基片100的边缘区域形成有垫板111,112,113,114,115,116,117,118,121,122,123,124,125,126,127,128,131,132,133,134,135,136,137,138,141,142,143,144,145,146,147,148，并且，如图2所示，在未形成有所述垫板111,112,113,114,115,116,117,118,121,122,123,124,125,126,127,128,131,132,133,134,135,136,137,138,141,142,143,144,145,146,147,148的中央的一部分区域以蚀刻工艺或研磨工艺形成有
Figure BDA0002688742540000031
形状的空腔150。
并且，在所述QFN基片100的空腔150安装所述射频芯片300，在所述周边电路芯片210,220的垫板中的一部分211,221重叠地配置有所述QFN基片100的垫板114,134，并通过导电体物质的连接销411,421而电性连接，并且，在所述周边电路芯片210,220的垫板中的另一部分212,222重叠地配置有所述射频芯片300的垫板301,302，并通过所述导电体物质的连接销412,422电性连接。
如图3所示，所述连接销由Au、Ag、Cu或Al等导电性物质形成圆柱形状，并且，在所述周边电路芯片210,220的垫板中的一部分211,221与所述QFN基片100的垫板114,134之间配置连接销411,421并压缩，所述周边电路芯片210,220的垫板中的一部分211,221与所述QFN基片100的垫板114,134通过连接销411,421电性连接。
并且，在所述周边电路芯片210,220的垫板中的另一部分212,222与所述射频芯片300的垫板301,302之间配置连接销412,422并压缩，所述周边电路芯片210,220的垫板中的另一部分212,222与所述射频芯片300的垫板301,302通过连接销412,422电性连接。
在此，所述空腔150的深度形成能够维持所述射频芯片300的厚度的1倍～1.3倍左右的程度，而能够减少所述射频芯片300与所述周边电路芯片210,220之间存在的阶梯差。
根据本发明的一实施例的QFN射频芯片封装在所述QFN基片100预先形成
Figure BDA0002688742540000041
形状的空腔150，并在所述空腔150安装射频芯片300后，通过连接销411,421将所述周边电路芯片210,220的垫板中的一部分211,221与所述QFN基片100的垫板114,134电性连接，并且，通过连接销412,422将所述周边电路芯片210,220的垫板中的另一部分212,222与所述射频芯片300的垫板301,302电性连接，从而，能够减少所述射频芯片300与所述周边电路芯片210,220之间存在的阶梯差，因此，能够有效地抑制焊接工艺复杂或频率特性降低的问题。
以上为了示例本发明的原理而说明并图示了优选实施例，但，本发明并非限定于如上述地图示和说明的构成和作用。
本发明的技术领域的技术人员应当理解在不脱离附加的权利要求范围的思想和范畴的前提下，可对本发明进行各种变更和修改。
因此，此类的所有适当的变更和修改和均等物也应当被视为本发明的范围。

Claims (2)

1.一种QFN射频芯片封装，由包括匹配电路或无源器件的周边电路芯片、射频芯片及安装所述周边电路芯片和所述射频芯片的QFN基片构成的射频芯片封装，其特征在于，
在所述QFN基片的边缘区域形成有垫板，在未形成有所述垫板的中央的一部分区域形成有
Figure FDA0002688742530000011
形状的空腔，
所述QFN基片的空腔安装所述射频芯片，
所述周边电路芯片的垫板中一部分与所述QFN基片的垫板重叠地配置，并通过导电体物质的连接销电性连接，
所述周边电路芯片的垫板中另一部分与所述射频芯片的垫板重叠地配置，并通过所述导电体物质的连接销电性连接。
2.根据权利要求1所述的QFN射频芯片封装，其特征在于，
所述空腔的深度为所述射频芯片的厚度的约1倍～1.3倍。
CN201880091418.4A 2018-03-23 2018-06-05 Qfn射频芯片封装 Active CN111902936B (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060099936A (ko) * 2005-03-15 2006-09-20 한국과학기술원 극미세피치를 가지는 플립칩 및 이의 제조방법
US20070232050A1 (en) * 2006-03-31 2007-10-04 Munehiro Toyama Embedding device in substrate cavity
CN102460690A (zh) * 2009-06-24 2012-05-16 英特尔公司 多芯片封装和在其中提供管芯到管芯互连的方法
CN106165092A (zh) * 2014-02-26 2016-11-23 英特尔公司 具有穿桥导电过孔信号连接的嵌入式多器件桥

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060099936A (ko) * 2005-03-15 2006-09-20 한국과학기술원 극미세피치를 가지는 플립칩 및 이의 제조방법
US20070232050A1 (en) * 2006-03-31 2007-10-04 Munehiro Toyama Embedding device in substrate cavity
CN102460690A (zh) * 2009-06-24 2012-05-16 英特尔公司 多芯片封装和在其中提供管芯到管芯互连的方法
CN106165092A (zh) * 2014-02-26 2016-11-23 英特尔公司 具有穿桥导电过孔信号连接的嵌入式多器件桥

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