CN110600431A - 集成电路封装体及其形成方法 - Google Patents

集成电路封装体及其形成方法 Download PDF

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CN110600431A
CN110600431A CN201910833366.XA CN201910833366A CN110600431A CN 110600431 A CN110600431 A CN 110600431A CN 201910833366 A CN201910833366 A CN 201910833366A CN 110600431 A CN110600431 A CN 110600431A
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李维钧
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SUZHOU RIYUEXIN SEMICONDUCTOR CO Ltd
Suzhou ASEN Semiconductors Co Ltd
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract

本发明涉及一种集成电路封装体的形成方法。根据本发明一实施例的集成电路封装体，其包括：芯片；芯片座，经配置以承载芯片；信号引脚，设置于芯片座外围且经配置以与芯片电连接；接地引脚，设置于芯片座外围且经配置以接地，至少一导电凸块，设置于接地引脚上方以与接地引脚电连接；绝缘壳体，其遮蔽芯片、芯片座、信号引脚、以及接地引脚，并使至少一导电凸块上端外露；屏蔽金属层，其覆盖在绝缘壳体的上方及侧壁以及至少一导电凸块上端，以与至少一导电凸块电连接。根据本发明实施例的集成电路封装体及其形成方法可以简化制造工艺、降低制造成本。

Description

集成电路封装体及其形成方法
本申请是申请日为2015年9月1日，申请号为201510552353.7，发明名称为“集成电路封装体及其形成方法”的申请的分案申请。
技术领域
本发明涉及一种集成电路封装体及形成该集成电路封装体的方法。
背景技术
因越来越多的无线通信装置被高度集成在一有限面积的手机中，使得原本较不受重视、且采用低成本的导线框架加工的射频组件如：射频功率放大器(RF PowerAmplifier,RF PA)、低噪声功率放大器(Low Noise Amplifier,LNA)、天线开关(AntennaSwitch)等面临的电磁场干扰问题也越来越多。
在公开号为CN102479767A的专利申请中，利用先设计好的高低配置好的导线框架将信号垫(Signal Pad)与地垫(GND Pad)分开。在这种技术中，信号引脚与导线框架的外缘平齐，而接地引脚内缩于导线框架的外缘内。为了使位于芯片外围的屏蔽金属层能够与接地引脚电连接形成电磁场屏蔽，需要在制作接地引脚时将接地引脚制作得高于信号引脚，利用半切(half-cut)方式切到高于信号引脚的接地引脚(GND引脚)露出后，即停止切割，之后完成金属涂层，如此完成电磁场屏蔽。
在CN102479767A的专利申请中，高低引脚配置好的导线框架需要特殊模具定制而成，使其制作成本偏高。
因此，现有的具有电磁场屏蔽功能的集成电路封装体及其制作方法仍需进一步改进。
发明内容
本发明的目的之一在于提供集成电路封装体及形成该集成电路封装体的方法，能够以简单的工艺获得具有电磁场屏蔽功能的集成电路封装体。
本发明的一实施例提供了一集成电路封装体，其包括：芯片；芯片座，经配置以承载该芯片；信号引脚，设置于该芯片座外围且经配置以与该芯片电连接；接地引脚，设置于该芯片座外围且经配置以接地；至少一导电凸块，设置于该接地引脚上方以与该接地引脚电连接；绝缘壳体，其遮蔽该芯片、该芯片座、该信号引脚、以及该接地引脚，并使该至少一导电凸块上端外露；屏蔽金属层，其覆盖在该绝缘壳体的上方及侧壁以及该至少一导电凸块上端，以与该至少一导电凸块电连接。
本发明的另一实施例提供了一形成集成电路封装体的方法，其包括：将芯片固定于芯片座上；用引线连接该芯片与位于该芯片座外围的信号引脚；在位于该芯片座外围的接地引脚上方形成与该接地引脚电连接的至少一导电凸块；注塑而形成绝缘壳体，该绝缘壳体遮蔽该芯片、该芯片座、该信号引脚、该芯片与该信号引脚之间的该引线、该接地引脚、及该至少一导电凸块；在该绝缘壳体中正对该至少一导电凸块上方自上而下开槽直至该至少一导电凸块上端外露；以及在该绝缘壳体上方及该槽的侧壁和底部覆盖屏蔽金属层，使得该屏蔽金属层与该至少一导电凸块电连接。
根据本发明实施例的集成电路封装体及形成集成电路封装体的方法，在接地引脚上方形成与接地引脚电连接的导电凸块，并使金属屏蔽层覆盖导电凸块的上端形成电连接，从而达到屏蔽电磁场干扰的目的。因此，不需要像现有技术那样需要采用特殊的模具来定制高低引脚配置的导线框架。相应的，本发明具有制造工艺简单，制造成本低的优点。
附图说明
图1是根据本发明一个实施例的集成电路封装体的纵向截面示意图。
图2是图1中的集成电路封装体的横向截面示意图。
图3是根据本发明另一个实施例的集成电路封装体的横向截面示意图。
图4是根据本发明一个实施例的形成集成电路封装体的方法的流程图。
图5A-图5F是采用图4的方法制作集成电路封装体的过程的示例性示意图。
具体实施方式
图1是根据本发明一个实施例的集成电路封装体100的纵向截面示意图。图2是图1中的集成电路封装体100的横向截面示意图。
如图1、图2所示，根据本发明一个实施例的集成电路封装体100包括芯片101、芯片座102、信号引脚207、接地引脚103、绝缘壳体104、屏蔽金属层105、及至少一个导电凸块108。芯片座102经配置以承载该芯片101。信号引脚207设置于芯片座102外围且经配置以与芯片101电连接。接地引脚103设置于芯片座102外围且经配置以接地。在本实施例中，信号引脚207相对于接地引脚103不内缩。导电凸块108设置于接地引脚103上方以与接地引脚103电连接。绝缘壳体104遮蔽芯片101、芯片座102、信号引脚207以及接地引脚103，并使导电凸块108上端外露。屏蔽金属层105覆盖在绝缘壳体104上方及侧壁以及导电凸块108上端，以与导电凸块108电连接。由于在接地引脚103上方形成与接地引脚103电连接的导电凸块108，并使金属屏蔽层105覆盖导电凸块108的上端形成电连接，从而能够达到屏蔽电磁场干扰的目的。因此，不需要像现有技术那样需要采用特殊的模具来定制高低引脚配置的导线框架。相应的，本发明具有制造工艺简单，制造成本低的优点。
如图1所示，在本实施例中，导电凸块108可以是焊球或其它种类的金属球。
在本实施例中，设置芯片座102外围的接地引脚103的数目与芯片101的频率有关。芯片101的频率越高，需要的接地引脚103越多。接地引脚103可以包括位于集成电路封装体100的端角处的接地引脚103。端角处的接地引脚103可以经配置以通过引线107或连接部109与芯片座102电连接。接地引脚103还可以包括至少一个位于集成电路封装体100的相邻端角之间的接地引脚103。如图2所示，集成电路封装体100的相邻端角之间的接地引脚103经配置以通过引线107与芯片座102电连接，或者通过引线107与该端角处的接地引脚103连接。如图2所示，在本实施例中，接地引脚103可以与信号引脚207交替布置。
图3是根据本发明另一个实施例的集成电路封装体的横向截面示意图。在图3所示的实施例中，除了信号引脚207相对于接地引脚103内缩之外，集成电路封装体的结构与图1、图2所示的实施例相同。在图3所示的实施例中，信号引脚207相对于接地引脚103例如内缩50μm，100μm，或150μm，但不限于此。
图4是根据本发明一个实施例的形成集成电路封装体100的方法的流程图，其可形成图1、2所示实施例中的集成电路封装体100。图5A-图5F是采用图4的方法制作集成电路封装体100的过程的示例性示意图。
根据图4所示的实施例，在步骤S301中，如图5A所示，待封装的导线框架条上设有若干阵列排列的导线框单元，其中各导线框单元的接地引脚103相互连接在一起。对于每一导线框单元，将芯片101固定于芯片座102上。在步骤S302中，用引线107连接芯片101与信号引脚207。在步骤S303中，如图5B所示，在位于芯片座102外围的接地引脚103上方形成与接地引脚103电连接的导电凸块108。譬如使用打线机形成用作导电凸块108的焊球或其他种类的金属球。如图2所示，信号引脚207相对于接地引脚103内缩。在步骤S304中，如图5C所示，注塑而形成绝缘壳体104，绝缘壳体104遮蔽芯片101、芯片座102、信号引脚207、芯片101与信号引脚207之间的引线107、接地引脚103、及导电凸块108。在步骤S305中，如图5D所示，在绝缘壳体104中正对导电凸块108上方自上而下开槽410直至导电凸块108上端外露。在步骤S306中，如图5E所示，在绝缘壳体101上方以及所开的槽410的侧壁和底部覆盖屏蔽金属层105，使得屏蔽金属层105与导电凸块108电连接。屏蔽金属层105例如但不限于通过溅镀形成。如图5F所示，将连在一起的多个集成电路封装体100进行分割，得到多个分离的集成电路封装体100。由于在接地引脚103上方形成与接地引脚103电连接的导电凸块108，并使金属屏蔽层105覆盖导电凸块108的上端形成电连接，从而能够达到屏蔽电磁场干扰的目的。因此，不需要像现有技术那样需要采用特殊的模具来定制高低引脚配置的导线框架。相应的，本发明具有制造工艺简单，制造成本低的优点。
本发明的技术内容及技术特点已揭示如上，然而熟悉本领域的技术人员仍可能基于本发明的教示及揭示而作种种不背离本发明精神的替换及修饰。因此，本发明的保护范围应不限于实施例所揭示的内容，而应包括各种不背离本发明的替换及修饰，并为本专利申请权利要求书所涵盖。

Claims (3)

1.一种形成集成电路封装体的方法，其包括：
将芯片固定于芯片座上；
用引线连接所述芯片与位于所述芯片座外围的信号引脚；
在位于所述芯片座外围的接地引脚上方形成与所述接地引脚电连接的至少一导电凸块；其中所述接地引脚当中包括位于所述集成电路封装体的端角处的接地引脚，所述端角处的接地引脚经配置以通过引线或连接部与所述芯片座电连接；
注塑而形成绝缘壳体，所述绝缘壳体遮蔽所述芯片、所述芯片座、所述信号引脚、所述芯片与所述信号引脚之间的所述引线、所述接地引脚、及所述至少一导电凸块；
在所述绝缘壳体中正对所述至少一导电凸块上方自上而下开槽直至所述至少一导电凸块上端外露；以及
在所述绝缘壳体上方及所述槽的侧壁和底部覆盖屏蔽金属层，使得所述屏蔽金属层与所述至少一导电凸块电连接。
2.根据权利要求1所述的方法，其中形成所述至少一导电凸块进一步包含使用打线机形成的焊球或其他种类的金属球。
3.根据权利要求1所述的方法，其中所述接地引脚当中还包括至少一个位于所述集成电路封装体的相邻端角之间的接地引脚，所述相邻端角之间的接地引脚经配置以通过引线与所述端角处的接地引脚或所述芯片座电连接。
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