CN111883622A - Light emitting diode epitaxial wafer and preparation method thereof - Google Patents

Light emitting diode epitaxial wafer and preparation method thereof Download PDF

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Publication number
CN111883622A
CN111883622A CN202010532472.7A CN202010532472A CN111883622A CN 111883622 A CN111883622 A CN 111883622A CN 202010532472 A CN202010532472 A CN 202010532472A CN 111883622 A CN111883622 A CN 111883622A
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layer
ingan well
light emitting
gan
gan barrier
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CN111883622B (en
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姚振
从颖
董彬忠
李鹏
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HC Semitek Zhejiang Co Ltd
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HC Semitek Zhejiang Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
    • H01L33/325—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen characterised by the doping materials

Abstract

The disclosure provides a light emitting diode epitaxial wafer and a preparation method thereof, and belongs to the technical field of light emitting diodes. The light-emitting layer includes a first composite layer and a second composite layer. The first GaN barrier layer in the first composite layer slightly blocks electrons, and the electron migration speed is slowed down. The first InGaN well layer with larger thickness provides a migration space with more electrons and accumulates the electrons, the electrons which migrate to the second composite layer and are compounded are reduced, and holes with lower migration speed have enough space to migrate to the second composite layer and the first composite layer which comprise a plurality of alternately laminated second InGaN well layers and third GaN barrier layers and are compounded. The thickness of the second GaN barrier layer is smaller than that of the third GaN barrier layer, more holes can enter the first composite layer close to the n-type GaN layer to be combined with more electrons for light emission, the electrons and the holes are not concentrated on the edge of the light emitting layer close to the p-type GaN layer for light emission, and the light emitting uniformity of the epitaxial wafer can be improved.

Description

Light emitting diode epitaxial wafer and preparation method thereof
Technical Field
The disclosure relates to the technical field of light emitting diodes, and particularly relates to a light emitting diode epitaxial wafer and a preparation method thereof.
Background
The light emitting diode is a light emitting device with wide application, and is commonly used for communication signal lamps, automobile interior and exterior lamps, urban illumination, landscape illumination and the like, and the light emitting diode epitaxial wafer is a basic structure for preparing the light emitting diode. The light emitting diode epitaxial wafer generally includes a substrate and an epitaxial layer grown on the substrate, wherein the epitaxial layer includes at least a GaN buffer layer, an n-type GaN layer, a light emitting layer and a p-type GaN layer sequentially stacked on the substrate. The light emitting layer generally includes InGaN well layers and GaN barrier layers stacked alternately, and both electrons in the n-type GaN layer and holes in the p-type GaN layer migrate into the InGaN well layers under the action of current to perform composite light emission.
Since the electron transfer speed is much faster than the hole transfer speed, when the electron from the n-type GaN layer transfers to the light emitting layer near the edge of the p-type GaN layer, the electron from the p-type GaN layer may just transfer to the light emitting layer. In the light emitting diode, electrons and holes are mainly concentrated on one side of the light emitting layer close to the p-type GaN layer to emit light, and the light emitting uniformity of the light emitting diode is poor.
Disclosure of Invention
The embodiment of the disclosure provides a light emitting diode epitaxial wafer and a preparation method thereof, which can improve the light emitting uniformity of a light emitting diode. The technical scheme is as follows:
the embodiment of the disclosure provides a light emitting diode epitaxial wafer and a preparation method thereof, the light emitting diode epitaxial wafer comprises a substrate and an epitaxial layer grown on the substrate, the epitaxial layer comprises an n-type GaN layer, a light emitting layer and a p-type GaN layer which are sequentially stacked on the substrate,
the light emitting layer comprises a first composite layer and a second composite layer which are sequentially laminated on the n-type GaN layer, the first composite layer comprises a first GaN barrier layer, a first InGaN well layer and a second GaN barrier layer which are sequentially laminated on the n-type GaN layer, the second composite layer comprises a plurality of second InGaN well layers and third GaN barrier layers which are alternately laminated,
the thickness of the first GaN barrier layer is smaller than that of the third GaN barrier layer, the thickness of the first InGaN well layer is larger than that of the second InGaN well layer, the thickness of the second GaN barrier layer is larger than or equal to that of the second InGaN well layer, and the thickness of the second GaN barrier layer is smaller than that of the third GaN barrier layer.
Optionally, the thickness of the first GaN barrier layer is smaller than that of the first InGaN well layer.
Optionally, the thickness of the first InGaN well layer is smaller than that of the third GaN barrier layer.
Optionally, the thickness of the first GaN barrier layer is 1-2.5 nm, the thickness of the first InGaN well layer is 4-5.5 nm, and the thickness of the second GaN barrier layer is 4.5-6 nm.
Optionally, the In content In the first InGaN well layer decreases In a direction directed from the n-type GaN layer to the p-type GaN layer.
The embodiment of the disclosure provides a preparation method of a light-emitting diode epitaxial wafer, which comprises the following steps:
providing a substrate;
growing an n-type GaN layer on the substrate;
growing a light emitting layer on the n-type GaN layer, wherein the light emitting layer comprises a first composite layer and a second composite layer which are sequentially laminated on the n-type GaN layer, the first composite layer comprises a first GaN barrier layer, a first InGaN well layer and a second GaN barrier layer which are sequentially laminated on the n-type GaN layer, the second composite layer comprises a plurality of second InGaN well layers and third GaN barrier layers which are alternately laminated, the thickness of the first GaN barrier layer is smaller than that of the third GaN barrier layer, the thickness of the first InGaN well layer is larger than that of the second InGaN well layer, the thickness of the second GaN barrier layer is larger than or equal to that of the second InGaN well layer, and the thickness of the second GaN barrier layer is smaller than that of the third GaN barrier layer;
and growing a p-type GaN layer on the light emitting layer.
Optionally, when the first InGaN well layer is grown on the first GaN barrier layer, dividing the growth time of the first InGaN well layer into an In source introduction time and an In source stop time In a time sequence,
and continuously introducing the In source into the reaction cavity within the time of introducing the In source, and stopping introducing the In source into the reaction cavity within the time of stopping introducing the In source.
Optionally, the growth time of the first InGaN well layer is 2-4 min.
Optionally, the time for stopping the In source is 10-40 s.
Optionally, a ratio of the time for stopping the In source flowing to the growth time of the first InGaN well layer is less than or equal to 1/10.
The beneficial effects brought by the technical scheme provided by the embodiment of the disclosure include:
a light emitting layer in an epitaxial wafer of the epitaxial wafer is provided to include a first composite layer and a second composite layer which are sequentially laminated on the n-type GaN layer. The first composite layer comprises a first GaN barrier layer, a first InGaN well layer and a second GaN barrier layer which are sequentially stacked on the n-type GaN layer, and the second composite layer comprises a plurality of second InGaN well layers and third GaN barrier layers which are alternately stacked. The thickness of the first GaN barrier layer is smaller than that of the third GaN barrier layer, the first GaN barrier layer with smaller thickness can play a role of slightly blocking electrons, so that the electrons relatively and uniformly enter the first InGaN well layer, meanwhile, the first GaN barrier layer with smaller thickness has a weaker blocking role on the electrons, and most of the electrons can enter the first InGaN well layer. The thickness of the first InGaN well layer is larger than that of the second InGaN well layer, the first InGaN well layer with the larger thickness can provide a migration space with more electrons, more electrons are accumulated, electrons which are migrated to the second composite layer and are compounded are reduced, and holes with the lower migration speed have enough space to migrate to the second composite layer and be compounded with the first composite layer. Most electrons are limited in the first InGaN well layer, the thickness of the second GaN barrier layer stacked on the first InGaN well layer is larger than or equal to that of the second InGaN well layer, the thickness of the second GaN barrier layer is smaller than that of the third GaN barrier layer, the blocking effect of the second GaN barrier layer on holes is weakened, and the holes can more easily pass through the second GaN barrier layer and enter the first InGaN well layer for compound light emission. More holes can enter the first composite layer close to the n-type GaN layer to be recombined with more electrons for light emission, and the electrons and the holes are not concentrated on the edge of the light emitting layer close to the p-type GaN layer for light emission, so that the light emitting uniformity of the epitaxial wafer can be improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of another light emitting diode epitaxial wafer according to an embodiment of the present disclosure;
fig. 3 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure;
fig. 4 is a flowchart of another method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present disclosure. As can be seen from fig. 1, the embodiment of the present disclosure provides a light emitting diode epitaxial wafer, which includes a substrate 1 and an epitaxial layer 2 grown on the substrate 1, wherein the epitaxial layer 2 includes an n-type GaN layer 21, a light emitting layer 22 and a p-type GaN layer 23 sequentially stacked on the substrate 1.
The light emitting layer 22 includes a first composite layer 221 and a second composite layer 222 sequentially stacked on the n-type GaN layer 21, the first composite layer 221 includes a first GaN barrier layer 2211, a first InGaN well layer 2212, and a second GaN barrier layer 2213 sequentially stacked on the n-type GaN layer 21, and the second composite layer 222 includes a plurality of second InGaN well layers 2221 and third GaN barrier layers 2222 alternately stacked. The thickness of the first GaN barrier layer 2211 is smaller than that of the third GaN barrier layer 2222, the thickness of the first InGaN well layer 2212 is larger than that of the second InGaN well layer 2221, the thickness of the second GaN barrier layer 2213 is larger than or equal to that of the second InGaN well layer 2221, and the thickness of the second GaN barrier layer 2213 is smaller than that of the third GaN barrier layer 2222.
The light-emitting layer 22 in the epitaxial wafer of the epitaxial wafer is provided to include a first composite layer 221 and a second composite layer 222 laminated in this order on the n-type GaN layer 21. The first composite layer 221 includes a first GaN barrier layer 2211, a first InGaN well layer 2212, and a second GaN barrier layer 2213 sequentially stacked on the n-type GaN layer 21, and the second composite layer 222 includes a plurality of second InGaN well layers 2221 and third GaN barrier layers 2222 alternately stacked. The thickness of the first GaN barrier layer 2211 is smaller than that of the third GaN barrier layer 2222, the first GaN barrier layer 2211 with smaller thickness can play a role in slightly blocking electrons, so that the electrons relatively uniformly enter the first InGaN well layer 2212, meanwhile, the first GaN barrier layer 2211 with smaller thickness has a weaker electron blocking effect, and most of the electrons enter the first InGaN well layer 2212. The thickness of the first InGaN well layer 2212 is greater than that of the second InGaN well layer 2221, and the first InGaN well layer 2212 with a greater thickness can provide a migration space for more electrons, accumulate more electrons, reduce electrons that migrate to the second composite layer 222 and are recombined, so that holes with a slower migration speed have a sufficient space to migrate to the second composite layer 222 and be recombined with the first composite layer 221. Most electrons are confined in the first InGaN well layer 2212, the thickness of the second GaN barrier layer 2213 laminated on the first InGaN well layer 2212 is greater than or equal to that of the second InGaN well layer 2221, and the thickness of the second GaN barrier layer 2213 is smaller than that of the third GaN barrier layer 2222, so that the blocking effect of the second GaN barrier layer 2213 on holes is weakened, and the holes more easily pass through the second GaN barrier layer 2213 and enter the first InGaN well layer 2212 for compound light emission. More holes can enter the first composite layer 221 close to the n-type GaN layer 21 to be recombined with more electrons for emitting light, and the electrons and the holes are not concentrated at the edge of the light-emitting layer 22 close to the p-type GaN layer 23 for emitting light, so that the light-emitting uniformity of the epitaxial wafer can be improved.
And the luminous uniformity of the epitaxial wafer is improved, so that the epitaxial wafer can be applied to the preparation processes of different light emitting diodes. The epitaxial wafer with improved light emitting uniformity can be used for preparing micro light emitting diodes with limited sizes, and the light emitting intensity and the light emitting uniformity of the obtained micro light emitting diodes can be guaranteed.
Alternatively, the thickness of the first GaN barrier layer 2211 may be smaller than the thickness of the first InGaN well layer 2212.
The thickness of the first GaN barrier layer 2211 can be smaller than that of the first InGaN well layer 2212, the thickness of the first GaN barrier layer 2211 has a small blocking effect on electrons, the electrons can stably enter the first InGaN well layer 2212, and the first InGaN well layer 2212 with the larger thickness can also have more space, so that more electrons and holes are compounded.
Alternatively, the thickness of the first InGaN well layer 2212 may be smaller than the thickness of the third GaN barrier layer 2222.
The thickness of the first InGaN well layer 2212 is smaller than that of the third GaN barrier layer 2222, the thickness of the first InGaN well layer 2212 is set reasonably, electrons can be better constrained in the first InGaN well layer 2212 for composite light emission, the thickness of the first InGaN well layer 2212 is not too large, the low-temperature growth time required by the first InGaN well layer 2212 is too long, and the overall crystal quality of the epitaxial layer 2 is affected by low temperature.
Illustratively, the thickness of the first GaN barrier layer 2211 can be 1-2.5 nm, the thickness of the first InGaN well layer 2212 can be 4-5.5 nm, and the thickness of the second GaN barrier layer 2213 can be 4.5-6 nm.
When the thickness of the first GaN barrier layer 2211, the thickness of the first InGaN well layer 2212, and the thickness of the second GaN barrier layer 2213 are within the above ranges, the first GaN barrier layer 2211 can slow down the migration velocity of electrons, and meanwhile, the electrons can smoothly jump over the first GaN barrier layer 2211 to enter the first InGaN well layer 2212, so that the light emitting efficiency of the epitaxial wafer is good. The thickness of the first InGaN well layer 2212 is in the above range, electrons can be well confined in the first InGaN well layer 2212 to perform composite light emission, and the crystal quality of the entire epitaxial layer 2 is also good. When the thickness of the second GaN barrier layer 2213 is 4.5-6 nm, the overall crystal quality of the first composite layer 221 is good, the effect of blocking holes is not too strong, and more holes can be allowed to enter the first InGaN well layer 2212. The light emitting diode prepared by the epitaxial wafer has high luminous efficiency.
Optionally, the thickness of first GaN barrier layer 2211 may also be 1-2 nm.
The thickness of the first GaN barrier layer 2211 is 1-2 nm, the migration speed of electrons can be slowed down to a reasonable degree, the number of electrons entering the first InGaN well layer 2212 is equivalent to the number of holes entering the InGaN well layer, and the light emitting efficiency and the light emitting uniformity of the light emitting diode are effectively guaranteed.
Illustratively, the thickness of the first InGaN well layer 2212 may also be 4-5 nm. It can be ensured that the electrons and the holes have a sufficient recombination space.
Optionally, the thickness of the second GaN barrier layer 2213 may also be 4.5-5.5 nm.
When the thickness of the second GaN barrier layer 2213 is 4.5-5.5 nm, the crystal quality of the second GaN barrier layer 2213 is good, the blocking effect on the holes is weak, the number of holes which enter the first InGaN well layer 2212 for recombination and light emission is large, and the light emitting efficiency and the light emitting uniformity of the light emitting diode can be effectively improved.
Alternatively, the In content In the first InGaN well layer 2212 may be reduced In the direction directed from the n-type GaN layer 21 to the p-type GaN layer 23.
The In content In the first InGaN well layer 2212 is reduced In the direction from the n-type GaN layer 21 to the p-type GaN layer 23, so that while the first InGaN well layer 2212 plays a role In confining electrons and holes, a barrier at one side of the first InGaN well layer 2212 close to the second GaN barrier layer 2213 is slightly higher, and a good transition and engagement can be formed between the first InGaN well layer 2212 and the second GaN barrier layer 2213, so that holes can more easily enter the first InGaN well layer 2212 from the second GaN barrier layer 2213 with a higher barrier, and the number of holes which can enter the first InGaN well layer 2212 for composite light emission is increased. In the above structure, too much In element does not exist on the side of the first InGaN well layer 2212 close to the second GaN barrier layer 2213, and when the second GaN barrier layer 2213 grows, too much In atoms In the first InGaN well layer 2212 are not decomposed and precipitated into the second GaN barrier layer 2213 due to high temperature, so that the crystal quality of the second GaN barrier layer 2213 can be improved, and the light emitting efficiency of the light emitting diode is also improved.
The In content In the first InGaN well layer 2212 is still In the range of 0.2 to 0.35. In this case, the first InGaN well layer 2212 can perform its function of trapping carriers such as electrons and holes.
Alternatively, in the second composite layer 222, the thickness of the second InGaN well layer 2221 may be 2 to 3nm, and the thickness of the third GaN barrier layer 2222 may be 9 to 20 nm. The obtained light-emitting diode has better luminous efficiency.
For example, in the second composite layer 222, the number of the second InGaN well layer 2221 and the number of the third GaN barrier layer 2222 may be equal, and the number of the second InGaN well layer 2221 may be 1 to 5.
The number of layers of the second InGaN well layer 2221 is equal to the number of layers of the third GaN barrier layer 2222, and the number of layers of the second InGaN well layer 2221 may be 1 to 5, in this range, electrons and holes may enter the second composite layer 222 and the first composite layer 221 relatively uniformly, so that the light emitting efficiency and the light emitting uniformity of the light emitting diode may be greatly improved.
Optionally, the number of the second InGaN well layer 2221 may also be 1 to 4. The luminous efficiency and the luminous uniformity of the light emitting diode are also greatly improved.
Fig. 2 is a schematic structural diagram of another light emitting diode epitaxial wafer according to an embodiment of the present disclosure, and as can be seen from fig. 2, in another implementation manner provided by the present disclosure, the light emitting diode epitaxial wafer may include a substrate 1 and an epitaxial layer 2 grown on the substrate 1, and the epitaxial layer 2 may further include a low temperature buffer layer 24, a high temperature buffer layer 25, an n-type GaN layer 21, a current spreading layer, a light emitting layer 22, an electron blocking layer 26, and a p-type GaN layer 23, which are sequentially stacked on the substrate 1.
Note that the structure of the light-emitting layer 22 shown in fig. 2 is the same as the structure of the light-emitting layer 22 shown in fig. 1, and the description thereof is omitted.
Alternatively, the substrate 1 may be a sapphire substrate. Easy to manufacture and obtain.
Illustratively, the low temperature buffer layer 24 may be a low temperature GaN buffer layer. The crystal quality of the epitaxial thin film grown on the low-temperature buffer layer 24 can be ensured.
Optionally, the low temperature buffer layer 24 may have a thickness of 10 to 30 nm. The lattice mismatch between the n-type GaN layer 21 and the substrate 1 can be reduced, and the growth quality of the epitaxial layer 2 is ensured.
Illustratively, the high temperature buffer layer 25 may be an undoped GaN layer, and the thickness of the undoped GaN layer may be 2 to 3.5 μm. The quality of the obtained light emitting diode epitaxial wafer is good.
Alternatively, the doping element of the n-type GaN layer 21 may be Si, and the doping concentration of the Si element may be 1 × 1018～1×1019cm-3. The overall quality of the n-type GaN layer 21 is good.
Illustratively, the thickness of the n-type GaN layer 21 may be 2 to 3 μm. The obtained n-type GaN layer 21 has good quality as a whole.
Alternatively, the electron blocking layer 26 may be Mg-doped AlyGa1-yN layers, wherein y ranges from 0.15 to 0.25. The effect of blocking electrons is better.
Illustratively, the electron blocking layer 26 may have a thickness of 30 to 50 nm. The quality of the epitaxial layer 2 as a whole is good.
Optionally, the p-type GaN layer 23 can be doped with Mg, and the thickness of the p-type GaN layer 23 can be 50-80 nm. The obtained p-type GaN layer 23 has good quality as a whole.
Fig. 3 is a flowchart of a method for manufacturing an led epitaxial wafer according to an embodiment of the present disclosure, and as shown in fig. 3, the method for manufacturing an led epitaxial wafer includes:
s101: a substrate is provided.
S102: an n-type GaN layer is grown on the substrate.
S103: and growing a light emitting layer on the n-type GaN layer.
The light emitting layer comprises a first composite layer and a second composite layer which are sequentially stacked on the n-type GaN layer, the first composite layer comprises a first GaN barrier layer, a first InGaN well layer and a second GaN barrier layer which are sequentially stacked on the n-type GaN layer, and the second composite layer comprises a plurality of second InGaN well layers and third GaN barrier layers which are alternately stacked. The thickness of the first GaN barrier layer is smaller than that of the third GaN barrier layer, the thickness of the first InGaN well layer is larger than that of the second InGaN well layer, the thickness of the second GaN barrier layer is larger than or equal to that of the second InGaN well layer, and the thickness of the second GaN barrier layer is smaller than that of the third GaN barrier layer.
S104: and growing a p-type GaN layer on the light emitting layer.
A light emitting layer in an epitaxial wafer of the epitaxial wafer is provided to include a first composite layer and a second composite layer which are sequentially laminated on the n-type GaN layer. The first composite layer comprises a first GaN barrier layer, a first InGaN well layer and a second GaN barrier layer which are sequentially stacked on the n-type GaN layer, and the second composite layer comprises a plurality of second InGaN well layers and third GaN barrier layers which are alternately stacked. The thickness of the first GaN barrier layer is smaller than that of the third GaN barrier layer, the first GaN barrier layer with smaller thickness can play a role of slightly blocking electrons, so that the electrons relatively and uniformly enter the first InGaN well layer, meanwhile, the first GaN barrier layer with smaller thickness has a weaker blocking role on the electrons, and most of the electrons can enter the first InGaN well layer. The thickness of the first InGaN well layer is larger than that of the second InGaN well layer, the first InGaN well layer with the larger thickness can provide a migration space with more electrons, more electrons are accumulated, electrons which are migrated to the second composite layer and are compounded are reduced, and holes with the lower migration speed have enough space to migrate to the second composite layer and be compounded with the first composite layer. Most electrons are limited in the first InGaN well layer, the thickness of the second GaN barrier layer stacked on the first InGaN well layer is larger than or equal to that of the second InGaN well layer, the thickness of the second GaN barrier layer is smaller than that of the third GaN barrier layer, the blocking effect of the second GaN barrier layer on holes is weakened, and the holes can more easily pass through the second GaN barrier layer and enter the first InGaN well layer for compound light emission. More holes can enter the first composite layer close to the n-type GaN layer to be recombined with more electrons for light emission, and the electrons and the holes are not concentrated on the edge of the light emitting layer close to the p-type GaN layer for light emission, so that the light emitting uniformity of the epitaxial wafer can be improved.
The structure of the light emitting diode epitaxial wafer after the step S104 is performed can be seen in fig. 1.
It should be noted that the light emitting layer includes a first composite layer and a second composite layer that are sequentially stacked on the n-type GaN layer, the first composite layer includes a first GaN barrier layer, a first InGaN well layer, and a second GaN barrier layer that are sequentially stacked on the n-type GaN layer, and the second composite layer includes a plurality of second InGaN well layers and third GaN barrier layers that are alternately stacked. Therefore, when the light emitting layer is grown on the n-type GaN layer, a first GaN barrier layer, a first InGaN well layer, and a second GaN barrier layer are actually grown on the n-type GaN layer in sequence, and then a second InGaN well layer and a third GaN barrier layer are alternately grown on the second GaN barrier layer.
Fig. 4 is a flowchart of another method for manufacturing an led epitaxial wafer according to an embodiment of the present disclosure, and as shown in fig. 4, the method for manufacturing an led epitaxial wafer includes:
s201: a substrate is provided.
Wherein the substrate may be a sapphire substrate. Easy to realize and manufacture.
Optionally, step S201 may further include: and treating the surface of the substrate for growing the epitaxial layer for 5-6 min in a hydrogen atmosphere.
For example, when the substrate is processed for growing the surface of the epitaxial layer, the temperature of the reaction chamber may be 1000-1100 ℃, and the pressure of the reaction chamber may be 200-500 torr.
S202: a low temperature buffer layer is grown on the substrate.
In step S202, the low temperature buffer layer may be a low temperature GaN buffer layer.
Alternatively, the low-temperature GaN buffer layer may be grown on the [0001] plane of the sapphire substrate. The low-temperature GaN buffer layer is tightly combined with the sapphire substrate, and the obtained low-temperature GaN buffer layer has good crystal quality.
Optionally, the thickness of the low-temperature GaN buffer layer can be 10-30 nm.
Optionally, the growth temperature of the low-temperature GaN buffer layer can be 530-560 ℃, and the growth pressure can be 200-500 Torr. The obtained GaN low-temperature three-dimensional nucleation layer has better quality.
S203: and growing a high-temperature buffer layer on the low-temperature buffer layer.
Alternatively, the high temperature buffer layer may be an undoped GaN layer. The thickness of the non-doped GaN layer can be 2-3.5 um.
Illustratively, the growth temperature of the non-doped GaN layer can be 1000-1100 ℃, and the growth pressure is controlled within 200-600 torr. The obtained undoped GaN layer has better quality.
S204: and growing an n-type GaN layer on the high-temperature buffer layer.
Alternatively, the growth temperature of the n-type GaN layer may be 1000 to 1100 ℃, and the growth pressure of the n-type GaN layer may be 200 to 600 Torr.
Optionally, the thickness of the n-type GaN layer can be 2-3 um.
S205: and growing a light emitting layer on the n-type GaN layer.
The light emitting layer comprises a first composite layer and a second composite layer which are sequentially stacked on the n-type GaN layer, the first composite layer comprises a first GaN barrier layer, a first InGaN well layer and a second GaN barrier layer which are sequentially stacked on the n-type GaN layer, the second composite layer comprises a plurality of second InGaN well layers and third GaN barrier layers which are alternately stacked, the thickness of the first GaN barrier layer is smaller than that of the third GaN barrier layer, the thickness of the first InGaN well layer is larger than that of the second InGaN well layer, the thickness of the second GaN barrier layer is larger than or equal to that of the second InGaN well layer, and the thickness of the second GaN barrier layer is smaller than that of the third GaN barrier layer.
In step S205, when the first InGaN well layer is grown on the first GaN barrier layer, the growth time of the first InGaN well layer is divided into the time for introducing the In source and the time for stopping introducing the In source according to the time sequence. And continuously introducing the In source into the reaction cavity within the time of introducing the In source, and stopping introducing the In source into the reaction cavity within the time of stopping introducing the In source.
And when the first InGaN well layer grows on the first GaN barrier layer, dividing the time for introducing the In source and the time for stopping introducing the In source according to the time sequence. And stopping introducing the In source into the reaction cavity within the time of stopping introducing the In source, wherein the first InGaN well layer still can react and grow on the first GaN barrier layer, but the In content In the first InGaN well layer can be reduced, the lattice constant of the first InGaN well layer is closer to the lattice constant of a subsequently grown second GaN barrier layer, the crystal quality of the second GaN barrier layer grown on the first InGaN well layer is ensured, and In the first InGaN well layer is not easy to be separated out into the second GaN barrier layer to influence the crystal quality of the second GaN barrier layer.
Optionally, the growth time of the first InGaN well layer can be 2-4 min. The first InGaN well layer with a reasonable thickness range can be grown.
Illustratively, the time for stopping the In source can be 10-40 s.
The time for stopping leading In the source is 10-40 s, the obtained first InGaN well layer can be ensured to be capable of effectively capturing electrons, and the crystal quality of the second GaN barrier layer grown on the first InGaN well layer is good. The transition between the potential barrier of the first InGaN well layer and the potential barrier of the second GaN barrier layer is good, and more holes can smoothly enter the first InGaN well layer to perform composite light emission.
Alternatively, the ratio of the time for stopping the passage of the In source to the growth time of the first InGaN well layer is less than or equal to 1/10. At this time, the quality of the whole first InGaN well layer is better, and the crystal quality of the second GaN barrier layer grown on the first InGaN well layer is also better.
Optionally, in the light emitting layer, the growth temperature of the first InGaN well layer and the growth temperature of the second InGaN well layer may be 760 to 780 ℃, and the growth temperature of the first GaN barrier layer, the growth temperature of the second GaN barrier layer, and the growth temperature of the third GaN barrier layer may be 860 to 890 ℃. The quality of the luminescent layer grown under the condition is good, and the luminous efficiency of the light-emitting diode can be ensured.
S206: an electron blocking layer is grown on the light emitting layer.
Alternatively, the electron blocking layer may be Mg-doped AlyGa1-yN layers, wherein y ranges from 0.15 to 0.25. The effect of blocking electrons is better.
The growth thickness of the electron blocking layer can be 30-50 nm.
The growth temperature of the electron blocking layer can be 930-970 ℃, and the growth pressure of the electron blocking layer can be 100 Torr. The quality of the electron blocking layer grown under the condition is good, and the improvement of the luminous efficiency of the light-emitting diode is facilitated.
S207: and growing a p-type GaN layer on the electron blocking layer.
Alternatively, the growth pressure of the p-type GaN layer may be 200 to 600Torr, and the growth temperature of the p-type GaN layer may be 940 to 980 ℃.
The structure of the light emitting diode epitaxial wafer after step S207 is performed can be seen in fig. 2, and the thicknesses of the layers in the epitaxial layer are described in the light emitting diode epitaxial wafer shown in fig. 2, so the growth thicknesses of the layers in the epitaxial wafer are not described in detail in the structure shown in fig. 4.
It should be noted that, in the embodiments of the present disclosure, a VeecoK465iorC4 orrbmcvd (metalorganic chemical vapor deposition) apparatus is used to implement the growth method of the LED. By using high-purity H2(Hydrogen) or high purity N2(Nitrogen) or high purity H2And high purity N2The mixed gas of (2) is used as a carrier gas, high-purity NH3As an N source, trimethyl gallium (TMGa) and triethyl gallium (TEGa) as gallium sources, trimethyl indium (TMIn) as indium sources, silane (SiH4) as an N-type dopant, trimethyl aluminum (TMAl) as an aluminum source, and magnesium dicylocene (CP)2Mg) as a P-type dopant.
The above description is intended to be exemplary only and not to limit the present disclosure, and any modification, equivalent replacement, or improvement made without departing from the spirit and scope of the present disclosure is to be considered as the same as the present disclosure.

Claims (10)

1. A light emitting diode epitaxial wafer comprises a substrate (1) and an epitaxial layer (2) grown on the substrate (1), wherein the epitaxial layer (2) comprises an n-type GaN layer (21), a light emitting layer (22) and a p-type GaN layer (23) which are sequentially stacked on the substrate (1),
characterized in that the light emitting layer (22) comprises a first composite layer (221) and a second composite layer (222) which are sequentially laminated on the n-type GaN layer (21), the first composite layer (221) comprises a first GaN barrier layer (2211), a first InGaN well layer (2212) and a second GaN barrier layer (2213) which are sequentially laminated on the n-type GaN layer (21), the second composite layer (222) comprises a plurality of second InGaN well layers (2221) and third GaN barrier layers (2222) which are alternately laminated,
the thickness of the first GaN barrier layer (2211) is smaller than that of the third GaN barrier layer (2222), the thickness of the first InGaN well layer (2212) is larger than that of the second InGaN well layer (2221), the thickness of the second GaN barrier layer (2213) is larger than or equal to that of the second InGaN well layer (2221), and the thickness of the second GaN barrier layer (2213) is smaller than that of the third GaN barrier layer (2222).
2. The light emitting diode epitaxial wafer according to claim 1, wherein the thickness of the first GaN barrier layer (2211) is smaller than the thickness of the first InGaN well layer (2212).
3. The light emitting diode epitaxial wafer according to claim 1, wherein the thickness of the first InGaN well layer (2212) is smaller than the thickness of the third GaN barrier layer (2222).
4. The light emitting diode epitaxial wafer according to any one of claims 1 to 3, wherein the thickness of the first GaN barrier layer (2211) is 1 to 2.5nm, the thickness of the first InGaN well layer (2212) is 4 to 5.5nm, and the thickness of the second GaN barrier layer (2213) is 4.5 to 6 nm.
5. The light emitting diode epitaxial wafer according to any of claims 1 to 3, wherein the In content In the first InGaN well layer (2212) is reduced In a direction from the n-type GaN layer (21) to the p-type GaN layer (23).
6. A preparation method of a light emitting diode epitaxial wafer is characterized by comprising the following steps:
providing a substrate;
growing an n-type GaN layer on the substrate;
growing a light emitting layer on the n-type GaN layer, wherein the light emitting layer comprises a first composite layer and a second composite layer which are sequentially laminated on the n-type GaN layer, the first composite layer comprises a first GaN barrier layer, a first InGaN well layer and a second GaN barrier layer which are sequentially laminated on the n-type GaN layer, the second composite layer comprises a plurality of second InGaN well layers and third GaN barrier layers which are alternately laminated, the thickness of the first GaN barrier layer is smaller than that of the third GaN barrier layer, the thickness of the first InGaN well layer is larger than that of the second InGaN well layer, the thickness of the second GaN barrier layer is larger than or equal to that of the second InGaN well layer, and the thickness of the second GaN barrier layer is smaller than that of the third GaN barrier layer;
and growing a p-type GaN layer on the light emitting layer.
7. The method of claim 6, wherein the growth time of the first InGaN well layer is divided into In-source time and In-source stop time In time sequence when the first InGaN well layer is grown on the first GaN barrier layer,
and continuously introducing the In source into the reaction cavity within the time of introducing the In source, and stopping introducing the In source into the reaction cavity within the time of stopping introducing the In source.
8. The method for preparing the light emitting diode epitaxial wafer according to claim 7, wherein the growth time of the first InGaN well layer is 2-4 min.
9. The method for preparing the light-emitting diode epitaxial wafer as claimed In claim 7, wherein the time for stopping the In source is 10-40 s.
10. The method for preparing an epitaxial wafer for light emitting diodes according to claim 7, wherein the ratio of the time for stopping the In source to the growth time of the first InGaN well layer is less than or equal to 1/10.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10242512A (en) * 1997-02-24 1998-09-11 Toshiba Corp Semiconductor light emitting device
CN101459216A (en) * 2008-12-29 2009-06-17 上海蓝光科技有限公司 Bluelight LED in asymmetric multiple quanta pit structure and manufacturing process thereof
CN102903808A (en) * 2012-10-31 2013-01-30 合肥彩虹蓝光科技有限公司 Shallow quantum well growth method for increasing light emitting efficiency of GaN-based LED (Light-Emitting Diode)

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10242512A (en) * 1997-02-24 1998-09-11 Toshiba Corp Semiconductor light emitting device
CN101459216A (en) * 2008-12-29 2009-06-17 上海蓝光科技有限公司 Bluelight LED in asymmetric multiple quanta pit structure and manufacturing process thereof
CN102903808A (en) * 2012-10-31 2013-01-30 合肥彩虹蓝光科技有限公司 Shallow quantum well growth method for increasing light emitting efficiency of GaN-based LED (Light-Emitting Diode)

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