CN111865301A

CN111865301A - Synchronous compensation circuit of time-lag VCO

Info

Publication number: CN111865301A
Application number: CN201910346867.5A
Authority: CN
Inventors: 张伟林
Original assignee: Individual
Current assignee: Individual
Priority date: 2019-04-27
Filing date: 2019-04-27
Publication date: 2020-10-30
Anticipated expiration: 2039-04-27
Also published as: CN111865301B

Abstract

The technology provides a standardized design scheme of a high-resistance digital phase discriminator which is suitable for various different types and purposes and is used for a synchronous compensation synchronous control circuit aiming at a time-delay VCO group ring phase-locked loop, and the high-resistance digital phase discriminator has the following characteristics: 1. the control end signal is directly obtained from the output signal of the phase discriminator; 2. the maximum compensation bandwidth is limited by an artificially set bandwidth; 3. the actual compensation time width is limited by the maximum compensation time width and is controlled by a phase error signal output by the phase discriminator; 4. the time width of the positive phase compensation and the negative phase callback compensation are unequal; 5. and setting a compensation non-acting window, wherein the reverse phase callback compensation window is larger than the normal phase compensation window and is used as the period of the self-locking window of the phase-locked loop.

Description

Synchronous compensation circuit of time-lag VCO

Technical Field

The invention provides a standardized design of a synchronous control circuit with synchronous compensation function aiming at the time-lag VCO (voltage controlled oscillator) in a standardized design.

The phase detector used in the invention is a high-resistance digital phase detector provided in 'structural principle scheme of standardized design high-resistance digital phase detector' with patent application number 2015106449019, two input signals in the phase detector are marked as Wr and Wc, an output signal is marked as PDo, and two control end signal high-resistance state control signals INH and a phase difference detection signal a for outputting an interface circuit are arranged in the phase detector.

Background

The traditional time-lag VCO synchronous control circuit is composed of oscillation, adjustable frequency division, a phase discriminator PD, a loop filter LF, an adder, a driver, a time-lag VCO and initial setting shown in figure 1.

This technology is to patent application number: 2015106448853 synchronous control circuit for synchronous compensation type three-phase motor is mainly suitable for edge type phase detector group ring and phase-locked loop with heavy time lag characteristic to be adapted to design change of high resistance type phase detector group ring phase-locked loop. However, the phase detector that is easy to compensate is still considered by the designer to be the one described in patent application No.: 2015106844003 new design method of edge-type high-resistance digital phase discriminator and patent application number: 2018115280200 edge-type high-resistance digital phase detector suitable for time-lag VCO group ring.

Disclosure of Invention

The block diagram of the skew VCO synchronization compensation circuit shown in fig. 2 includes core technologies, including:

a. a forming technology of synchronous compensation pulse original signals;

b. a technology for forming the maximum compensation time width of the synchronous compensation pulse signal;

c. the limited time width forming technology of the swallowed synchronous compensation pulse signal for the requirement of the autonomous synchronous time width;

d. The forming technology of the time width of the actual effective synchronous compensation pulse signal.

Drawings

Fig. 1 is a block diagram of a conventional skew VCO synchronization control circuit, in which symbols and functions are described as follows:

a. oscillation of label 1: the square wave is generated by a crystal oscillator and other oscillators with higher stability, and the square wave is subjected to adjustable frequency division by a mark 2: and after frequency division adjustment, a square wave of a reference frequency is generated and is connected to the Wr input end of the PD phase discriminator of the identifier 3 to generate positive phase jump.

b. The output of the phase detector is filtered by the inverse LF of the identifier 4, for example, the active integration loop filter, and then added to the adder "-" of the identifier 5, i.e., the negative phase terminal, where a port is added for accessing the output of the synchronous compensation circuit of the present technology, and after being set and synthesized with the initial value of the identifier 8 loaded at the adder "+" i.e., the positive phase terminal, the synthesized signal is applied to the driver of the identifier 6 as the VCO control terminal signal. The frequency control output of the skew-type VCO of reference 7 is formed under the controlled control of the driver, and the output signal thereof is fed back to the Wc input terminal of the phase detector.

FIG. 2 is a block diagram of the synchronization compensation circuit of the present invention, in which the symbols and functions are illustrated as follows:

the phase discriminator with 1 mark 1 is the phase discriminator in the phase locked loop of the compensation object of the technology, and the two control end signals INH and a in the phase discriminator for outputting the interface circuit are the two input signals of the technology

2-labeled 3 inverter is a control terminal signal for changing INH active to INH inactive signal for one of the techniques

3 and gate marked 2 is a digital multiplier, and forms an autonomous working window period of compensation object phase-locked loop

Delay of 4, i.e. delay t0 of INH invalid signal to form working time of a compensation object phase-locked loop autonomous working window period

5-mark 5 monostable trigger oscillator with time width T0 as basic compensation time width T0-T0 of the technology

6-mark 6 delay forms a pressed/swallowed time width t1

The digital adder with 7 marks is an OR gate, and the width of the basic compensation is compressed to form a compensation width T0+ T1-T0

8, the inversion of 8, i.e. the inversion of the input signal, complies with the specification of the VCO control end signal

9 the digital multiplier of sign 9 is an and gate, and the time-covering time forms a compensation time width T0-T1-T0

The 10 mark 10 is a two-way selector with an original model of HC4053, the control end signal is an a control end signal in the input signal of the phase detector in the technology, when a = "H", a signal with the maximum compensation time width of T0+ T1-T0 is sent, and when a = "L", a signal with the maximum compensation time width of T0-T1-T0 is sent

11, the digital multiplier, labeled 11, is an and gate that cuts the end of the compensation signal to the end of the INH invalid signal.

Several supplementary notes

a. The technical description contents applied to a synchronous compensation type three-phase motor synchronous control circuit in the technology are subject to the relevant contents in the element;

b. for convenience of explanation, a prototype circuit of the conventional edge type high-resistance phase detector HC4046 is used as a phase detector, and the operation characteristic of the phase detector is that the phase detector changes in the output direction of the "H" state under the action of the Wr edge signal and changes in the output direction of the "L" state under the action of the Wc edge signal, and a high-resistance state is separated between the two output states in the changing direction. One of the high impedance states is an initial state, the flip-flop returns to the initial state after being reset, and the two input signals return to the initial state when being synchronous signals. The phase detector has two working initial states, wherein one of the two working initial states is an H state if Wr signals exist and no Wc signals exist, and the other working initial state is an L state if Wc signals exist and no Wr signals exist.

Detailed Description

Firstly, the phase-locked loop is in a mode of a phase detector working initial state without the VCO, the output signal of the phase detector is in an 'H' state, the work of the synchronous compensation circuit of the invention is started, and a time T0 after the synchronous starting time is stopped at the stopping time of the maximum compensation time width T0+ T1. Once the VCO is connected, although the output signal of the phase detector is in an 'H' state, the VCO is a time-lag VCO, asynchronous output signals have delay, the working period of the VCO output signal at the moment is still larger than that of a reference signal, and the output of the phase detector is continuously maintained to be not full-state output but an 'H' state signal with shortened time width. If the time width of the output 'H' state signal is larger than t0, the synchronous compensation circuit of the invention is started to work, and the synchronous start time is also a time t0 after the synchronous start time, and the end time is determined by the INH invalid signal with priority; otherwise, the synchronous compensation circuit of the invention can not be started and the phase-locked loop enters into the autonomous synchronous operation.

Secondly, the work period of the VCO output signal is continuously shortened along with the action of the H-state output signal of the phase detector. Because the time lag of the VCO at the moment can generate an overcompensation phenomenon, namely the work period of the VCO is smaller than that of the reference signal, and the output of the phase discriminator jumps to output an L-state signal. If the time width of the output 'L' state signal is larger than T0+ T1, the synchronous compensation circuit of the invention is started to work, and similarly, the synchronous start time is one time T0+ T1 later and the end time is determined by the INH invalid signal with priority, but the maximum end time is T0; otherwise, the synchronous compensation circuit of the invention can not be started and the phase-locked loop enters into the autonomous synchronous operation.

Finally, after repeated adjustment for many times until the time width of the output H state signal is less than t0 and the time width of the output L state signal is less than t0+ t1, the phase-locked loop enters the autonomous synchronous working mode.

Some specifications for operation of different phase detector group rings

One phase discriminator is an edge type high-resistance phase discriminator which is the same as HC4046, and has the characteristic that input and output signals work synchronously at the same frequency under the locking state of a general phase-locked loop; meanwhile, the two working initial states of the phase discriminator have two different working modes of maintaining the non-high impedance state unchanged and continuously switching the non-high impedance state and the high impedance state, although the actual output of the phase discriminator is the same and is in the non-high impedance state; however, the phase locked loops of different sets of phase detectors have different operating characteristics.

For example, in a new design method of an existing edge type high-resistance digital phase detector with the patent application number of 2015106844003, when the output state of the phase detector is in the 'H' state or the 'L' state, the output state of the phase detector returns to the high-resistance state as long as an input signal edge triggers when the basic type of the phase detector is output; the phase discriminator in the high-resistance state outputs an 'H' state if the Wr edge arrives, outputs an 'L' state if the Wc edge arrives, and returns to a high-resistance state form of an initial state if the synchronous signal arrives; meanwhile, if the synchronous signals of the two input signals arrive, the phase detector in the 'H' state or the 'L' state can generate output which is directly jumped to the 'L' state or the 'H' state without passing through a high impedance state.

If the phase detector adopts the preposed reset technology provided in the brand new edge type high-impedance digital phase detector with the patent application number of 2015106462973, the phase detector in the 'H' state or the 'L' state is changed, and if the synchronous signals of two input signals reach, the output of directly jumping to the 'L' state or the 'H' state without passing through the high impedance state can occur. In order to return to the initial state, the working modes of other phase detectors are kept unchanged, and the phase detector in the brand-new edge type high-resistance digital phase detector also has the same working mode.

For example, when the output state of the phase detector in the edge type high-resistance digital phase detector suitable for the time-lag type VCO (voltage controlled oscillator) group ring with the patent application number of 2018115280200 is in L-state output, the output state of the phase detector returns to a high-resistance state as long as an input signal edge triggers; when the output state of the phase discriminator is in the H state output, if the Wr edge arrives, the output state is maintained unchanged, and only if the Wc edge arrives, the output state returns to the high impedance state; meanwhile, the synchronous signal returns to the initial state when arriving in any state.

A phase discriminator is a level type high-resistance phase discriminator, which is different from an edge type high-resistance phase discriminator and is always a single pulse signal in the output signal period of the phase discriminator, and the level type high-resistance phase discriminator is always two pulse signals in two directions in pair in the output signal period of the phase discriminator; the input and output signal relationship has both the same frequency and frequency multiplication relationship, and the two input signals in the locking state have the asynchronous relationship of inversion, orthogonality and the like besides the synchronous relationship; besides two different working modes of maintaining the non-high impedance state unchanged and continuously switching the non-high impedance state and the high impedance state, the two working initial states of the phase discriminator also have a third state that the actual output is between two power supply potentials. However, the phase-locked loop has a combination of five different modes of a high impedance state and supply potential compensation in each period of the output signal of the phase detector during the working process.

In summary, based on the structure principle scheme of the standardized design high-resistance digital phase detector of patent application No. 2015106449019, the standardized design scheme of the synchronous control circuit with synchronous compensation function can be realized by the standardized design of the time-lag VCO.

Claims

1. A suitable object phase detector is one that is in accordance with patent application No.: 2015106448849, the high impedance state control signal INH and the phase difference detection signal a generated by the structural principle scheme of the standardized design high impedance type digital phase discriminator are provided to the patent application number: 2015106448849 Standard interface Circuit of high resistance digital phase discriminator output stage and patent application No.: 2017104018440 Standard interface circuit of high-resistance phase discriminator output level non-FET switch class, a kind of edge-triggered high-resistance phase discriminator using output interface circuit as characteristic, for a kind of phase-locked loop application by time-lag VCO group ring, add an incoming end to the negative phase terminal of the adder that is the compression shifter between LF and VCO accuse end in the original general type synchronous control phase-locked loop circuit, the signal that has the synchronous compensation effect that inserts this technology provides, its characterized in that includes: three digital multipliers, two delayers, two inverters, a digital adder, a monostable trigger oscillator and two selectors; the INH signal is converted into a control end signal of the device through an inverter, when the control end signal is effective, a monostable trigger oscillator is triggered through digital multiplication of an original path signal and a signal with time delay T0, a basic compensation signal with time width T0, namely time width T0-T0, is swallowed at the starting moment, the basic compensation signal is divided into two paths, one path is the original path signal, and the other path is output after being delayed by T1; one path of the two basic compensation signals is used as a maximum negative phase compensation signal in the phase discriminator output after digital multiplication, the time width is T0-T0-T1, and the swallowed time width T0+ T1 is used as the self-synchronization time width of the negative phase signal of the phase-locked loop; the other path of the two basic compensation signals are converted into the maximum normal phase compensation signal of the phase-locked loop through an inverter after digital addition, the time width is T0-T0+ T1, and the swallowed time width T0 is the autonomous synchronous time width of the normal phase signal of the phase-locked loop; the maximum positive phase compensation signal is input to the '1' input end of one two-way selector, the maximum negative phase compensation signal is input to the '0' input end of the other two-way selector, the output control signal of the two-way selector is the phase difference detection signal a, the output signal and the control end signal of the two-way selector are digitally multiplied to form a final compensation signal, the maximum termination time relative to the time width of the reference is the time width of a non-INH effective signal, and the final compensation signal is connected to the connecting end additionally arranged on the compression shifter.