JPH08191245A - Pll circuit - Google Patents

Abstract

PURPOSE: To expand a frequency range capable of solving and locking operation instability due to the feedback of both loops in a PLL circuit having a double loop for solving a clock skew. CONSTITUTION: The PLL circuit is provided with a pulse input terminal 21, a pulse output terminal 23 and 1st and 2nd loops 25, 27. The 1st loop 25 is constituted of a frequency difference/voltage conversion circuit(FDVC) connecting one input terminal i1 to a pulse input terminal 21 and connecting the other input terminal i2 to the output terminal of a voltage controlled oscillator(VCO) and the VCO connecting its control terminal to the output terminal of the FDVC. The 2nd loop 27 is constituted of a phase difference/voltage conversion circuit(PDVC) connecting one input terminal i1 to the terminal 21 and connecting the other input terminal i2 to a pulse output circuit 23 and a delay circuit 27a consisting of a voltage controlled delay circuit(VCD) controlled by an output from the FDVC connected to the terminal 21 and a voltage controlled phase shifter(PS) connected to the VCD and controlled by an output from the PDVC.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL used for reducing the skew of an input pulse such as an input clock.
It is about circuits.

[0002]

2. Description of the Related Art A PLL circuit having a double loop has been proposed as a PLL circuit capable of achieving both high-speed pull-in and jitter reduction. An example of the configuration is disclosed in, for example, the literature (A-I-A-Transaction on Communication (IEEE TRANS)).
ACTIONS ON COMMUNICATIONS), VOL.COM-27, NO.9, SEP.197
9, pp.1288-1295). As shown in FIG. 18, this configuration example includes a first loop 11 having a frequency difference detection circuit FDD, a charge pump and a low pass filter LPF, and a second loop 11 having a phase difference detection circuit PDD, a charge pump and a low pass filter LPF. Loop 13 of
It was provided with an adder 15 into which the outputs of both loops are input, and a voltage controlled oscillator 17 controlled by the output voltage of the adder 15, and operated as follows. During the period when the frequency difference between the input clock CKIN and the output clock CKOUT is large, the first loop 11 mainly performs the high-speed pull-in operation. When the frequency difference becomes small, the second loop 13 ensures accurate phase synchronization. As a result, both high-speed pull-in and jitter reduction can be achieved.

[0003]

However, as shown in FIG.
In the conventional PLL circuit described by using the first loop 11 and the second loop, a portion from the control voltage input terminal VC of the VCO 17 to each input of the frequency difference detection circuit FDD and the phase difference detection circuit PDD via the VCO 17 is described. Since the loop 13 is shared, the following problems (1) to (4) occur.

Since the two loops 11 and 13 influence each other, the operation of the PLL circuit becomes unstable. : There is a case where the jitters in the two loops 11 and 13 are synergized to increase the jitter of the entire PLL circuit. : The state of one loop is fed back to the other loop via the other loop. That is, there is parasitic multiple feedback. These problems make it difficult to design for stable operation of the PLL circuit, and therefore improvement is desired.

The conventional PL described with reference to FIG.
In the L circuit, since the voltage controlled oscillator VCO is operated while also adjusting the phase, the PL of the type used to operate the VCO only by adjusting the frequency.
Compared with the L circuit, the phase control can be performed with high accuracy, but there is a problem that the frequency range in which locking is possible is narrow. Although not described in the section of the prior art, there is a so-called delay locked loop PLL circuit including a phase difference voltage conversion circuit and a phase shifter.
This PLL circuit is known to be capable of obtaining a clock with a small phase error and a small amount of jitter, but the lockable frequency range is narrower than that shown in FIG.

In order to further utilize the PLL circuit, for example, it is desired to solve the following problems. First, there is a demand for a technique capable of increasing the maximum operating frequency even for a PLL circuit having a double loop in order to cope with the increase in the operating speed of an electronic circuit. Also, a PLL having a double loop
The circuit is generally realized as a semiconductor integrated circuit, but a structure suitable for high integration is desired even for a PLL circuit having a double loop in order to cope with high integration of the semiconductor integrated circuit.

[0007]

Therefore, according to the PLL circuit of the present invention, the following components (a) to (d) are provided in order to enable stable operation and expand the frequency range in which locking is possible. It is characterized by having

(A). Pulse input terminal for inputting single or complementary input pulse.

(B). A pulse output end that outputs a single or complementary output pulse related to the input pulse.

(C). One input terminal is connected to the pulse input terminal, the other input terminal is connected to the output terminal of the voltage controlled oscillator, and at least the frequency difference between the signals input to these one and the other input terminals is converted into a voltage. A first loop including a frequency difference voltage conversion circuit and a voltage controlled oscillator having a control terminal connected to an output terminal of the frequency difference voltage conversion circuit.

(D). One input end is connected to the pulse input end, the other input end is connected to the pulse output end, and at least the phase difference between the signals input to these one and the other input ends is detected and converted into a voltage. A phase difference voltage conversion circuit, and an input end connected to the pulse input end,
A voltage control delay circuit having a control terminal connected to an output terminal of the frequency difference voltage conversion circuit included in the first loop, for controlling a delay time of an input signal by an output voltage of the frequency difference voltage conversion circuit; The input end is connected to the output end of the voltage controlled delay circuit, the control terminal is connected to the output end of the phase difference voltage conversion circuit, the output end is connected to the pulse output end, and the phase of the input signal is And a delay circuit including a voltage control phase shifter controlled by the output voltage of the phase difference voltage conversion circuit.

In the present invention, the connection means the case where they are directly connected to each other and, if necessary, other circuit elements,
For example, both cases are indirectly connected through circuit elements such as means for compensating for the offset of the phase error and buffer means for improving the output drive capability.

In the present invention, instead of the delay circuit, a delay circuit having a plurality of stages of delay cells having first and second control terminals is connected, the input end of which is the pulse input end. The output terminal of the delay cell is connected to the output terminal of the frequency difference voltage conversion circuit included in the first loop, Each of the second control terminals may be provided with a delay circuit connected to the output terminal of the phase difference voltage conversion circuit included in the second loop.

Alternatively, instead of any of the above delay circuits,
A second voltage controlled oscillator having a control terminal connected to an output terminal of the frequency difference voltage conversion circuit in the first loop; and an input terminal connected to an output terminal of the second voltage controlled oscillator,
The control terminal is connected to the output end of the phase difference voltage conversion circuit in the second loop, the output end is connected to the pulse output end, and the phase of the input signal is controlled by the output voltage of the phase difference voltage conversion circuit. It is also possible to provide an oscillating circuit section composed of a voltage control phase shifter for

Alternatively, in place of any one of the delay circuits or the oscillation circuit units described above, an oscillation circuit unit is configured by connecting a plurality of stages of delay cells having first and second control terminals, and each delay circuit is provided. Each of the first control terminals of the cell is connected to the output terminal of the frequency difference voltage conversion circuit included in the first loop, and each of the second control terminals of the cell is connected to the output terminal of the phase difference voltage conversion circuit included in the second loop. An oscillator circuit section connected to the output terminal may be provided.

Further, according to the PLL circuit of the present invention, the stable operation is enabled, the frequency range in which locking is possible is expanded, and the maximum operating frequency is increased, so that the configurations (a) to (d) described above are used. (However, the configuration of (d) may be the configuration including the replaced delay circuit or oscillation circuit section.) In addition to the one input end of the frequency difference voltage conversion circuit included in the above (c). It is characterized in that a frequency dividing circuit is further provided as a new component between the pulse input terminal (a) and the pulse input terminal (a). In the configuration of (d) above, when using the oscillation circuit section including the second voltage controlled oscillator and the voltage controlled phase shifter, the one input end and the pulse input end of the frequency difference voltage conversion circuit are used. In addition to or in place of the configuration in which the frequency divider circuit is provided between the pulse output terminal and the pulse output terminal of the phase difference voltage conversion circuit, A circuit may be provided.

According to the PLL circuit of the present invention, stable operation is possible, the frequency range in which locking is possible is expanded, and the degree of integration is improved when the PLL is built in a semiconductor substrate. The configuration of (a) to (d) described above (however, the configuration of (d) may be a configuration including the replaced delay circuit or oscillation circuit section) and
Furthermore, when the low-pass filter including the low-pass filter is used as the frequency difference voltage conversion circuit included in the configuration of (c), the low-pass filter is connected to the first resistance means and the first resistance means. A second resistance means and a capacitance means connected in series between a terminal on the side opposite to the terminal connected to the input terminal and a reference potential, and the first resistance means and the second resistance means. The connection point of the resistance means is used as the first output terminal, and the connection point of the second resistance means and the capacitance means is used as the second output terminal.

[0018]

According to the invention having the above-mentioned components (a) to (d) (however, the configuration of (d) includes a configuration including a replaced delay circuit or oscillation circuit section). , The first loop is locked at the frequency of the input pulse. At this time, the frequency difference voltage conversion circuit of the first loop supplies a constant voltage corresponding to the locked state (corresponding to the frequency of the input pulse) to the voltage control delay circuit of the second loop or the control terminal of the second voltage control oscillator. Output to. This constant voltage controls the delay time of the voltage-controlled delay circuit or the second voltage-controlled oscillator, so that the voltage-controlled delay circuit or the second voltage-controlled oscillator is a pulse having the same frequency as the input pulse and having a phase difference. Is output. Further, this phase difference is controlled in the second loop so that there is no phase difference with respect to the input pulse. That is, since the frequency is adjusted in the first loop and the resulting voltage is given to the second loop to adjust the phase, the first loop is used as the master and the second loop is used. A PLL circuit that operates as a master and a slave is realized.

Further, in the configuration in which the frequency dividing circuit is provided between the input terminal and the pulse input terminal of the frequency difference voltage converting circuit, the frequency difference voltage converting circuit is operated at a frequency of 1 / k with respect to the frequency of the input pulse. Can be done. This is a frequency difference voltage conversion circuit (details will be described later) of 1 / k of the frequency f of the input pulse, which is said that the operating frequency of the entire circuit cannot be increased so much because one operation period is long. It means that the input pulse handled by the PLL circuit can be k times the input pulse when the frequency divider circuit is not provided, so that the operating frequency of the entire PLL circuit can be improved. Further, in the case where the oscillation circuit section is used instead of the delay circuit in the second loop, the frequency division circuit is provided between the input terminal of the oscillation circuit section and the pulse output terminal in the second loop. Since an output pulse having a frequency that is k times the frequency of the pulse is obtained, in this case as well, P
The operating frequency of the LL circuit can be improved.

Further, the frequency difference voltage conversion circuit includes a low-pass filter, and the low-pass filter has the first resistance means, the second resistance means, and the capacitance means arranged in a predetermined arrangement, which is different. It is possible to realize two types of low-pass filters having a transfer characteristic by sharing the resistance means and the capacitance means. If the resistance means and the capacitance means can be shared when they are formed in the semiconductor substrate, the area occupied by these means in the semiconductor substrate can be reduced. Therefore, even when two types of low-pass filters having different transfer characteristics are configured so that the characteristics of the PLL circuit can be easily optimized, the degree of hindrance to high integration is reduced.

[0021]

Embodiments of the PLL circuit of the present invention will be described below with reference to the drawings. However, the drawings used for the explanation are shown schematically so that the present invention can be understood. Further, in each of the drawings used for the description, the same components are denoted by the same reference numerals, and the duplicate description may be omitted.

1. First Embodiment FIG. 1 shows a PLL circuit having a double loop of the present invention (hereinafter, referred to as “PLL circuit”).
Also called a PLL circuit. 2) is a block diagram for explaining the first embodiment of FIG. The PLL circuit 20 shown in FIG. 1 shows an example in which a single clock CKIN is used as an input pulse.

The PLL circuit 20 of the first embodiment has a pulse input end 21, a pulse output end 23, a first loop 25, and a second loop 27.

The pulse input terminal 21 can be constituted by an input terminal to which the clock CKIN is input as a single input pulse in this case. In addition, the pulse output terminal 23 has a clock CK.
Clock CK as a single output pulse associated with IN
It can be composed of an output terminal for outputting OUT.

The first loop 25 comprises a frequency difference voltage conversion circuit FDVC and a voltage controlled oscillator VCO. The frequency difference voltage conversion circuit FDVC converts the frequency difference between the signals input to the input terminals i1 and i2 of the frequency difference voltage conversion circuit FDVC into a voltage. Further, the voltage controlled oscillator VCO has its oscillation frequency controlled according to the voltage VCf input to the control terminal VC. Then, in the first loop 25, the frequency difference voltage conversion circuit FDVC
One input terminal i1 is connected to the pulse input terminal 21 and the other input terminal i2 is connected to the output terminal o of the voltage controlled oscillator VCO. Further, the frequency difference voltage conversion circuit FDVC
Output terminal o of the control terminal VC of the voltage controlled oscillator VCO
Although described later in detail, they are respectively connected to the first control terminal VC1 in the second loop 27 (actually the control terminal VC of the voltage control delay circuit VCD via this VC1). A detailed configuration example of these FDVC and VCO will be described later.

The second loop 27 is composed of a phase difference voltage conversion circuit PDVC and a delay circuit 27a. The phase difference voltage conversion circuit PDVC has an input terminal i1 included therein.
And the phase difference between the signals input to i2 is converted into a voltage. The delay circuit 27a controls the delay time until the signal input here is output and also controls the phase. In this case, the delay circuit 27a is composed of the voltage control delay circuit VCD and the voltage control phase shifter PS. I am doing it. Further, in the second loop 27, one input end i1 of the phase difference voltage conversion circuit PDVC is connected to the pulse input end 21 and the other input end i2 is connected to the pulse output end 23, respectively. Furthermore, the phase difference voltage conversion circuit PD
The output terminal o of VC is connected to the control terminal C of the voltage control phase shifter PS in the delay circuit 27a. Further, the pulse input terminal 21 is connected to the voltage control delay circuit VC of the delay circuit 27a.
It is also connected to the input terminal of D. The output end o of the voltage control delay circuit VCD is connected to the input end i of the voltage control phase shifter PS, and the output end o of the voltage control phase shifter PS is connected to the pulse output end 23 and the phase difference voltage conversion circuit PDVC. Is connected to the other input end i2.

Next, the frequency difference voltage conversion circuit FDV described above.
C, phase difference voltage conversion circuit PDVC, voltage controlled oscillator VC
A detailed configuration example of the O and delay circuit 27a will be described.

The frequency difference voltage conversion circuit FDVC includes, for example, a frequency difference detection circuit FDD, a charge pump (charge pump circuit) 25x, and a low pass filter LPFf.
Can be configured with, and this embodiment does so. The phase difference voltage conversion circuit PDVC includes, for example, a phase difference detection circuit PDD and a charge pump (charge pump circuit) 27.
x and the low-pass filter LPFp, which is also the case in this embodiment. Here, the frequency difference detection circuit FD
D, phase difference detection circuit PDD, charge pumps 25x, 2
Each of the 7x and the low-pass filters LPFf and LPFp can be configured by various known circuits, but specific examples are as follows.

As an example of the configuration of the frequency difference detection circuit FDD, for example, a circuit using D-type flip-flops 31a and 31b and a NOR gate 31c as shown in FIG. 2A can be cited. As an example of the configuration of the phase difference detection circuit PDD, for example, as shown in FIG.
Type flip-flop circuit 32a and AND gate 32
A circuit using b and 32c can be mentioned. As an example of the configuration of each of the charge pumps 25x and 27x, for example, constant current sources 33a and 33x as shown in FIG.
b, PMOS field effect transistor 33c and NMOS
A circuit using the field effect transistor 33d and the inverter 33e can be given. Low pass filter L
As a configuration example of each of PFf and LPFp, for example, a circuit using the first resistance means R ₁ , the second resistance means R ₂ and the capacitance means CL ₁ as shown in FIG. You can Since each of the circuits shown in FIGS. 2A to 2D is disclosed in various documents, the description of the operation thereof will be omitted here.

The frequency difference detection circuit FDD shown in FIG. 2A has a structure capable of detecting a phase difference as well.
Although the conversion gain is high compared to a known circuit (FV converter) that detects only the frequency difference, the conversion gain is small, but such a circuit can also be used as the frequency difference detection circuit in the present invention. This is because by adjusting the characteristic of the low-pass filter LPFf connected to the subsequent stage of the frequency difference detection circuit FDD, it is possible to obtain the same characteristic as the circuit that detects only the frequency difference.

The voltage controlled oscillator VCO is, for example,
An n-stage delay cell DLC1 as shown in FIG.
Inverter IN connected to the output o of the delay cell in the nth stage
V35 and a well-known ring oscillator in which the output of the inverter INV35 is fed back to the delay cell of the first stage, and this example also does so. Here, n is a positive integer determined according to the design. Here, each delay cell DLC1 is composed of, for example, a circuit using an inverter, an NMOS transistor NTR1, and a capacitor C1 as shown in FIG. 3B. In the configuration of the voltage controlled oscillator VCO shown in FIG. 3, the oscillation frequency is controlled by the voltage applied to the control terminal C of the delay cell DLC1.

As an example of the configuration of the voltage control delay circuit VCD provided in the delay circuit 27a, the circuit of FIG. 4 can be cited, for example. A voltage controlled delay circuit VCD configured by cascade-connecting (2n + n / 2) stages of delay cells DLC1 to the voltage controlled oscillator VCO configured by n stages of delay cells. In this voltage control delay circuit VCD, the control terminal C of each delay cell DLC1 is commonly connected to the control terminal VC1 of the voltage control delay circuit VCD.
Further, the output terminal o of the delay cell DLC1 of the (2n−n / 2) th stage is connected to the output terminal o1 of the voltage controlled delay circuit VCD,
The output terminal o of the second delay cell DLC1 is the output terminal o2 of the voltage controlled delay circuit VCD, and the output terminal o of the (2n + n / 2) th delay cell DLC1 is the output terminal o3 of the voltage controlled delay circuit VCD. To each of them. Then, these output terminals o1 of the voltage control delay circuit VCD
To o3 are respectively connected to the corresponding input terminals i1 to i3 of the voltage control phase shifter PS (details will be described later). That is, the voltage control delay circuit VCD and the voltage control phase shifter P in the delay circuit 27a in the case of this embodiment.
The connection to S should be understood as a bus description. Note that the number of outputs of the voltage control delay circuit VCD (the number of inputs of the corresponding voltage control phase shifter PS) is not limited to the above three, and it depends on the design (for example, depending on the phase control width) 1 Alternatively, it can be plural other than 3.

The voltage control phase shifter PS, which is the other component of the delay circuit 27a, is used in various circuits, for example, in Document II (IE General Off-Slot State Circuit (IE).
EE, J.of Solid-State Cirduits), Vol.27, No.12, pp.1747
-1751), etc. by the differential type circuit disclosed in
For example, it can be configured by the circuit described below with reference to FIG. The voltage controlled phase shifter shown in FIG. 5 has a first input terminal i1 connected to the output terminal o1 of the voltage controlled delay circuit VCD and an output terminal o of the voltage controlled delay circuit VCD.
2 and a third input terminal i2 connected to the output terminal o3 of the voltage controlled delay circuit VCD.
3, reference voltage input terminal VREF, and buffer means B5
1 to B56 and transfer gates T51 to T56
And a differential type buffer means OP. The buffer units B51 to B56 have gains of 1 to
2 Low and small amplifier. The differential type buffer means OP is also composed of a differential type amplifier having a small gain, like the buffer means B51 and the like. In the voltage-controlled phase shifter PS having the configuration shown in FIG. 5, the combined waveform of the waveform of the input terminal i1 with the advanced phase and the waveform of the reference signal of the input terminal i2 having the phase of 0 ° is the node N51 in FIG. Obtained in. In addition, a composite waveform of the waveform of the input terminal i2 and the waveform of the input terminal i3 whose phase is delayed is a node N52 in FIG.
Obtained in. Similarly, the waveform at the node N51 and the waveform at the node N52 are combined at the output terminal o. Since this is done, the phase of the waveform at the output terminal o can be controlled by the voltage at the control terminal C of the voltage control phase shifter PS. A loop using such a voltage control phase shifter PS becomes a primary loop.

Next, in order to deepen the understanding of the PLL circuit 20 of the first embodiment, its operation will be described.

The PLL circuit 2 of the first embodiment shown in FIG.
At 0, the first loop 25 is the same as the PLL circuit of a general secondary loop, so that the frequency of the input pulse applied to the pulse input terminal 21 is between the clock CKIN and the output o of the voltage controlled oscillator VCO. If there is a difference, the normal pulling operation, that is, the output of the VCO is the clock CKI.
It operates so that the frequency matches the frequency of N. As a result, the frequency difference voltage conversion circuit F in the first loop 25
The output VCf of the DVC has a constant voltage value. This voltage V
Cf is a voltage control delay circuit VC in the second loop 27
It is also input to D.

Here, the voltage controlled oscillator VCO is shown in FIG.
In the case of the circuit having the configuration shown in (A), the phase of the signal is the inverter INV35 provided in the voltage controlled oscillator VCO.
Considering that the signal is rotated by 180 °, the phase of this signal is further increased by 180 ° by the n-stage delay cell DLC1.
I will turn around. That is, the cycle T of the clock CKIN
On the other hand, the delay time of the signal in each delay cell DLC1 is T
/ 2n.

On the other hand, the delay circuit 27a of the second loop 27
In this case, the voltage-controlled delay circuit VCD in FIG. 2 has a plurality of delay cells DLC1 similar to those used in the voltage-controlled oscillator VCO in the first loop 25, specifically (2n + n /
2) The control terminal VC has a stepped configuration, and the control terminal VC has the same voltage VCf as the voltage input to the control terminal of the voltage controlled oscillator VCO, as described above.
Given as. Therefore, this voltage control delay circuit VC
At the output of the delay cell DLC1 at the 2n-th stage of D, that is, at the output terminal o2 in FIG. 4, a clock of phase 0 ° delayed by one cycle T from the input terminal i (see FIG. 4) is obtained. Further, in this voltage control delay circuit VCD, a clock whose phase is shifted by 90 ° is obtained every n / 2 stages. These clocks are input terminals i1 to i3 of the voltage control phase shifter PS.
(See FIG. 5) respectively and combined in this voltage controlled phase shifter PS as already described. Therefore, in the voltage control phase shifter PS, the phase of the output signal (clock CKOUT) depends on the voltage VCp (see FIG. 1) input to the control terminal of the voltage control phase shifter PS regardless of the frequency of the input signal. , -90 °
It can be controlled in the range of 90 °. In addition, this voltage VCp
Is the phase difference voltage conversion circuit PD in the second loop 27.
Depending on VC, clock CKIN and clock CKOUT
It is controlled so that there is no phase difference with. Therefore, the voltage control phase shifter PS has a clock CKOU that has no phase difference with respect to the clock CKIN (of course the same frequency).
It will output T.

As described above, in the PLL circuit 20 of the first embodiment, the basic delay of the delay circuit 27a in the second loop 27 is promptly increased in the cycle of the clock CKIN by the pull-in operation of the first loop 25 of the secondary system. In addition, the phase of the clock CKOUT is accurately matched to the phase of the clock CKIN by the second loop 27 of the primary system. Therefore, while maintaining high phase accuracy, the response of the first loop 25 can be speeded up to achieve high-speed pull-in. Also, the output voltage V of the first loop 25
Since Cf is configured to be referred to from the second loop 27, there is no feedback path from the second loop 27 to the first loop 25, so that a PLL circuit that performs a complete master slave operation can be realized. . Therefore, the conventional technique in which the first and second loops have a shared portion (see FIG. 18).
The problem that occurs in :), the problem that the operation is unstable, the problem that the jitter may increase due to the synergistic effect of the jitters of the first and second loops, and the problem that the parasitic multiple feedback occurs , PL of this first embodiment
It can be prevented by the L circuit. Further, since the first loop 25 adjusts the frequency and the second loop 27 adjusts the phase, it is possible to provide a PLL circuit capable of frequency locking and having a wide frequency range.

2. Second Embodiment In the above-described first embodiment, the delay circuit 27a including the voltage control delay circuit VCD and the voltage control phase shifter PS is used as the delay circuit. However, the configuration of the delay circuit is not limited to the example of the first embodiment, and other configurations may be used. This is because the degree of freedom in circuit design is improved in some cases, which is convenient. This second embodiment is such an example. This description will be given with reference to FIGS.

In the PLL circuit of the second embodiment, as shown in FIG.
As shown in (B), the first and second control terminals vc1
In the delay circuit 27b in which a plurality of delay cells DLC2 having vc2 and vc2 are connected in series here, 2n stages, the input terminal i of which is the pulse input terminal 21 as shown in FIG. 6 (A). Connected, and its output end o is the pulse output end 23
The first control terminal vc1 of each delay cell DLC2 is connected to the first control terminal V of the delay circuit 27b.
It is connected to the output terminal o of the frequency difference voltage conversion circuit FDVC included in the first loop 25 via C1, and the second control terminal vc2 of each delay cell is connected to the output terminal o of the delay circuit 27a via the second control terminal VC2 of the delay circuit 27a. A delay circuit 27b connected to the output terminal o of the phase difference voltage conversion circuit PDVC included in the second loop 27 is provided instead of the delay circuit 27a in the first embodiment. The delay cell DLC2 may have any suitable configuration, but in the second embodiment, the drive circuit unit 61 is used.
And the load circuit section 63 is used as the delay cell as shown in FIG. That is, the delay cell DLC
2 is provided with an inverter INV as a drive circuit unit 61 provided between an input end i and an output end o of the same, and further as a load circuit unit 63, an output terminal of the delay cell DLC2 and a reference potential (here, ground potential). ) And a first MOS (NMOS) transistor NTR1 and a first capacitance means C1a connected in series, and a first MOS means (N1) connected in parallel to the first capacitance means C1a and connected in series with each other. MO of 2
And a load circuit section composed of an S (NMOS) transistor NTR2 and a second capacitance means C2. However, the first NMOS transistor NTR1 receives the second NMO depending on the voltage input to the first control terminal vc1.
The S transistor NTR2 is controlled by the voltage input to the second control terminal vc2. Here, the first capacitance means C1a in the DLC2
Is the capacitance means C1 in the delay cell DLC1 described with reference to FIG. 3B (that is, the capacitance means C1 on the VCO side).
The capacitance is designed to be slightly smaller than the capacitance of the second capacitance means C2, and the second capacitance means C2 is designed to be sufficiently smaller than the capacitance C1 of the capacitance means C1 in the DLC1. As the capacity relationship, C1
>C1a> C1-C2 is satisfied so that the signal delay time in the delay cell DLC2 becomes (α) and (β) described later.

Next, the operation of the PLL circuit according to the second embodiment will be described in order to deepen the understanding thereof.

Also in the PLL circuit of the second embodiment, the first loop 25 is first operated when the frequency difference between the clock CKIN and the output of the voltage controlled oscillator VCO is generated.
At 1), the retracting operation is performed and the first loop 25 is locked. At this time, the delay time of the signal in each delay cell DLC1 of the voltage controlled oscillator VCO is T / 2n.
However, T is the cycle of the clock CKIN.

On the other hand, the voltage of each first control terminal vc1 of each delay cell DLC2 which constitutes the delay circuit 27b is the frequency difference voltage conversion circuit F in the first loop 25.
It becomes equal to the voltage VCf at the output end of the DVC. Here, if the potential of the second control terminal vc2 of each delay cell DLC2 in the delay circuit 27b is 0 V, for example, NTR2
Is off, the load capacitance of each delay cell DLC2 is the first capacitance means C1a (<DL
The delay time in the delay cell DLC2 becomes T / 2n−δt <t / 2n (α) because it is only the capacity of the capacitance means C1) of C1 and is slightly shorter than that of the delay cell DLC1. However, δt∝C1-C1a. On the other hand, each delay cell D
When the potential of the second control terminal VC2 of LC2 is equal to V _CC , NTR2 is turned on, and the load capacitance of each delay cell DLC2 is C1a + C2. Therefore, the delay time in the delay cell DLC2 is T / 2n + δt> T / 2n (β), which is slightly longer than that of the delay cell DLC1. However, δt∝C1-C1a + C2.

Therefore, if C2 = C1−C1a is designed, the delay time in the delay circuit 27b can be reduced by the delay circuit 27b.
Voltage VCp input to the second control terminal VC2 of
It can be precisely controlled within the range of T−n · δt to T + n · δt (where δt∝C2). Further, since the voltage VCp is controlled by the phase difference voltage conversion circuit PDVC to form the second loop 27, the PLL circuit of the second embodiment also performs high-speed pull-in as in the first embodiment. Jitter is reduced. Further, also in the double loop structure of the second embodiment, the second loop 27
Since there is no feedback loop from the to the first loop 25, a complete master-slave operation PLL circuit can be obtained. Therefore, the same operation as that of the PLL circuit of the first embodiment can be obtained.

Further, in the second embodiment, the control voltage VCp by the second loop 27 is applied to each delay cell DLC2 of the delay circuit 27b, so that the transmission of the delay circuit 27b in the second loop 27 is performed. Function is Kp / S
(However, S = jω) and S is included. Therefore, the second loop 27 of this embodiment using the phase difference voltage conversion circuit PDVC including the low pass filter LPFp described with reference to FIG. 2D exhibits the secondary system loop characteristic. Therefore, in this second embodiment, a PLL circuit having both the first loop 25 and the second loop 27 having secondary loop characteristics can be constructed. In this way, in the PLL circuit in which both the first and second loops have the secondary loop characteristic, although the accuracy of the phase control in the second loop 27 is slightly lowered, Since the response speed can be improved, the pull-in time of the PLL circuit as a whole can be shortened.

3. Third Embodiment In the above-described first and second embodiments, a PL capable of operating stably and expanding a lockable frequency range as compared with the conventional PL can be achieved.
Although the L circuit can be provided, an example (third embodiment) in which the maximum operating frequency can be further improved will be described. This description will be described with reference to FIGS. 7 and 8. Here, FIG. 7 is a block diagram showing the entire configuration of the PLL circuit of the third embodiment,
FIG. 8 is an explanatory diagram of the delay circuit 27c included in the PLL circuit of the third embodiment.

The main difference between the PLL circuit of the third embodiment and the first and second PLL circuits is that the input terminal i1 and the pulse input terminal to which the clock CKIN in the frequency difference voltage conversion circuit FDVC is input. 21 is further provided with a 1 / k frequency dividing circuit 25y. Further, the configuration of the delay circuit is changed as a benefit of providing the 1 / k frequency dividing circuit 25y. These will be described below.

The 1 / k frequency dividing circuit 25y is composed of a conventionally known circuit. Further, the delay circuit 27c of the third embodiment can basically be configured by the voltage control delay circuit VCD and the voltage control phase shifter PS, like the delay circuit 27a of the first embodiment. However, in the voltage controlled delay circuit VCD, when the number of stages of the delay cell DLC1 in the voltage controlled oscillator VCO in the first loop 25 is n and the frequency division number in the frequency divider circuit 25y is k, as shown in FIG. , (2n-n /
2) A voltage-controlled delay circuit including a delay circuit 1 including delay cells DLC1 of k stages and delay circuits 2 and 3 each including delay cells DLC1 of n / 2 stages. . Each delay circuit 1 ~
The respective outputs of the delay cells at the final stage of No. 3 are outputs o1 to o3 of the voltage control delay circuit VCD.

To deepen the understanding of the PLL circuit of the third embodiment, its operation will be described.

First, regarding the operating frequency,
The operating frequency of the loop 25 is 1 / k frequency divider 25y
The frequency becomes 1 / k by the provision of. On the other hand, generally, the operating frequency of the frequency difference detection circuit FDD is the phase difference detection circuit P
Lower than that of DD. This is because, for example, considering the example of the frequency difference detection circuit FDD described with reference to FIG. 2A, the D-type flip-flops 31a and 3a are generated due to the timing difference between the signals input to the input i1 and the input i2.
After 1b is inverted, the output change is fed back and each flip-flop 31a, 31b is reset, and one operation period ends. That is, since the flip-flop needs to be inverted twice in one operation period, the upper limit of the operation frequency naturally becomes low. On the other hand, in the example of the phase difference detection circuit PDD described with reference to FIG.
The D-type flip-flop 32a does not invert unless there is a change in the phase relationship between the signals input to the input i2 and the input i2, and therefore the response speed thereof is determined only by the AND gate 32b or 32c1 stage. In the PLL circuit of the third embodiment, the operating frequency of the first loop 25 including the frequency difference detecting circuit FDD having a low maximum operating frequency can be set to 1 / k of the frequency of the input pulse (clock CKIN in this case), so that 1 As compared with the case where the / k frequency dividing circuit 25y is not provided, a PLL circuit that can handle even an input pulse having a frequency of k times can be obtained.

Next, the first and second loops 25 and 27
The operation will be described. In the first loop 25, the pull-in operation is performed as in the first and second embodiments. When this pull-in operation is completed, the delay time of the signal in each delay cell DLC1 of the voltage controlled oscillator VCO is kT / 2n (however,
T is the cycle of the clock CKIN. ). Also,
The same voltage as the voltage applied to the control terminal of the VCO, that is, the output VCf of the frequency difference voltage conversion circuit FDVC, is applied to the control terminal VC1 of the voltage control delay circuit VCD of the second loop 27. Circuit VCD
, 90 for each n / 2k stage delay cell DLC1.
° Phase-shifted clock is obtained. Therefore, in the second loop 27, as in the case of the first embodiment,
Since the phase is controlled in the range of −90 ° to + 90 ° regardless of the frequency, the clock CKOUT having no phase difference with respect to the clock CKIN can be obtained.

In the PLL circuit of the third embodiment, the delay circuit 27c may of course be composed of a delay circuit in which the delay cells DLC2 described in the second embodiment are connected in 2n / k stages. The delay time in the delay circuit having such a configuration is precisely controlled within the range of T ± nδt / k centering on the cycle T of the input clock CKIN by the second loop. A clock CKOUT having no phase difference can be obtained.

As can be understood from the above description, this third
In the PLL circuit of the embodiment, the PL circuits of the first and second embodiments are used.
In addition to the effect of the L circuit, the maximum operating frequency can be improved.

4. Fourth Embodiment Instead of the delay circuit provided in each of the first to third embodiments described above, an oscillation circuit section capable of phase control may be provided. This fourth embodiment is such an example. This description will be given with reference to FIGS. 9 and 10. Here, FIG. 9 shows P of the fourth embodiment.
FIG. 10 is a diagram showing the overall configuration of the LL circuit, and FIG. 10 is a diagram for explaining the voltage control phase shifter PS2 in the fourth embodiment.

The main difference between the PLL circuit of the fourth embodiment and that of the first to third embodiments is the delay circuits 27a to 27.
The point is that an oscillation circuit section 27α capable of phase control is provided instead of c. In this case, the oscillation circuit unit 27α has the same configuration as that of the voltage controlled oscillator VCO in the first loop 25.
Voltage-controlled oscillator VCO2, that is, a second voltage-controlled oscillator VCO2 configured by a circuit having the same configuration as described with reference to FIGS. 3A and 3B, and a voltage-controlled phase shifter PS2 (details will be described later). It consists of. here,
The control terminal vc of the second voltage controlled oscillator VCO2 is connected to the first control terminal VC1 of the oscillation circuit section 27α,
The control terminal c of the voltage control phase shifter PS2 is connected to the second control terminal VC2 of the oscillation circuit section 27α.

However, the second voltage controlled oscillator VCO2 in the PLL circuit of the third embodiment has a phase difference of 90 °.
It is configured to have output terminals from −180 ° to + 180 ° in steps. Since the output terminals for the phase 180 ° and the phase −180 ° are common, the second voltage controlled oscillator VCO2 is eventually assumed to have a total of four output terminals. On the other hand, the voltage control phase shifter PS2 has four output terminals from −180 ° to + 180 ° in 90 ° phase difference increments, and is supplied to the control terminal c (VC2) from the phase difference voltage conversion circuit PDVC. The phase is controlled by the voltage VCp. That is, it should be understood that the connection between the second voltage controlled oscillator VCO2 and the voltage controlled phase shifter PS2 in the PLL circuit of FIG. 9 is a bus description.

The voltage control phase shifter PS2 in the PLL circuit of the fourth embodiment needs to have a four-input configuration to correspond to the four outputs of the second voltage-controlled oscillator as described above. For example, the voltage control phase shifter described with reference to FIG. 5 may be expanded to add an input terminal. Specifically, the differential type buffer means OP
, A predetermined number of buffers B, and a predetermined number of transfer gates T can be used to configure the circuit as shown in FIG. The operating principle of this voltage control phase shifter PS2 is shown in FIG.
Since it is the same as the one already described by using, the description thereof will be omitted here.

Next, the operation of the PLL circuit of the fourth embodiment will be described in order to deepen the understanding thereof.

Also in this fourth embodiment, the pulling operation of the first loop 25 causes the oscillation frequencies of the voltage controlled oscillator VCO and the second voltage controlled oscillator VCO to quickly match the frequency of the input clock CKIN. , The input clock C by the second loop 27
The phase difference between KIN and the output clock CKOUT is eliminated. The master-slave operation is performed in which the first loop 25 is the master and the second loop 27 is the slave. Therefore, the same effect as in the first and second embodiments can be obtained.

In the case of the fourth embodiment, the range of the phase controlled by the voltage control phase shifter PS2 is large (-18
0 ° to 180 °), the accuracy of phase control is lower than in the first and second embodiments, but the advantages described below can be obtained.

The output clock CKOUT is generated by the oscillation circuit section 27α. That is, the output clock C
Since KOUT is generated without having a direct relationship with the input clock CKIN, the input clock CKI due to noise is generated.
This means that even if there are N pulse dropouts, the pulse dropout in the output clock CKOUT due to this does not occur.

As is apparent from the above description, according to the PLL circuit of the fourth embodiment, in addition to the effects similar to those of the first and second embodiments, the influence of the momentary disturbance of the input clock is exerted. The effect that a stable output clock that does not receive is obtained is also obtained.

The PLL circuit of the fourth embodiment can also be applied as a clock recovery circuit for separating data and clock from a phase-modulated signal. In that case, for example, the clock may be extracted from the voltage controlled oscillator VCO in the first loop 25 and the data may be extracted from CKOUT.

5. Fifth Embodiment Next, an example (fifth embodiment) in which a frequency dividing circuit is further provided in the PLL circuit of the above-described fourth embodiment will be described. This description will be given with reference to FIG. Here, FIG. 11 is a block diagram showing the entire configuration of the PLL circuit of the fifth embodiment.

The PLL circuit of the fifth embodiment is different from the PLL circuit of the fourth embodiment in that the input end i2 connected to the pulse output end 23 of the phase difference voltage conversion circuit PDVC in the second loop 27, A feature is that a 1 / k frequency dividing circuit 27y is further provided between the pulse output terminal 23 and the pulse output terminal 23. Further, the second voltage controlled oscillator VCO2 used in the fourth embodiment is used as an allowance for providing the 1 / k frequency dividing circuit 27y.
Instead, a voltage controlled oscillator VCO2a having n / k stages of delay cells DLC1 is provided. Further, the 1 / k frequency dividing circuit 2 is connected to one input terminal i2 of the phase difference voltage converting circuit PDVC.
In order to compensate for the timing deviation of the signals input to the input ends i1 and i2 by providing 5y, a predetermined delay is provided between the input end i1 on the side where the input clock CKIN is input and the pulse input end 21. A circuit DLY is provided.
The other structure is the same as that of the fourth embodiment.

The operation of the PLL circuit of the fifth embodiment will be described. As in the PLL circuit of the first embodiment, the pulling operation of the first loop 25 causes the oscillation frequency of the voltage controlled oscillator VCO in the first loop 25 to match the frequency of the input clock CKIN. At this time, in the second loop 27, the operating frequency of the voltage controlled oscillator VCO2a having n / k stages of delay cells DLC1 is k times the frequency of the input clock CKIN from the number of stages of delay cells. Therefore, an output clock having a frequency that is k times the frequency of the input clock CKIN can be obtained as the output clock CKOUT. Further, this output clock having a frequency that is k times the frequency of the input clock CKIN is fed back to the phase difference voltage conversion circuit PDVC, and the 1 / k frequency dividing circuit 2
The frequency is divided into 1 / k by 7y (that is, returned to the frequency of the input clock CKIN) and input to the input end i2 of the PDVC.
And the phases are compared. The phase error due to the delay time of the 1 / k frequency dividing circuit 27y is canceled by the delay circuit DLY. In this way, the second loop 27 eliminates the phase difference between the input clock and the output clock, and the pulse output terminal 23 outputs the frequency k of the input clock.
An output clock CKOUT having a doubled frequency and an edge having no phase difference with respect to the edge of the input clock is obtained.

As described above, in the PLL circuit of the fifth embodiment, in addition to the effect obtained in the fourth embodiment, the maximum operating speed can be increased. Also, since output pulses of various frequencies can be obtained depending on the value of k, this fifth
The PLL circuit of the embodiment can also be used as a frequency synthesizer.

6. Sixth Embodiment In the fourth embodiment, the oscillation circuit section is composed of the second voltage-controlled oscillator and the voltage-controlled phase shifter, but the oscillation circuit section may have another structure. The sixth embodiment is an example of this. This description will be made with reference to FIGS. 12 and 13. Here, FIG. 12 shows the PL of the sixth embodiment.
FIG. 13 is a block diagram showing the overall configuration of the L circuit, and FIG. 13 is a diagram for explaining the oscillator circuit unit VCO3 used in the sixth embodiment.

The PLL circuit of the sixth embodiment differs from the PLL circuit of the fourth embodiment in that the oscillation circuit section 27α
Instead of, the delay cell DLC2 having the first and second control terminals vc1 and vc2 as shown in FIG. 13 is provided in a plurality of stages (n stages), and the output o of the delay cell DLC2 at the nth stage is provided. With a connected inverter INV37,
It is characterized in that it comprises an oscillating circuit section (that is, a third voltage controlled oscillator) VCO3 composed of a ring oscillator in which the output of the inverter INV37 is connected to the delay cell of the first stage. However, the first control terminal vc1 of each delay cell DLC2 is connected to the frequency difference voltage conversion circuit FDV via the first control terminal VC1 of the oscillation circuit section VCO3.
It is connected to the output terminal o of C. Also, each delay cell DL
Each second control terminal vc2 of C2 is connected to the output terminal o of the phase number difference voltage conversion circuit PDVC via the second control terminal VC2 of the oscillation circuit section VCO3.

Next, the operation of the PLL circuit of the sixth embodiment will be described. As in the previous embodiments, the output frequency of the voltage controlled oscillator VCO in the first loop becomes equal to the frequency of the input clock CKIN when the pull-in operation in the first loop 25 ends. At this time, a constant voltage VCf is applied to the first control terminal VC1 of the oscillation circuit section VCO3 from the output terminal o of the frequency difference voltage conversion circuit FDVC.
Since it has a structure having n stages of LC2 and a delay cell structure similar to that of the delay circuit 27b in the second embodiment, each delay cell DLC2 of this oscillation circuit section VCO3 is similar to that described in the second embodiment. The delay time of the signal at the second control voltage V
It is controlled in the range of T / 2n−δt to T / 2n + δt according to the voltage of VCp given to C2. However, T is the cycle of the input clock CKIN. Therefore, the output of the oscillation circuit unit VCO3, that is, the frequency of the output clock CKOUT is controlled between 1 / (T + nδt / 2) and 1 / (T-nδt / 2) centering on the frequency (1 / T) of the input clock CKIN. Will be. On the other hand, this oscillator circuit VC
The voltage at the second control terminal VC2 of O3 is
The phase difference voltage conversion circuit PDVC in 7 controls the voltage so that there is no phase difference between the input clock CKIN and the output clock CKOUT. As described above, in the PLL circuit of the sixth embodiment, the output clock CK is set to the frequency of the input clock CKIN by the first loop 25.
The frequency of OUT is roughly adjusted, and the second loop 27 eliminates the frequency difference with higher accuracy. In particular,
When the frequency difference of the clock CKOUT with respect to the clock CKIN is T >> nδt / 2 in terms of period, it is considered that the second loop 27 mainly works to eliminate the phase difference between the clock CKIN and the clock CKOUT. good.

Further, in the PLL circuit of the sixth embodiment, since the second loop 27 has the secondary loop characteristic as in the case of the second embodiment, the pull-in time of the entire PLL circuit is increased. The effect of reduction can also be obtained in addition to the effect obtained by the fourth embodiment.

7. Seventh Embodiment In each of the first to sixth embodiments described above, the low-pass filter LPFf included in the frequency difference voltage conversion circuit FDVC is shown in FIG.
The example of the low-pass filter described using (D), that is, the example of the low-pass filter exhibiting a single transfer characteristic has been described. However, as the low-pass filter LPFf, the first output terminal connected to the control terminal of the voltage controlled oscillator VCO in the first loop 25 and the first output terminal connected to the control terminal of the delay circuit or the oscillation circuit section in the second loop are connected. It is also possible to use a low-pass filter having two output terminals, which shows different transfer characteristics for each of the first and second output terminals with respect to a common input. This is because, as will be described later in detail, such an advantage is obtained that the design of each of the first loop and the second loop can be optimized. This seventh embodiment is such an example. This explanation is shown in FIGS. 14 and 15 (A) and (B).
Refer to. Here, FIG. 14 shows the PL of the seventh embodiment.
15A and 15B are block diagrams showing the overall configuration of the L circuit, and FIGS. 15A and 15B are diagrams showing a configuration example of a low-pass filter used in the seventh embodiment. However, FIG. 14 is an example in which the idea of the seventh embodiment is applied to the configuration of the first embodiment.

As shown in FIG. 14, the low-pass filter LPFd, which exhibits different transfer characteristics with respect to a common input at the first and second output terminals o1 and o2, has its input i connected to the output end of the charge pump 25x. , Its first output o1 is connected to the control terminal VC of the voltage controlled oscillator VCO,
The PLL circuit 2 is so arranged that its second output terminal o2 is connected to the first control terminal VC1 of the delay circuit 27a.
Place within 0.

Any suitable LPFd can be used. For example, as shown in FIG.
The input ends of the first low-pass filter LPF1 and the second low-pass filter LPF2 having different transfer characteristics are connected to each other and used as the input terminal of LPFd, and one output end of the first and second low-pass filters LPF1 and LPF2 is connected. Set the first output terminal o1 of LPFd to the other output end
An example is a configuration in which the second output terminal o2 of Fd is used. In this case, each of the first and second low-pass filters LPF1 and LPF2 can be constituted by, for example, a lag filter including a resistance means R and a capacitance means C as shown in FIG.

In the configuration of the seventh embodiment, the conversion gain characteristic of the frequency difference voltage conversion circuit FDVC is set to the first loop 2
5 and the second loop 27 can be designed separately, so that it is easy to optimize the characteristics of each of the first loop 25 and the second loop 27.

For example, by designing these lowpass filters so that the cutoff frequency of the lowpass filter LPF2 is lower than the cutoff frequency of the lowpass filter LPF1, the following characteristics are obtained. That is, the first loop 2 caused by the jitter of the input clock CKIN
Variation of control voltage VCf1 of 5 (see FIG. 14) ΔVCf1
And the variation ΔVCf2 of VCf2 that is the control voltage for the second loop 27, ΔVCf1 >> ΔVCf2
Holds. Therefore, while increasing the response speed of the first loop 25 with respect to changes in the phase difference and the frequency difference between the input clock CKIN and the output clock CKOUT, the fluctuation width of the control voltage VCf2 with respect to the second loop 27 is suppressed to reduce jitter. Can be planned.

When a lag lead filter is used as the low pass filter LPF1 and a lag filter is used as the low pass filter LPF2, the following characteristics are obtained. That is, in the first loop 25, the free-running frequency of the loop and the damping constant can be independently optimized, so that the first loop capable of high-speed pull-in can be realized. Also in this case, ΔVCf1 >> ΔVCf2
Therefore, the jitter can be reduced in the second loop 27.

As described above, in the PLL circuit of the seventh embodiment, in addition to the effects obtained by the first to sixth embodiments, the PLL circuit which can perform the pulling operation at a higher speed and further reduce the jitter can be obtained. The circuit is obtained.

8. Eighth Embodiment Next, an example (eighth embodiment) suitable for high integration when a PLL circuit is built in a semiconductor substrate will be described. In particular, this is a preferable example when using the low-pass filter LPFd that exhibits different transfer characteristics for each of the first and second output terminals with respect to a common input. This description will be given with reference to FIG.

In the eighth embodiment, as shown in FIG. 16, a low-pass filter LPFd showing different transfer characteristics for the first and second output terminals with respect to a common input, as shown in FIG.
The resistance means R1 connected to the input terminal i of the LPFd, the terminal of the resistance means R1 on the side opposite to the input terminal i, and the reference potential (here, ground potential; power supply potential may be used). Low-pass filter LPFd composed of second resistance means R2 and capacitance means CL connected in between
The connection point between the first resistance means R1 and the second resistance means R2 is used as the first output terminal o1 of the LPFd, and the connection point between the second resistance means R2 and the capacitance means CL is A low pass filter LPFd is used as the second output terminal o2 of the LPFd.

In the low-pass filter LPFd described with reference to FIG. 16, the portion between the input terminal i and the first output terminal o1 functions as a lag lead filter,
The portion between the input terminal i and the second output terminal o2 functions as a lag filter. Therefore, as in the case of the seventh embodiment, it is possible to obtain a PLL circuit in which high-speed pull-in control can be performed by the first loop and jitter can be reduced by the second loop. Further, in general, such a circuit requires a resistor having a resistance value of several tens of KΩ and a capacitance having a capacitance value of several pF, and a relatively large area is required to form such a resistance and a capacitance on a semiconductor substrate. Therefore, if such resistance and capacitance are required for each of the two low-pass filters, the formation area of these elements on the semiconductor substrate increases. However, in the eighth embodiment, since the resistance means and the capacitance means which are the constituent elements of the lag lead filter and the lag filter are commonly used, the formation area of these elements occupying the semiconductor substrate can be reduced accordingly. Therefore, it is possible to realize a PLL circuit having excellent characteristics and suitable for high integration. Of course, the idea of the eighth embodiment can be applied to the PLL circuits of the first to seventh embodiments.

The first resistance means R1 provided between the input terminal i and the first output terminal o1 of the low-pass filter LPFd described with reference to FIG. 16 is removed, and the charge pump 25x (see FIG. 1) is removed. The current source (see FIG. 2C) may be used instead of the first resistance means R1.

9. Modification 9-1. In each of the above-mentioned embodiments, an example of a circuit that handles a single clock as an input pulse has been described, but the present invention can of course be applied to the case of handling complementary input pulses. As an example thereof, an example will be described in which the PLL circuit of the first embodiment is provided with an allowance for handling a complementary input pulse. FIG. 17 is a diagram provided for the explanation.

In the example shown in FIG. 17, the input clock CKIN is applied to the pulse input terminal 21 of the PLL circuit of the first embodiment.
And an input clock CKINB complementary thereto, respectively, and output from the pulse output terminal 23 to the output clock CKOUT.
And an example of a circuit that outputs an output clock CKOUTB complementary thereto. Pulse input end 2 in this case
1 can be composed of an input terminal group which can input CKIN and CKINB. The pulse output terminal 23 can be composed of an output terminal group to which CKOUT and CKOUTB can be input. Note that B in CKINB and CKOUTB means a bar signal (the same applies to each of the following signals).

In the circuit of FIG. 17 for handling complementary signals, necessary signal lines are paired. Particularly, regarding the signal line between the voltage control delay circuit VCD and the voltage control phase shifter PS in the delay circuit 27a, when considered in correspondence with the first embodiment, o1 (phase difference −90 °), o1B (same −90).
O), o2 (same 0 °), o2B (same 0 °), o3 (same 9)
A total of 6 signal lines for 0 °) and o3B (90 ° for the same) are provided. The signal line from the frequency difference detection circuit FDD to the charge pump 25x and the signal line from the phase difference detection circuit PDD to the charge pump 27x do not necessarily have to be paired lines.

Further, when handling complementary signals in this way,
The flip-flops and gate circuits included in the frequency difference detection circuit FDD and the phase difference detection circuit PDD may be configured by an ECL type circuit having complementary input / output terminals, or, for example, FIG.
For example, the delay cell DLC1 described with reference to (B) is replaced with an operational amplifier.

The idea of handling complementary signals is, of course, second to second.
It can be applied to the PLL circuit of each of the eighth embodiments. Even in that case, the treatment described with reference to FIG. 17 and a well-known circuit technique may be applied to deal with the problem.

9-2. In each of the above-described embodiments, the frequency difference voltage conversion circuit FDVC is composed of the frequency difference detection circuit FDD, the charge pump, and the LPFf. However, the frequency difference voltage conversion circuit FDVC includes an FV converter using an integration circuit, an up / down counter and a D / A.
Of course, it may be configured by other circuits of various disclosures such as a circuit using a converter.

9-3. Further, the phase difference voltage conversion circuit PDVC in each embodiment may be a circuit using an analog multiplication circuit. In that case, the phase of the signal applied to one of the two inputs i1 and i2 of the phase difference voltage conversion circuit may be shifted by 90 ° with respect to the other and input to the circuit. Further, as the phase difference detection circuit PDD in the phase difference voltage conversion circuit, various disclosed circuits including a phase-frequency difference detection circuit can be used.

9-4. For each of the second, fourth, fifth and sixth embodiments, a frequency dividing circuit is provided between the input end and the pulse input end of the frequency difference conversion circuit FDVC, as described in the third embodiment. At the same time, the maximum operating frequency can be improved by appropriately changing the number of stages of delay cells in the delay circuit and the oscillation circuit section.

9-5. In the fifth embodiment, the oscillation circuit unit 27α used therein may be replaced by the oscillation circuit unit VCO3 described in the sixth embodiment. By doing so, it is possible to obtain a frequency synthesizer that exhibits a secondary loop characteristic in both the first loop 25 and the second loop 27.

9-6. In the overall configuration diagrams of all the examples, specifically, in FIGS. 1, 6A, 7, 9, 11, 12, 14, and 17, it is necessary to include each component. Accordingly, other circuit components such as a delay circuit for compensating for the offset of the phase error and buffer means for improving the output drive capability may be inserted.

[0093]

As is apparent from the above description, according to the PLL circuit of the present invention, a pulse input terminal to which a single or complementary input pulse is input, and a single or complementary output related to the input pulse. A pulse output terminal for outputting a pulse, a first loop including a predetermined frequency difference voltage conversion circuit and a voltage control oscillator, and a predetermined phase difference voltage conversion circuit, a predetermined voltage control delay circuit, and a voltage control phase shifter. A second loop including a delay circuit is provided, so that the frequency is adjusted in the first loop, and the resulting voltage is applied to the second loop to adjust the phase. That is, a PLL circuit that operates as a master-slave is realized. Therefore, the second
Since a PLL circuit having no feedback path from the loop of 1 to the first loop can be obtained, the problem that occurred in the conventional circuit in which the above feedback path existed does not occur in the present invention.
An LL circuit is obtained. Further, since the first loop performs frequency matching and the second loop eliminates the phase difference, it is possible to obtain a PLL circuit in which the frequency range in which the frequency can be locked is wider than in the conventional case. These effects are similarly obtained when the delay circuit in the second loop is changed to a delay circuit having a predetermined delay cell or an oscillation circuit section.

Further, in the structure in which the frequency dividing circuit is provided, the allowance for the frequency difference voltage converting circuit, which is said to be impossible to raise the operating frequency so much, or k on the second loop side.
Because it is possible to obtain the output of double frequency, PLL
The effect of increasing the maximum operating frequency of the entire circuit is further obtained.

Further, in the configuration in which the predetermined low-pass filter is provided, the components of these two types of low-pass filters are used when two types of low-pass filters having different transfer characteristics are used so that the characteristics of the PLL circuit can be easily optimized. Since they can be shared, the formation area of these low-pass filters on the semiconductor substrate can be reduced. Therefore, the effect of reducing the degree of hindrance to high integration can be further obtained.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a PLL circuit according to a first embodiment.

FIGS. 2A to 2D are explanatory views of some constituent components of the PLL circuit of the first embodiment.

FIG. 3 is an explanatory diagram of the first embodiment, particularly an explanatory diagram of a voltage controlled oscillator VCO.

FIG. 4 is an explanatory diagram of a voltage control delay circuit VCD.

FIG. 5 is an explanatory diagram of a voltage control phase shifter PS.

6A to 6C are explanatory diagrams of a PLL circuit according to a second embodiment.

FIG. 7 is an overall configuration diagram of a PLL circuit according to a third embodiment.

FIG. 8 is an explanatory diagram of a voltage control delay circuit VDC of the delay circuit 27c in the third embodiment.

FIG. 9 is an explanatory diagram of a PLL circuit according to a fourth embodiment.

FIG. 10 is a voltage control phase shifter PS in the fourth embodiment.
It is explanatory drawing of 2.

FIG. 11 is an explanatory diagram of a PLL circuit according to a fifth embodiment.

FIG. 12 is an explanatory diagram of a PLL circuit according to a sixth embodiment.

FIG. 13 is an explanatory diagram of an oscillation circuit section VCO3.

FIG. 14 is an explanatory diagram of a PLL circuit according to a seventh embodiment.

FIG. 15 is an explanatory diagram of a low pass filter LPFd having different transfer characteristics for each output terminal.

FIG. 16 is an explanatory diagram of a more preferable LPFd.

FIG. 17 is an explanatory diagram of a modified example, which is an explanatory diagram of a circuit example that handles complementary signals.

FIG. 18 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 20: PLL circuit of the first embodiment 21: Pulse input end 23: Pulse output end 25: First loop 27: Second loop FDVC: Frequency difference voltage conversion circuit PDVC: Phase difference voltage conversion circuit VCO: Voltage controlled oscillator VCD: Voltage control delay circuit PS: Voltage control phase shifter 27a: Delay circuit DLC1, DLC2: Delay cell

Claims (10)

[Claims] 1. (a). A pulse input terminal to which a single or complementary input pulse is input, (b). A pulse output end that outputs a single or complementary output pulse related to the input pulse, (c). One input end is connected to the pulse input end,
The other input terminal is connected to the output terminal of the voltage controlled oscillator, and a frequency difference voltage conversion circuit for converting at least a frequency difference between signals input to the one and the other input terminals into a voltage, and a control terminal for the frequency difference. A first loop including the voltage controlled oscillator connected to an output terminal of the voltage conversion circuit, and (d). One input end is connected to the pulse input end,
The other input end is connected to the pulse output end, and a phase difference voltage conversion circuit that detects at least the phase difference between the signals input to the one and the other input ends and converts it into a voltage, and the input end is the pulse The control terminal is connected to the input terminal, the control terminal is connected to the output terminal of the frequency difference voltage conversion circuit included in the first loop, and the delay time of the input signal is controlled by the output voltage of the frequency difference voltage conversion circuit. A voltage control delay circuit and an input end connected to an output end of the voltage control delay circuit, a control terminal connected to an output end of the phase difference voltage conversion circuit, and an output end connected to the pulse output end,
A PLL circuit comprising a second loop including a delay circuit configured by a voltage control phase shifter for controlling a phase of an input signal by an output voltage of the phase difference voltage conversion circuit. 2. The PLL circuit according to claim 1, wherein a plurality of delay cells having first and second control terminals are provided instead of the delay circuit composed of a voltage control delay circuit and a voltage control phase shifter. A delay circuit configured by connecting in stages, the input end of which is connected to the pulse input end, the output end of which is connected to the pulse output end, and each of the first control terminals of the respective delay cells is A delay circuit connected to the output end of the frequency difference voltage conversion circuit included in the first loop, and each second control terminal connected to the output end of the phase difference voltage conversion circuit included in the second loop. PLL characterized by including
circuit. 3. The PLL circuit according to claim 1, further comprising a frequency dividing circuit between the one input end and the pulse input end of the frequency difference voltage conversion circuit. . 4. The PLL circuit according to claim 1, wherein a control terminal of the frequency difference voltage conversion circuit in the first loop is used instead of the delay circuit configured by a voltage control delay circuit and a voltage control phase shifter. A second voltage controlled oscillator connected to the output terminal, an input terminal connected to the output terminal of the second voltage controlled oscillator, and a control terminal connected to the output terminal of the phase difference voltage conversion circuit in the second loop. A voltage control phase shifter having an output terminal connected to the pulse output terminal and controlling the phase of an input signal by the output voltage of the phase difference voltage conversion circuit. A characteristic PLL circuit. 5. The PLL circuit according to claim 4, further comprising a frequency dividing circuit between an input terminal to which the pulse output terminal of the phase difference voltage conversion circuit is connected and the pulse output terminal. A PLL circuit characterized by the above. 6. The PLL circuit according to claim 4, further comprising first and second control terminals instead of the oscillation circuit section including the second voltage controlled oscillator and the voltage controlled phase shifter. The delay circuit is configured by connecting a plurality of delay cells,
Control terminals are connected to output terminals of the frequency difference voltage conversion circuit included in the first loop, and second control terminals are connected to output terminals of phase difference voltage conversion circuit included in the second loop. A PLL circuit characterized by comprising an oscillating circuit section. 7. The PLL circuit according to claim 1, 2, 3, 4, or 6, wherein the frequency difference voltage conversion circuit is connected to a control terminal of a voltage controlled oscillator in a first loop. A low-pass filter having an output terminal and a second output terminal connected to a control terminal of a delay circuit or an oscillation circuit section in a second loop, which has different transfer characteristics for each of the first and second output terminals. A PLL circuit comprising a frequency-voltage conversion circuit including the low-pass filter shown. 8. The PLL circuit according to claim 2, wherein the delay cell includes a drive circuit section and a load circuit section,
And, the load circuit section is connected in parallel to the first capacitance means and a first MOS transistor and a first capacitance means connected in series between the output terminal of the delay cell and a reference potential. And a second MOS transistor and a second capacitance means connected in series with each other. 9. The PLL circuit according to claim 7, wherein the low-pass filter includes a first filter formed between the input terminal and the first output terminal, the input terminal and the second filter. And a second filter formed between the output terminal and the output terminal of the PLL circuit. 10. The PLL circuit according to claim 7, wherein the low-pass filter has first resistance means connected to its input terminal, and a terminal connected to the input terminal of the first resistance means. And a second resistance means and a capacitance means connected in series between a terminal on the side opposite to and a reference potential, and a connection point of the first resistance means and the second resistance means is the first resistance means and the second resistance means. A PLL circuit having an output terminal and a connection point of the second resistance means and the capacitance means being the second output terminal.