CN111863706A - Flash memory and manufacturing method thereof - Google Patents
Flash memory and manufacturing method thereof Download PDFInfo
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- CN111863706A CN111863706A CN202010884241.2A CN202010884241A CN111863706A CN 111863706 A CN111863706 A CN 111863706A CN 202010884241 A CN202010884241 A CN 202010884241A CN 111863706 A CN111863706 A CN 111863706A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Abstract
The present invention provides a flash memory and a method for manufacturing the same, which performs a plasma film deposition process to form an isolation material layer on a trench and a mask layer at a slower rate of plasma deposition in a peripheral region of a substrate than in a central region of the substrate. Thereby making the rate of plasma deposition in the edge region of the substrate relatively slow to increase the densification of the layer of isolation material formed in the trenches in the edge region of the substrate. Therefore, the problem of poor filling performance of the edge area of the substrate to the groove is solved, and the performance of the flash memory is improved.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a flash memory and a method for manufacturing the same.
Background
Flash memory is an important device in integrated circuit products. The main characteristic of flash memory is that it can keep the stored information for a long time without applying voltage, and it has the advantages of high integration level, faster access speed and easy erasing, so it is widely used.
In the manufacturing process of the flash memory, a shallow trench isolation process is usually performed to isolate a plurality of active areas of the flash memory on a substrate, that is, a trench is opened in the substrate and a material layer above the substrate, and an isolation material is filled in the trench to form an isolation structure for isolating the plurality of active areas of the flash memory. However, in the current wafer processing process, uniformity of each position of the substrate is not good, especially, filling performance of the edge area of the substrate to the groove is poor, the sealing is easy to be performed prematurely when the filling is insufficient, and the sealing is exposed to form a cavity after the CPM (polishing), and the defect of the cavity can cause the failure of a storage unit, thereby seriously affecting the performance of the flash memory.
Disclosure of Invention
The invention aims to provide a flash memory and a manufacturing method thereof, which aim to solve the problem that a shallow trench isolation structure in the edge area of a substrate of the existing flash memory is easy to form a cavity to cause the failure of a storage unit.
In order to solve the above problems, the present invention provides a method for manufacturing a flash memory, the method comprising:
providing a substrate;
forming a mask layer on the substrate, wherein a plurality of first openings are formed in the mask layer;
etching the substrate by taking the mask layer as a mask to form a plurality of second openings in the substrate, wherein the second openings and the first openings are communicated to form grooves;
and performing a plasma film deposition process to form an isolation material layer on the trench and the mask layer, wherein the plasma film deposition process is performed at a slower rate in the peripheral region of the substrate than in the central region of the substrate.
And grinding and removing the isolation material layer on the mask layer to form an isolation structure in the trench.
Optionally, the plasma deposition rates increase sequentially in a direction from the edge of the substrate toward the center of the substrate.
Optionally, before forming the isolation material layer, the method further includes:
and etching the mask layer on the side of the first opening to increase the width of the first opening, wherein the increased width of the first opening is greater than the width of the second opening.
Optionally, the method for etching the mask layer located on the side of the first opening is wet etching.
Optionally, the etching solution for wet etching is a hydrofluoric acid solution, and the mass ratio of hydrofluoric acid to water in the hydrofluoric acid solution is: 190: 1-230: 1, and the etching time of the wet etching is 3 min-5 min.
Optionally, while a plurality of first openings are formed in the mask layer, the method further includes: the width of the first opening is gradually reduced in a direction from the edge of the substrate toward the center of the substrate.
Optionally, before forming the mask layer on the substrate, the method further includes: forming a dielectric material layer on the substrate;
and, while etching the substrate with the mask layer as a mask, the method further comprises: and etching the dielectric material layer by taking the mask layer as a mask to form a dielectric layer, and extending the first opening to the dielectric layer to form a plurality of third openings in the dielectric layer.
Optionally, after forming the dielectric layer, the method further includes:
and etching the dielectric layer on the side of the third opening to enlarge the third opening, and enabling the enlarged width of the third opening to be equal to the enlarged width of the first opening.
Optionally, while forming the third opening in the dielectric layer, the method further includes: gradually decreasing a width of the third opening in a direction from the edge of the substrate toward the center of the substrate.
Optionally, the method for etching the dielectric layer on the side of the third opening is wet etching.
Optionally, the etching solution for wet etching is a phosphoric acid solution, and the concentration of phosphoric acid in the phosphoric acid solution is as follows: 75-90% and the etching time of the wet etching is 45-80 s.
Optionally, while forming the second opening in the substrate, the method further includes: the depth of the second opening is gradually increased in a direction from the edge of the substrate toward the center of the substrate.
Optionally, the width of the first opening is 81nm to 99nm, and the width of the second opening is 76nm to 94 nm.
Optionally, the depth of the groove is
In order to solve the above problems, the present invention further provides a flash memory, which is manufactured according to the method for manufacturing a flash memory as described in any one of the above embodiments.
The invention relates to a flash memory and a manufacturing method thereof, which can lower the plasma deposition rate of the edge area of a substrate than the plasma deposition rate of the central area of the substrate when a plasma film deposition process is carried out to form an isolation material layer on a groove and a mask layer. Thereby making the rate of plasma deposition in the edge region of the substrate relatively slow to increase the densification of the layer of isolation material formed in the trenches in the edge region of the substrate. Therefore, the problem of poor filling performance of the edge area of the substrate to the groove is solved, the isolation structure in the edge area of the substrate is prevented from forming a cavity, and the performance of the flash memory is improved.
Drawings
FIG. 1 is a flow chart illustrating a method for manufacturing a flash memory according to an embodiment of the present invention;
FIGS. 2-6 are schematic structural diagrams illustrating a method for manufacturing a flash memory according to an embodiment of the invention;
wherein the reference numbers are as follows:
1-a substrate;
2-a dielectric layer; 20-a layer of dielectric material;
3-a mask layer;
100-a trench;
101-a first opening; 102-a second opening;
103-first grooving;
d1 — width of first opening after increase; d2 — width of second opening;
d3 — increased width of the third opening;
Detailed Description
The following describes a flash memory and a method for manufacturing the same in detail with reference to the accompanying drawings and embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently. A core idea of the present invention is to provide a method of manufacturing a flash memory device, wherein a plasma film deposition process is performed to form an isolation material layer on the trench and the mask layer such that a plasma deposition rate is slower in a peripheral region of the substrate than in a central region of the substrate. Because the groove in the edge area of the substrate is filled by slower ion deposition, the compactness of the isolation structure formed in the groove in the edge area of the substrate can be increased, the isolation structure in the edge area of the substrate is prevented from forming a cavity, and the uniformity of groove filling on the substrate is improved, so that the performance of the flash memory is improved.
FIG. 1 is a flow chart illustrating a method for manufacturing a flash memory according to an embodiment of the present invention; FIGS. 2-6 are schematic structural diagrams illustrating a method for manufacturing a flash memory according to an embodiment of the invention; the following describes a method for manufacturing a flash memory in this embodiment with reference to fig. 1 to 6, and the following method for manufacturing a flash memory does not depart from the core idea.
In step S10: as shown in fig. 2, a substrate 1 is provided.
The substrate 1 may include a semiconductor material, an insulating material, a conductor material, or any combination thereof, and may have a single-layer structure or a multi-layer structure. Thus, the substrate may be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III/V or II/VI compound semiconductors. Layered substrates such as, for example, Si/SiGe, Si/SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator may also be included.
In step S20, with continued reference to fig. 2, a mask layer 3 is formed on the substrate 1, wherein a plurality of first openings 101 are opened in the mask layer 3.
In this embodiment, as shown in fig. 2, a method for forming a mask layer 3 on the substrate 1 and forming a plurality of first openings 101 in the mask layer 3 may be: firstly, forming a mask material layer on the substrate 1, wherein the mask material layer can be made of silicon nitride; then, a photoresist layer is formed on the mask material layer, the mask material layer is etched by using the photoresist layer as a mask to form a mask layer, and a plurality of first openings 101 are formed in the mask layer. And, in the present embodiment, while a plurality of first openings 101 are opened in the mask layer 3, the method further includes: the width of the first opening 101 is gradually reduced in a direction toward the center of the substrate 1 at the edge of the substrate 1. Wherein, the method for gradually reducing the width of the first opening 101 may include: forming a photoresist layer with a plurality of first grooves with gradually reduced width from the edge of the substrate 1 to the center of the substrate 1 on the mask material layer, etching the mask material layer by using the photoresist layer as a mask to form a mask layer 3, and forming a plurality of first openings 101 with gradually reduced width in the mask layer 3 in the direction from the edge of the substrate 1 to the center of the substrate 1. The method for forming the photoresist layer may include: and forming a photoresist layer on the mask material layer, and exposing to form the photoresist layer by taking a mask plate as a mask, wherein the mask plate is provided with a plurality of light transmission holes of which the width is gradually reduced from the edge area of the mask plate to the central area.
In step S30, referring to fig. 3, the substrate 1 is etched using the mask layer 3 as a mask to form a second opening 102 in the substrate 1, and the second opening 102 and the first opening 101 penetrate to form a trench 100. In the present embodiment, the width of the first opening is 81nm to 99nm, and the width of the second opening is 76nm to 94 nm. The depth of the groove is
In this embodiment, the method for etching the substrate 1 is wet etching. And, with continued reference to fig. 3, while forming the second opening 102 in the substrate 1, the method further comprises: the depth of the second opening 102 is gradually increased in a direction from the edge of the substrate 1 toward the center of the substrate 1. Therefore, the depth-to-width ratio of the trench 100 can be gradually increased in the direction from the edge of the substrate 1 to the center of the substrate 1, so that the closer to the edge area of the substrate 1, the better the filling performance when the trench 100 is filled, and the lower the possibility that the isolation structure formed in the trench 100 in the edge area of the substrate 1 forms a cavity, thereby improving the uniformity of trench filling on the substrate and improving the performance of the flash memory.
Further, with continued reference to fig. 2, before forming the mask layer 3 on the substrate 1, the method further comprises: a layer of dielectric material 20 is formed on the substrate 1. In this embodiment, the material of the dielectric material layer 20 may be silicon oxide.
And, with continued reference to fig. 3, while etching the substrate 1 with the mask layer 3 as a mask, the method further comprises: and etching the dielectric material layer 20 by using the mask layer 3 as a mask to form a dielectric layer 2, and extending the first opening 101 to the dielectric layer 2 to form a third opening 103 in the dielectric layer 2. In this embodiment, the first opening 101, the second opening 102 and the third opening 103 penetrate to form a slot 100.
With continued reference to fig. 4, in this embodiment, after etching the substrate 1 and before forming the isolation material layer, the method further includes: the mask layer 3 on the side of the first opening 101 is etched to increase the width of the first opening 103, wherein the increased width D1 of the first opening 101 is greater than the width D2 of the second opening 102. In the embodiment, since the increased width D1 of the first opening 103 is greater than the width D2 of the second opening 102, when a plasma film deposition process is subsequently performed to form an isolation material layer in the trench 100, more plasma can be deposited in the trench 100 through the wider first opening 103, so as to increase the compactness of the isolation material layer of the substrate in the trench 100, and further reduce the possibility of voids in the isolation structure formed in the trench 100 in the edge region of the substrate 1 after polishing, so as to improve the uniformity of filling the trench 100 on the substrate 1, and further improve the performance of the flash memory.
In this embodiment, the method for etching the mask layer 3 located at the side of the first opening 101 is wet etching. The etching solution for wet etching is a hydrofluoric acid solution, and the mass ratio of hydrofluoric acid to water in the hydrofluoric acid solution is as follows: 190: 1-230: 1, and the etching time of the wet etching is 3 min-5 min.
And, referring to fig. 5, in this embodiment, after forming the dielectric layer 2, the method further includes: etching the dielectric layer 2 on the side of the third opening 103 to enlarge the third opening 103, and making the width D3 of the enlarged third opening 103 equal to the width D1 of the enlarged first opening 101. Specifically, in this embodiment, after the mask layer 3 located at the side of the first opening 101 is etched by using the above-mentioned hydrofluoric acid solution to enlarge the first opening 101, the etching is stopped on the dielectric layer 2. And then, etching the dielectric layer 2 positioned on the side of the third opening 103 by using the etched mask layer 3 as a mask and adopting a wet etching method. The etching solution of the wet etching is phosphoric acid solution, and the concentration of phosphoric acid in the phosphoric acid solution is as follows: 75-90% and the etching time of the wet etching is 45-80 s.
In this embodiment, while etching the dielectric layer 2 located on the side of the third opening 103, the method further includes: the width of the third opening 103 is gradually reduced in a direction toward the center of the substrate 1 at the edge of the substrate 1. In the present embodiment, the widths of the plurality of first openings 101 in the mask layer 3 are gradually reduced in a direction from the edge of the substrate 1 toward the center of the substrate 1. In this way, when the third opening 103 is etched using the etched mask layer 3 as a mask, the plurality of third openings 103 in the dielectric layer 2 are formed such that the widths thereof gradually decrease as the edge of the substrate 1 faces the center of the substrate 1.
In step S40, as shown in fig. 6, a plasma film deposition process is performed to form an isolation material layer on the trench 100 and the mask layer 3, wherein the plasma film deposition process is performed at a rate of plasma deposition in the edge region of the substrate 1 slower than that in the center region of the substrate. In the present embodiment, the edge region of the substrate 1 is defined as a region where the edge of the substrate 1 occupies the total area 1/100 to 1/10 of the substrate 1, and the center region of the substrate 1 is defined as a region where the center of the substrate 1 occupies the total area 1/100 to 1/10 of the substrate 1.
In the method for manufacturing a flash memory according to this embodiment, when a plasma film deposition process is performed to form an isolation material layer on the trench 100 and the mask layer 3, the plasma deposition rate in the edge region of the substrate 1 is slower than the plasma deposition rate in the central region of the substrate 1. Since the trench 100 in the edge region of the substrate 1 is filled by relatively slow ion deposition, the compactness of the isolation structure formed in the trench 100 in the edge region of the substrate 1 can be increased, so as to prevent the isolation structure in the edge region of the substrate 1 from forming a cavity, thereby improving the filling uniformity of the trench 100 on the substrate 1 and improving the performance of the flash memory.
Preferably, in the present embodiment, the plasma deposition rates sequentially increase in a direction from the edge of the substrate 1 toward the center of the substrate 1. Therefore, the compactness of the isolation structure formed in the trench 100 of the substrate 1 is gradually increased in the direction that the center of the substrate 1 faces the edge of the substrate 1, so that the compactness of the isolation structure filled in the trench 100 of the substrate 1 is more uniform, the filling uniformity of the trench 100 on the substrate 1 is further improved, and the performance of the flash memory is improved.
In step S50, with continued reference to fig. 6, in the present embodiment, the isolation material layer on the mask layer 3 is removed by grinding to form the isolation structure 4 in the trench 100.
Further, the embodiment also provides a flash memory, which is prepared according to the manufacturing method of the flash memory.
It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, similar parts between the embodiments may be referred to each other, and different parts between the embodiments may also be used in combination with each other, which is not limited by the present invention.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (15)
1. A method for manufacturing a flash memory is characterized in that,
providing a substrate;
forming a mask layer on the substrate, wherein a plurality of first openings are formed in the mask layer;
etching the substrate by taking the mask layer as a mask to form a plurality of second openings in the substrate, wherein the second openings and the first openings are communicated to form grooves;
and performing a plasma film deposition process to form an isolation material layer on the trench and the mask layer, wherein the plasma film deposition process is performed at a slower rate in the peripheral region of the substrate than in the central region of the substrate.
And grinding and removing the isolation material layer on the mask layer to form an isolation structure in the trench.
2. The method of claim 1, wherein the plasma deposition rate increases sequentially in a direction from the edge of the substrate toward the center of the substrate.
3. The method of manufacturing a flash memory of claim 1, wherein prior to forming the layer of isolation material, the method further comprises:
and etching the mask layer on the side of the first opening to increase the width of the first opening, wherein the increased width of the first opening is greater than the width of the second opening.
4. The method of manufacturing a flash memory according to claim 3, wherein the method of etching the mask layer located at the side of the first opening is wet etching.
5. The method according to claim 4, wherein the etching solution for wet etching is a hydrofluoric acid solution, and the mass ratio of hydrofluoric acid to water in the hydrofluoric acid solution is: 190: 1-230: 1, and the etching time of the wet etching is 3 min-5 min.
6. The method of manufacturing a flash memory of claim 1, wherein while a plurality of first openings are opened in the mask layer, the method further comprises: the width of the first opening is gradually reduced in a direction from the edge of the substrate toward the center of the substrate.
7. The method of manufacturing a flash memory of claim 1, wherein prior to forming a mask layer on the substrate, the method further comprises: forming a dielectric material layer on the substrate;
and, while etching the substrate with the mask layer as a mask, the method further comprises: and etching the dielectric material layer by taking the mask layer as a mask to form a dielectric layer, and extending the first opening to the dielectric layer to form a plurality of third openings in the dielectric layer.
8. The method of manufacturing a flash memory of claim 7, wherein after forming the dielectric layer, the method further comprises:
and etching the dielectric layer on the side of the third opening to enlarge the third opening, and enabling the enlarged width of the third opening to be equal to the enlarged width of the first opening.
9. The method of manufacturing a flash memory of claim 7, wherein while forming the third opening in the dielectric layer, the method further comprises: gradually decreasing a width of the third opening in a direction from the edge of the substrate toward the center of the substrate.
10. The method of claim 8, wherein the etching of the dielectric layer at the side of the third opening is wet etching.
11. The method for manufacturing the flash memory according to claim 10, wherein the etching solution for the wet etching is a phosphoric acid solution, and the concentration of phosphoric acid in the phosphoric acid solution is: 75-90% and the etching time of the wet etching is 45-80 s.
12. The method of manufacturing a flash memory of claim 1, wherein while forming the second opening in the substrate, the method further comprises: the depth of the second opening is gradually increased in a direction from the edge of the substrate toward the center of the substrate.
13. The method of claim 1, wherein the width of the first opening is 81nm to 99nm, and the width of the second opening is 76nm to 94 nm.
14. The method of claim 1, wherein the trench has a depth of
15. A flash memory prepared according to the method of any one of claims 1 to 14.
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| CN202010884241.2A CN111863706A (en) | 2020-08-28 | 2020-08-28 | Flash memory and manufacturing method thereof |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB9901480D0 (en) * | 1998-01-26 | 1999-03-17 | Samsung Electronics Co Ltd | A method of forming a void free trench isolation |
| KR20000044881A (en) * | 1998-12-30 | 2000-07-15 | 김영환 | Method for forming shallow trench isolation of semiconductor device |
| KR20070026985A (en) * | 2005-08-29 | 2007-03-09 | 삼성전자주식회사 | Method of isolating elements in a semiconductor device |
| US20090127648A1 (en) * | 2007-11-15 | 2009-05-21 | Neng-Kuo Chen | Hybrid Gap-fill Approach for STI Formation |
| US20150093907A1 (en) * | 2013-10-02 | 2015-04-02 | Ellie Yieh | Method and system for three-dimensional (3d) structure fill |
| CN110211919A (en) * | 2019-07-15 | 2019-09-06 | 武汉新芯集成电路制造有限公司 | The forming method of fleet plough groove isolation structure and the forming method of semiconductor devices |
-
2020
- 2020-08-28 CN CN202010884241.2A patent/CN111863706A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB9901480D0 (en) * | 1998-01-26 | 1999-03-17 | Samsung Electronics Co Ltd | A method of forming a void free trench isolation |
| KR20000044881A (en) * | 1998-12-30 | 2000-07-15 | 김영환 | Method for forming shallow trench isolation of semiconductor device |
| KR20070026985A (en) * | 2005-08-29 | 2007-03-09 | 삼성전자주식회사 | Method of isolating elements in a semiconductor device |
| US20090127648A1 (en) * | 2007-11-15 | 2009-05-21 | Neng-Kuo Chen | Hybrid Gap-fill Approach for STI Formation |
| US20150093907A1 (en) * | 2013-10-02 | 2015-04-02 | Ellie Yieh | Method and system for three-dimensional (3d) structure fill |
| CN110211919A (en) * | 2019-07-15 | 2019-09-06 | 武汉新芯集成电路制造有限公司 | The forming method of fleet plough groove isolation structure and the forming method of semiconductor devices |
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