CN117080168A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN117080168A
CN117080168A CN202210499985.1A CN202210499985A CN117080168A CN 117080168 A CN117080168 A CN 117080168A CN 202210499985 A CN202210499985 A CN 202210499985A CN 117080168 A CN117080168 A CN 117080168A
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China
Prior art keywords
material layer
channel material
layer
forming
oxidation
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CN202210499985.1A
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Chinese (zh)
Inventor
汤汉杰
王洪岩
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN202210499985.1A priority Critical patent/CN117080168A/en
Publication of CN117080168A publication Critical patent/CN117080168A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a first region for forming a first device and a second region for forming a second device, and a first channel material layer formed on the substrate, and the first channel material layer of the first region is used for forming a channel of the first device; forming a hard mask layer on the first channel material layer; forming an opening in the hard mask layer and the first channel material layer in the second region; filling a second channel material layer in the opening, wherein the second channel material layer is used for forming a channel of a second device; forming an oxidation-preventing sacrificial layer covering the second channel material layer; removing the hard mask layer after forming the oxidation-preventing sacrificial layer; and after the hard mask layer is removed, flattening the oxidation-preventing sacrificial layer and the second channel material layer which are higher than the top surface of the first channel material layer. The embodiment of the invention is beneficial to improving the performance of the semiconductor device.

Description

Method for forming semiconductor structure
Technical Field
The embodiment of the invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
The fabrication of semiconductor integrated circuits (Integarted Circuit, ICs) utilizes a series of processes such as photolithography, etching, implantation, and deposition to form various types of complex devices on the same substrate and interconnect them to achieve complete electronic functionality. With the rapid development of very large scale integrated circuits, the integration level of chips is higher and higher, the size of components is smaller and smaller, and the influence of various effects caused by high density and small size of components on the manufacturing result of semiconductor processes is also increasingly prominent.
The flatness of the wafer plays a critical role in the quality of the semiconductor device. A wafer with poor flatness can adversely affect the device manufacturing process. Such as: uneven contact between the uneven wafer and the substrate during the epitaxial growth process can cause uneven thermal field distribution on the wafer surface, thereby causing uneven stress distribution within the wafer.
Currently, the performance of semiconductor devices is still to be improved under the influence of flatness factors.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a method for forming a conductor structure, which improves the performance of a semiconductor device.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base comprising a substrate and a first channel material layer formed on the substrate, wherein the base comprises a first region for forming a first device and a second region for forming a second device, and the first channel material layer of the first region is used for forming a channel of the first device; forming a hard mask layer on the first channel material layer; forming openings in the hard mask layer and the first channel material layer in the second region; filling a second channel material layer in the opening, wherein the second channel material layer is used for forming a channel of the second device; forming an oxidation-preventing sacrificial layer covering the second channel material layer; removing the hard mask layer after the oxidation-preventing sacrificial layer is formed; and after the hard mask layer is removed, flattening the oxidation-preventing sacrificial layer and the second channel material layer which are higher than the top surface of the first channel material layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming the semiconductor structure provided by the embodiment of the invention, the oxidation preventing sacrificial layer covering the second channel material layer is formed, and the formed oxidation preventing sacrificial layer can protect the second channel material layer positioned below the oxidation preventing sacrificial layer when the hard mask layer is removed, so that the probability of oxide formation caused by oxidation on the surface of the second channel material layer is reduced; and the material of the oxidation preventing sacrificial layer is easy to reasonably select, so that the probability that the oxidation preventing sacrificial layer blocks the second channel material layer in planarization treatment is reduced, the consistency of the removal rate of the second channel material layer in each region is improved, the flatness of the second channel material layer after the planarization treatment and the top surface height difference (step height) between the second channel material layer and the first channel material layer can be improved, and the performance of the semiconductor device is improved correspondingly.
Drawings
Fig. 1 to 6 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
FIG. 7 illustrates a partial electron microscope image of a semiconductor structure formed by a semiconductor formation method;
fig. 8 to 15 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention;
fig. 16 shows a partial electron microscope image of a semiconductor structure formed by the method of forming a semiconductor according to an embodiment of the present invention.
Detailed Description
As known from the background art, the performance of the semiconductor device is required to be improved. The reason why the performance of a semiconductor device is to be improved is now analyzed in conjunction with a method of forming a semiconductor structure. Fig. 1 to 6 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1, a base 100 is provided, including a substrate 1001 and a first channel material layer 1002 formed on the substrate 1001, the base 100 including a first region I for forming a first device, and a second region II for forming a second device, the first channel material layer 1002 of the first region I being for forming a channel of the first device.
Referring to fig. 2, a mask stack 180 is formed on the substrate 100, and the mask stack 180 includes a planarization stop layer 101 and a hard mask layer 103 stacked in order from bottom to top.
Referring to fig. 3, in the second region II, an opening 110 in the hard mask layer 103 and the first channel material layer 1002 is formed.
Referring to fig. 4, a second channel material layer 111 is filled in the opening 110, and the second channel material layer 111 is used to form a channel of the second device.
Referring to fig. 5, the hard mask layer 103 is removed.
Referring to fig. 6, the second channel material layer 111 is planarized.
When the hard mask layer 103 is removed, the surface of the second channel material layer 111 is easily oxidized, thereby forming an oxide 119 on the surface of the second channel material layer 111.
When the second channel material layer 111 is planarized, the removal rate of the oxide 119 is lower than the removal rate of the second channel material layer 111, and the areas of the oxide 119 located in the respective regions may be inconsistent due to the inconsistent opening sizes of the openings 110 in the respective regions, and furthermore, due to the influence of the low flatness of the second channel material layer 111 itself and the difference in the height of the top surface of the second channel material layer 111 in the respective regions, it is difficult to ensure that the oxide 119 in the respective regions is simultaneously removed, and due to the influence of the above factors, the removal rate of the second channel material layer 111 in the respective regions is inconsistent, which in turn leads to the low flatness of the second channel material layer 111 and the high difference in the height of the top surface between the second channel material layer 111 and the first channel material layer 1002 after the planarization of the second channel material layer 111, which in turn easily leads to the performance degradation of the semiconductor device.
For example, referring to fig. 7, fig. 7 shows a partial electron microscope image of a semiconductor structure formed by a semiconductor forming method. Fig. 7 shows that the second channel material layer 111 and the first channel material layer 1002 have a top surface height difference a, and the second channel material layer 111 has a low flatness.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base comprising a substrate and a first channel material layer formed on the substrate, wherein the base comprises a first region for forming a first device and a second region for forming a second device, and the first channel material layer of the first region is used for forming a channel of the first device; forming a hard mask layer on the first channel material layer; forming openings in the hard mask layer and the first channel material layer in the second region; filling a second channel material layer in the opening, wherein the second channel material layer is used for forming a channel of the second device; forming an oxidation-preventing sacrificial layer covering the second channel material layer; removing the hard mask layer after the oxidation-preventing sacrificial layer is formed; and after the hard mask layer is removed, flattening the oxidation-preventing sacrificial layer and the second channel material layer which are higher than the top surface of the first channel material layer.
In the method for forming a semiconductor structure provided by the embodiment of the invention, an anti-oxidation sacrificial layer covering the second channel material layer is formed, the anti-oxidation sacrificial layer is formed, the hard mask layer can be removed, the second channel material layer below the anti-oxidation sacrificial layer is protected, and the probability of oxide formation due to oxidation on the surface of the second channel material layer is reduced; and the material of the oxidation-preventing sacrificial layer is easy to reasonably select, so that the probability that the oxidation-preventing sacrificial layer blocks the second channel material layer in planarization treatment is reduced, the consistency of the removal rate of the second channel material layer in each region is improved, the flatness of the second channel material layer after planarization treatment and the top surface height difference between the second channel material layer and the first channel material layer are improved, and the performance of the semiconductor device is correspondingly improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 8 to 15 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 8, a base 200 is provided, comprising a substrate 2001 and a first channel material layer 2002 formed on said substrate 2001, said base 200 comprising a first region I for forming a first device, and a second region II for forming a second device, said first region I first channel material layer 2002 being for forming a channel of said first device.
The substrate 200 is used to provide a process platform for forming semiconductor structures.
In this embodiment, the substrate 200 is a silicon substrate, i.e., the material of the substrate 200 is monocrystalline silicon. In other embodiments, the substrate material may be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide, and the substrate may be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The substrate 2001 is used to provide support for subsequently formed fins and to provide a process platform for subsequent processing after the fins are formed.
The first channel material layer 2002 is then patterned to form channels of the first device.
In this embodiment, the material of the first channel material layer 2002 is silicon. In other embodiments, the material of the first channel material layer 2002 may also be silicon germanium. In other embodiments, the material of the first channel material layer may be other materials that are suitable for use as a channel and meet the performance requirements of the first device.
In this embodiment, the first device is an NMOS device, and the second device is a PMOS device.
The first channel material layer 2002 is used for forming a channel of a first device later, and the substrate 200 is a silicon substrate, so that the substrate 200 can meet the requirements of an NMOS device for channel materials.
In other embodiments, the first device may be a PMOS device and the second device may be an NMOS device.
In other embodiments, the first device and the second device may also be devices having the same channel conductivity type (e.g., both NMOS devices or both PMOS devices), but different channel materials.
In this embodiment, the base 200 includes a substrate 2001 and a first channel material layer 2002 formed on the substrate 2001, where the substrate 2001 and the first channel material layer 2002 are integrally formed.
In other embodiments, the first channel material layer 2002 may also be a film layer formed on the substrate by an epitaxial process, depending on the actual process requirements. Accordingly, the materials of the first channel material layer and the substrate may be the same or different.
It should be noted that, in this embodiment, the substrate 200 includes a pattern sparse region (not labeled) and a pattern dense region (not labeled), the pattern density of the pattern sparse region is lower than that of the pattern dense region, and the pattern dense region and the pattern sparse region both include the first region I and the second region II.
Specifically, the pattern sparse region is a region in which the size of an opening subsequently formed in the first channel material layer 2002 is large; the pattern-dense region is a region where the size of an opening subsequently formed in the first channel material layer 2002 is smaller.
Referring to fig. 9, a hard mask layer 203 is formed on the first channel material layer 2002.
The hard mask layer 203 is used as an etching mask for subsequently etching the first channel material layer 2002.
In this embodiment, the material of the hard mask layer 203 is silicon nitride.
Specifically, the process of forming the hard mask layer 203 includes a chemical vapor deposition (Chemical Vapor Deposition, CVD) process, thereby facilitating the formation of a dense and uniform hard mask layer 203. In other embodiments, the process of forming the mask material layer further includes a furnace tube process, an epitaxial process, or an atomic layer deposition process.
With continued reference to fig. 9, in this embodiment, before forming the hard mask layer 203 on the first channel material layer 2002, the method further includes: a planarization stop layer 201 is formed on the first channel material layer 2002.
After forming the openings in the hard mask layer 203 and the first channel material layer 2002 in the second region II, a second channel material layer may be further filled in the openings, and the planarization stop layer 201 is used to protect the substrate 200 and the second channel material layer.
Specifically, the hard mask layer 203 is formed on the planarization stop layer 201, and when the hard mask layer 203 is subsequently removed, the planarization stop layer 201 can protect the substrate 200 and the second channel material layer, so as to reduce damage to the substrate 200 and the second channel material layer caused by a planarization process.
In addition, the top surface of the planarization stop layer 201 can define an etch stop position when patterning the hard mask layer 203 later, thereby reducing the probability of causing an erroneous etch to the substrate 200 and the second channel material layer.
In this embodiment, when the planarization stop layer 201 is removed later, a higher selection ratio is made between the material of the planarization stop layer 201 and the material of the substrate 200, so that damage to the substrate 200 and the second channel material layer is reduced.
As an example, the material of the planarization stop layer 201 is silicon oxide. In other embodiments, the material of the planarization stop layer 201 further includes one or more of silicon nitride, a low dielectric constant (LowK) dielectric layer, a metal oxide, and a metal nitride. Here, low dielectric constant means that the dielectric constant K is less than 3.9.
Referring to fig. 10, in the second region II, openings in the hard mask layer 203 and the first channel material layer 2002 are formed.
The openings 210 are used to provide a forming space for a subsequent formation of a second channel material layer.
Specifically, before forming the opening 210 in the hard mask layer 203 and the first channel material layer 2002, the method further includes: forming a photoresist layer (not shown) on the hard mask layer 203; the photoresist layer is patterned by means of exposure and development to form a patterned layer (not shown). Specifically, the photoresist layer may be formed by coating.
The photoresist layer is converted into a pattern layer by means of exposure and development, thereby defining the position of the opening 210.
In this embodiment, the hard mask layer 203 is etched by using the pattern layer as a mask; accordingly, the planarization stop layer 201 and the first channel material layer 2002 are continuously etched with the hard mask layer 203 remaining after etching as a mask, so as to form openings 210 in the hard mask layer 203, the planarization stop layer 201 and the first channel material layer 2002.
It should be noted that, in other embodiments, after etching the first channel material layer in the second region, a portion of the thickness of the substrate may also be etched, so that the bottom of the opening is located in the portion of the thickness of the substrate.
Referring to fig. 11, a second channel material layer 211 is filled in the opening 210, and the second channel material layer 211 is used to form a channel of the second device.
A channel of the second device can be formed subsequently by patterning the second channel material layer 211.
In this embodiment, the second channel material layer 211 is formed by an epitaxial process, so as to improve the quality of forming the second channel material layer 211. In other embodiments, the process of forming the second channel material layer 211 further includes a chemical vapor deposition process, a furnace tube process, or an atomic layer deposition process.
The pattern dense region has a smaller opening size, and the pattern sparse region has a larger opening size, so that the second channel material layer 211 formed in the opening 210 having a smaller opening size has a larger thickness at the same time.
In this embodiment, the top surface of the second channel material layer 211 is higher than the top surface of the first channel material layer 2002, so that it is beneficial to provide enough process windows for the subsequent planarization treatment of the second channel material layer 211, and further to improve the flatness of the top surfaces of the second channel material layer 211 and the first channel material layer 2002 after the planarization treatment.
The material of the second channel material layer 211 is determined according to the performance requirement of the second device. In this embodiment, the second device is a PMOS device, and therefore, the material of the second channel material layer 211 is silicon germanium. In other embodiments, the second channel material layer 211 may also be formed of silicon. In other embodiments, the material of the second channel material layer may be other materials suitable for use as a channel and meeting the performance requirements of the second device.
Referring to fig. 12, an oxidation preventing sacrificial layer 208 is formed to cover the second channel material layer 211.
The oxidation preventing sacrificial layer 208 is used for protecting the second channel material layer 211 below the oxidation preventing sacrificial layer 208, so that the probability of oxide formation due to oxidation on the surface of the second channel material layer 211 is reduced. Also, the oxidation resistance of the oxidation preventing sacrificial layer 208 is lower than that of the second channel material layer 211, thereby reducing the probability that the oxidation preventing sacrificial layer 208 is oxidized.
Specifically, forming the oxidation preventing sacrificial layer 208 covering the second channel material layer 211 includes: and selectively depositing the surface of the second channel material layer 211, and forming an oxidation-preventing sacrificial layer 208 on the surface of the second channel material layer 211.
In this embodiment, the surface of the second channel material layer 211 is selectively deposited, and the second channel material layer 211 may be selectively formed on the surface of the second channel material layer 211, so that the oxidation-preventing sacrificial layer 208 is formed on the surface of the second channel material layer 211 accurately, thereby facilitating the reduction of the process flow and the saving of the process cost.
Specifically, the process of forming the oxidation preventing sacrificial layer 208 includes a selective epitaxy process, thereby facilitating the formation of the oxidation preventing sacrificial layer 208 which is thin and uniform in thickness.
In other embodiments, forming the oxidation preventing sacrificial layer includes: forming an oxidation-preventing sacrificial material layer on the first channel material layer and the hard mask layer; and removing the oxidation preventing sacrificial material layer on the hard mask layer, and reserving the oxidation preventing sacrificial material layer on the second channel material layer as an oxidation preventing sacrificial layer.
In this embodiment, in the step of forming the oxidation preventing sacrificial layer 208 covering the second channel material layer 211, the thickness of the oxidation preventing sacrificial layer 208 is not too small or too large. If the thickness of the oxidation preventing sacrificial layer 208 is too small, the protection effect of the oxidation preventing sacrificial layer 208 on the second channel material layer 211 is easily poor, and the probability of forming oxide due to oxidation of the surface of the second channel material layer 211 is increased; if the thickness of the anti-oxidation sacrificial layer 208 is too large, more time is required to remove the anti-oxidation sacrificial layer 208 when the planarization process is performed later, which is disadvantageous to the improvement of the process efficiency. For this reason, in the present embodiment, the thickness of the oxidation preventing sacrificial layer 208 is 20 to 60 angstroms.
In this embodiment, in the step of forming the oxidation preventing sacrificial layer 208 covering the second channel material layer 211, the material of the oxidation preventing sacrificial layer 208 satisfies: when planarization is performed subsequently, the removal rates of the oxidation preventing sacrificial layer 208 and the second channel material layer 211 are close to each other, so that the probability that the oxidation preventing sacrificial layer 208 blocks the second channel material layer 211 in the planarization process can be reduced, thereby being beneficial to improving the uniformity of the removal rate of the second channel material layer 211 in each region, further improving the flatness of the second channel material layer 211 after the planarization process, and improving the top surface height difference between the second channel material layer 211 and the first channel material layer 2002, and correspondingly being beneficial to improving the performance of the semiconductor device.
As an example, the material of the oxidation preventing sacrificial layer 208 is silicon. Silicon has better oxidation resistance than silicon germanium, and silicon is also a semiconductor material, which is closer to the material of the channel material layer, and thus it is easy to make planarization approach the removal rate of the oxidation-preventing sacrificial layer 208 and the second channel material layer 211.
Referring to fig. 13, after the oxidation preventing sacrificial layer 208 is formed, the hard mask layer 203 is removed.
The hard mask layer 203 is removed, thereby providing a process basis for subsequent planarization of the second channel material layer 211.
In this embodiment, after the second channel material layer 211 is filled in the opening 210, the hard mask layer 203 is removed, and during the process of performing an epitaxial process in the opening 210 to form the second channel material layer 211, the probability of performing epitaxial growth on the surface of the hard mask layer 203 on the second channel material layer 211 is low, so that the formation position of the second channel material layer 211 is limited in the opening 210.
In this embodiment, the process of removing the hard mask layer 203 is a wet etching process, and the wet etching process is easy to realize a relatively high etching selectivity, so as to remove the hard mask layer 203.
Referring to fig. 14 and 15, after the hard mask layer 203 is removed, planarization is performed on the oxidation preventing sacrificial layer 208 and the second channel material layer 211, which are higher than the top surface of the first channel material layer 2002.
The oxidation preventing sacrificial layer 208 and the second channel material layer 211 are planarized above the top surface of the first channel material layer 2002, thereby providing a process basis for subsequent processing (e.g., patterning the second channel material layer 211 and the substrate 200 to form fins protruding above the remaining thickness of the substrate 2001).
When planarization is performed, since the removal rates of the oxidation preventing sacrificial layer 208 and the second channel material layer 211 are close to each other, the probability that the oxidation preventing sacrificial layer 208 blocks the second channel material layer 211 in the planarization process can be reduced, so that uniformity of the removal rate of the second channel material layer 211 in each region is improved, flatness of the second channel material layer 211 after planarization is improved, and a top surface height difference between the second channel material layer 211 and the first channel material layer 2002 is improved, which is also beneficial to improving performance of the semiconductor device.
Referring in conjunction to fig. 16, a partial electron microscope image of a semiconductor structure formed using the method of forming a semiconductor of an embodiment of the present invention is shown. As can be seen from fig. 16, after the planarization process, the difference in top surface height between the second channel material layer 211 and the first channel material layer 2002 is small.
With continued reference to fig. 14, planarizing the oxidation preventing sacrificial layer 208 and the second channel material layer 211 above the top surface of the first channel material layer 2002 includes: the first planarization process is performed on the oxidation preventing sacrificial layer 208 and the second channel material layer 211 with the top surface of the planarization stop layer 201 as a stop position.
The first planarization process is advantageous for removing the oxidation preventing sacrificial layer 208 and the second channel material layer 211 located above the planarization stop layer 201, and is advantageous for providing a relatively flat surface for a subsequent second planarization process.
In this embodiment, the ratio of the removal rates of the second channel material layer 211 and the planarization stop layer 201 should not be too small. If the ratio of the removal rates of the second channel material layer 211 and the planarization stop layer 201 is too small, it is easy to damage the planarization stop layer 201 when the second channel material layer 211 is removed, so that it is difficult to define a stop position of the first planarization process by the top surface of the planarization stop layer 201. For this reason, in the present embodiment, in the first planarization process, the removal rate ratio of the second channel material layer 211 to the planarization stop layer 201 is greater than 40.
In this embodiment, the ratio of the removal rates of the second channel material layer 211 to the oxidation preventing sacrificial layer 208 is not too small or too large in the planarization process of the oxidation preventing sacrificial layer 208 and the second channel material layer 211 above the top surface of the first channel material layer 2002. If the ratio of the removal rates of the second channel material layer 211 and the oxidation preventing sacrificial layer 208 is too small, it is easy to cause a low removal rate of the second channel material layer 211, and the surface height of the second channel material layer 211 is higher than the top surface height of the oxidation preventing sacrificial layer 208, it is difficult to rapidly remove the second channel material layer 211 higher than the top surface of the planarization stop layer 201, thereby reducing the effect of the planarization treatment on the second channel material layer 211; if the ratio of the removal rates of the second channel material layer 211 and the oxidation preventing sacrificial layer 208 is too large, the removal rate of the oxidation preventing sacrificial layer 208 is easily too small, and the process time of the first planarization process may be too long when the oxidation preventing sacrificial layer 208 and the second channel material layer 211 above the top surface of the planarization stop layer 201 are removed, so that the probability that the thickness of the second channel material layer 211 is too small after the first planarization process is increased. For this reason, in the present embodiment, in the first planarization process, the ratio of the removal rates of the second channel material layer 211 and the oxidation preventing sacrificial layer 208 is 0.9 to 1.1, thereby facilitating the removal rates of the oxidation preventing sacrificial layer 208 and the second channel material layer 211 to be close.
In this embodiment, the planarization process is a chemical mechanical polishing process, so that the overall flatness and integrity of the first channel material layer 2002 and the second channel material layer 211 are advantageously improved.
Referring to fig. 15, after the first planarization process, a second planarization process is performed on the planarization stop layer 201 and the second channel material layer 211.
The planarization stop layer 201 and the second channel material layer 211 are subjected to a second planarization process to remove the planarization stop layer 201 and the second channel material layer 211 higher than the top of the first channel material layer 2002.
Specifically, in the second planarization process, the ratio of the removal rates of the second channel material layer 211 and the planarization stop layer 201 should not be too small nor too large; if the ratio of the removal rates of the second channel material layer 211 and the planarization stop layer 201 is too small, the removal rate of the second channel material layer 211 is too low, which easily causes the planarization stop layer 201 to be removed first, thereby increasing the probability of damage to the first channel material layer 2002; if the ratio of the removal rates of the second channel material layer 211 and the planarization stop layer 201 is too large, the removal rate of the second channel material layer 211 is easily caused to be too large, and accordingly, more time is required to remove the planarization stop layer 201, in which the removal amount of the second channel material layer 211 is easily caused to be too large, resulting in poor surface planarization of the second channel material layer 211. For this reason, in the present embodiment, the ratio of the removal rates of the planarization stop layer 201 and the second channel material layer 211 is 0.9 to 1.1.
In this embodiment, after the planarization process is performed on the second channel material layer 211, the method further includes: the second channel material layer 211 and the base 200 are patterned to form fins (not shown) protruding over the remaining thickness of the substrate, the fins being located on the remaining thickness of the substrate in the first region I and the second region II, respectively.
As an example, the first channel material layer 2002, the second channel material layer 211, and a portion of the thickness of the substrate 2001 are patterned to form fins protruding above the remaining thickness of the substrate 2001.
Accordingly, the first channel material layer 2002 is used to form a fin located in the first region I, and the second channel material layer 211 is used to form a fin located in the second region II, so that the first device formed in the first region I and the second device formed in the second region II have channels of different materials.
Specifically, descriptions of subsequent steps are not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (13)

1. A method of forming a semiconductor structure, comprising:
providing a base comprising a substrate and a first channel material layer formed on the substrate, wherein the base comprises a first region for forming a first device and a second region for forming a second device, and the first channel material layer of the first region is used for forming a channel of the first device;
forming a hard mask layer on the first channel material layer;
forming openings in the hard mask layer and the first channel material layer in the second region;
filling a second channel material layer in the opening, wherein the second channel material layer is used for forming a channel of the second device;
forming an oxidation-preventing sacrificial layer covering the second channel material layer;
removing the hard mask layer after the oxidation-preventing sacrificial layer is formed;
and after the hard mask layer is removed, flattening the oxidation-preventing sacrificial layer and the second channel material layer which are higher than the top surface of the first channel material layer.
2. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming a hard mask layer over the first channel material layer: forming a planarization stop layer on the first channel material layer;
the hard mask layer is formed on the planarization stop layer.
3. The method of forming a semiconductor structure of claim 2, wherein planarizing the oxidation-preventing sacrificial layer and the second channel material layer above the top surface of the first channel material layer comprises: taking the top surface of the planarization stop layer as a stop position, and performing first planarization treatment on the oxidation-preventing sacrificial layer and the second channel material layer;
and after the first planarization treatment, carrying out second planarization treatment on the planarization stop layer and the second channel material layer.
4. The method of forming a semiconductor structure of claim 3, wherein a ratio of removal rates of said second channel material layer and said planarization stop layer in said first planarization process is greater than 40.
5. The method of forming a semiconductor structure of claim 3, wherein a ratio of removal rates of the planarization stop layer and the second channel material layer in the second planarization process is 0.9 to 1.1.
6. The method of forming a semiconductor structure according to any one of claims 1 to 5, wherein a ratio of removal rates of the second channel material layer and the oxidation preventing sacrificial layer during planarization of the oxidation preventing sacrificial layer and the second channel material layer higher than a top surface of the first channel material layer is 0.9 to 1.1.
7. The method of forming a semiconductor structure according to any one of claims 1 to 5, wherein in the step of providing a substrate, the material of the first channel material layer comprises silicon or silicon germanium; in the step of providing a substrate, the material of the second channel material layer includes silicon germanium or silicon.
8. The method for forming a semiconductor structure according to any one of claims 1 to 5, wherein in the step of forming an oxidation preventing sacrificial layer covering the second channel material layer, a material of the oxidation preventing sacrificial layer includes: silicon.
9. The method of forming a semiconductor structure according to any one of claims 1 to 5, wherein in the step of forming an oxidation preventing sacrificial layer covering the second channel material layer, a thickness of the oxidation preventing sacrificial layer is 20 to 60 angstroms.
10. The method of forming a semiconductor structure according to any one of claims 1 to 5, wherein forming an oxidation-preventing sacrificial layer covering the second channel material layer comprises: and selectively depositing the surface of the second channel material layer, and forming an oxidation-preventing sacrificial layer on the surface of the second channel material layer.
11. The method of forming a semiconductor structure of any of claims 10, wherein the selective deposition process comprises: a selective epitaxy process.
12. The method of forming a semiconductor structure according to any one of claims 1 to 5, wherein forming the oxidation-preventing sacrificial layer comprises: forming an oxidation-preventing sacrificial material layer on the first channel material layer and the mask layer; and removing the oxidation preventing sacrificial material layer on the hard mask layer, and reserving the oxidation preventing sacrificial material layer on the second channel material layer as an oxidation preventing sacrificial layer.
13. The method of forming a semiconductor structure according to any one of claims 1 to 5, wherein in the step of filling the opening with a second channel material layer, a top surface of the second channel material layer is higher than a top surface of the first channel material layer.
CN202210499985.1A 2022-05-09 2022-05-09 Method for forming semiconductor structure Pending CN117080168A (en)

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CN117080168A true CN117080168A (en) 2023-11-17

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