CN111858217B - Hierarchical verification method, platform, equipment and storage medium - Google Patents
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Abstract
The invention discloses a hierarchical verification method, a platform, a device and a storage medium, wherein the platform comprises: an energizing top layer for: defining top-level excitations, wherein each top-level excitation corresponds to different values of a variable of the same enumeration type, and the different values of the variable correspond to different bottom-level excitations; an excitation substrate for: defining underlying stimuli, each underlying stimulus having a different data format, and the different data formats corresponding to different buses; a top sequence layer for: storing top-level sequences respectively corresponding to different top-level excitations, and generating corresponding top-level excitations by utilizing the top-level sequences; a sequence bottom layer for: storing bottom layer sequences respectively corresponding to different bottom layer excitations, and generating the bottom layer excitations by utilizing the corresponding bottom layer sequences after determining the bottom layer excitations corresponding to the top layer excitations generated by the top layer of the sequences. Therefore, the excitation corresponding to the bus protocols of different buses can be generated, and the reusability of the platform is greatly improved.
Description
Technical Field
The present invention relates to the field of UVM technologies, and in particular, to a hierarchical verification method, a hierarchical verification platform, a hierarchical verification device, and a storage medium.
Background
The UVM (Universal Verification Methodology) is a Verification Methodology based on SystemVerilog, and the reusability and normalization of a test can be enhanced by establishing a Verification platform by using the UVM; in a verification platform built by a universal UVM, a driver and a sequence are parameterized, one verification platform usually only comprises one sequence, and one sequence can only generate one type of excitation (transaction) for driving, but various different bus protocols are usually used in chip testing, and at the moment, different sequences are required to be used for different bus protocols to generate different excitations, so that the verification platform built by the universal UVM cannot generate excitations corresponding to different bus protocols, and the reusability is low.
Disclosure of Invention
The invention aims to provide a hierarchical verification method, a platform, equipment and a storage medium, different bus types are integrated into the same platform through a hierarchical design, and corresponding excitation of bus protocols of different buses can be generated, so that the reusability of the platform is greatly improved.
In order to achieve the above purpose, the invention provides the following technical scheme:
a hierarchical verification platform comprises an excitation top layer, an excitation bottom layer, a sequence top layer and a sequence bottom layer; wherein:
the excitation top layer is used for: defining top-level excitations, wherein each top-level excitation corresponds to different values of a variable of the same enumeration type, and the different values of the variable correspond to different bottom-level excitations;
the excitation substrate is used for: defining underlying stimuli, each of said underlying stimuli having a different data format, and said different data formats corresponding to different buses;
the sequence top layer is used for: storing top layer sequences respectively corresponding to different top layer excitations, and generating corresponding top layer excitations by utilizing the top layer sequences;
the sequence bottom layer is used for: storing bottom layer sequences respectively corresponding to the different bottom layer excitations, and generating the bottom layer excitations by utilizing the corresponding bottom layer sequences after determining the bottom layer excitations corresponding to the top layer excitations generated by the top layer of the sequences.
Preferably, the device also comprises a driving layer and a total sequence layer;
the total sequence layer is used for: acquiring bottom layer excitation generated by the sequence bottom layer, sending the acquired bottom layer excitation to the driving layer, and caching backup of the acquired bottom layer excitation;
the driving layer is used for: and if the bottom layer excitation sent by the total sequence layer is successfully received, sending the received bottom layer excitation to the device under test, otherwise, instructing the total sequence layer to resend the cached backup of the bottom layer excitation to the drive layer.
Preferably, the driving layer is further configured to: if the bottom layer excitation sent by the total sequence layer is successfully received, returning the information of successful reception to the total sequence layer;
the total sequence layer is further to: and if the information of successful receiving sent by the driving layer is received, deleting the cached backup of the bottom layer excitation.
Preferably, the monitoring system further comprises a monitoring layer, wherein the monitoring layer is used for: and counting the coverage rate obtained by the equipment under test by utilizing the received bottom layer excitation to realize the test, and indicating the equipment under test to carry out random test when the coverage rate does not reach the coverage rate threshold value until the coverage rate obtained by the equipment under test to realize the test reaches the coverage rate threshold value.
Preferably, the monitoring layer is further configured to: and if the times of the random test of the equipment in the test reaches a time threshold value and the coverage rate of the equipment in the test, which is obtained by realizing the test, does not reach the coverage rate threshold value, outputting corresponding alarm information.
Preferably, the monitoring layer is further configured to: and if the times of the random test of the equipment in the test does not reach the time threshold value and the coverage rate of the equipment in the test for realizing the test reaches the coverage rate threshold value, outputting corresponding test completion information.
Preferably, the hierarchical verification platform is built based on UVM, and the driving layer and the total sequence layer are both encapsulated in an env layer of the hierarchical verification platform.
A hierarchical verification method, comprising:
generating a corresponding top-level stimulus using the top-level sequence; wherein, different top-level sequences correspond to different top-level excitations, and the different top-level excitations correspond to different values of a variable of the same enumeration type, and the different values of the variable correspond to different bottom-level excitations;
determining a bottom layer excitation corresponding to the generated top layer excitation, and generating the bottom layer excitation by using a bottom layer sequence corresponding to the bottom layer excitation; wherein different underlying sequences correspond to different underlying stimuli and the different underlying stimuli have different data formats, the different data formats corresponding to different buses.
A hierarchical verification device comprising:
a memory for storing a computer program;
a processor for implementing the steps of the hierarchical verification method as described above when executing the computer program.
A computer-readable storage medium, having stored thereon a computer program which, when being executed by a processor, carries out the steps of the hierarchical verification method as set forth above.
The embodiment of the invention provides a hierarchical verification method, a platform, equipment and a storage medium, wherein the platform can comprise an excitation top layer, an excitation bottom layer, a sequence top layer and a sequence bottom layer; wherein: the excitation top layer is used for: defining top-level excitations, wherein each top-level excitation corresponds to different values of a variable of the same enumeration type, and the different values of the variable correspond to different bottom-level excitations; the excitation substrate is used for: defining underlying stimuli, each of the underlying stimuli having a different data format, the different data formats corresponding to different buses; the sequence top layer is used for: storing top-level sequences respectively corresponding to different top-level excitations, and generating corresponding top-level excitations by utilizing the top-level sequences; the sequence bottom layer is used for: storing bottom layer sequences respectively corresponding to different bottom layer excitations, and generating the bottom layer excitation by utilizing the corresponding bottom layer sequence after determining the bottom layer excitation corresponding to the top layer excitation generated by the top layer of the sequences. In the technical scheme provided by the application, the excitation top layer defines top layer excitation corresponding to different values of variables of the same enumeration type, and the different values of the variable correspond to different bottom layer excitations, the excitation bottom layer defines bottom layer excitations corresponding to the data formats of different buses respectively, the sequence top layer comprises top layer sequences corresponding to the different top layer excitations respectively, the sequence bottom layer comprises bottom layer sequences corresponding to the different bottom layer excitations respectively, so that when the corresponding excitation of a certain bus needs to be generated, after the top layer excitation is generated by using the corresponding top layer sequence, the bottom layer excitation is generated by using the bottom layer sequence of the corresponding bottom layer excitation of the top layer excitation, therefore, the generation of corresponding excitation of the bus is realized, and the application integrates different bus types into the same platform through hierarchical design, the excitation corresponding to the bus protocols of different buses can be generated, so that the reusability of the platform is greatly improved.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a hierarchical verification platform according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
Referring to fig. 1, a hierarchical verification platform provided by an embodiment of the present invention is shown, which may include an excitation top layer, an excitation bottom layer, a sequence top layer, and a sequence bottom layer; wherein:
an energizing top layer for: defining top layer excitation, wherein each top layer excitation corresponds to different values of a variable of the same enumeration type, and the different values of the variable correspond to different bottom layer excitations;
an excitation underlayer for: defining underlying stimuli, each underlying stimulus having a different data format, and the different data formats corresponding to different buses;
a top sequence layer for: storing top layer sequences respectively corresponding to different top layer excitations, and generating corresponding top layer excitations by utilizing the top layer sequences;
a sequence bottom layer for: storing bottom layer sequences respectively corresponding to different bottom layer excitations, and generating the bottom layer excitations by utilizing the corresponding bottom layer sequences after determining the bottom layer excitations corresponding to the top layer excitations generated by the top layer of the sequences.
The hierarchical verification platform provided by the embodiment of the application can be a verification platform built based on UVM, and the excitation (Transaction) and the Sequence (Sequence) have the same meaning as the corresponding concepts in the prior art, and are not described herein again. The method comprises the steps that four layers are arranged in a hierarchical verification platform, namely an excitation bottom layer, an excitation top layer, a sequence bottom layer and a sequence top layer; the excitation top layer is an abstract layer, an enumeration type variable is defined in the excitation top layer, different values (or different names) in an enumeration set, which can be taken by the corresponding variable, represent corresponding different bottom layer excitations, that is, the different values of the variable correspond to the different bottom layer excitations, and the essence of the top layer excitation defining variable is also the definition top layer excitation as the generated top layer excitation is actually the value of the variable defined by the excitation top layer; the excitation bottom layer defines data frames or packets corresponding to different buses respectively, and sets constraints according to bus protocols of different buses, wherein the buses can include an apb bus (advanced peripheral bus) in an AMBA (advanced microcontroller bus), an ahb bus (advanced high-performance bus), a asb bus (advanced system bus) and an axi bus (high-speed expandable interface), and because data exchange in a physical protocol is based on frames (short for data frames) or packets (short for data packets), various parameters are defined in one frame or one packet, the size of each frame or packet is different, and an excitation is actually a frame or packet, so that the excitation bottom layer defines the data frames or packets corresponding to different buses as bottom layer excitations defining data formats corresponding to different buses; the sequence top layer comprises corresponding top layer sequences, and different top layer excitations can be generated by using different top layer sequences; the sequence bottom layer contains corresponding bottom layer sequences, and different bottom layer excitations can be generated by using different bottom layer sequences.
The working process of the hierarchical verification platform in the embodiment of the application may include: if the bottom layer excitation corresponding to a certain bus needs to be generated, the top layer excitation can be generated by using the corresponding top layer sequence in the sequence top layer, the bottom layer excitation corresponding to the generated top layer excitation is determined, the bottom layer sequence corresponding to the bottom layer excitation is further determined, and the bottom layer excitation corresponding to the certain bus is generated by using the bottom layer sequence in the sequence bottom layer.
In the technical scheme provided by the application, the excitation top layer defines top layer excitation corresponding to different values of variables of the same enumeration type, and the different values of the variable correspond to different bottom layer excitations, the excitation bottom layer defines bottom layer excitations corresponding to the data formats of different buses respectively, the sequence top layer comprises top layer sequences corresponding to the different top layer excitations respectively, the sequence bottom layer comprises bottom layer sequences corresponding to the different bottom layer excitations respectively, therefore, when the corresponding excitation of a certain bus needs to be generated, after the top layer excitation is generated by using the corresponding top layer sequence, the bottom layer excitation is generated by using the bottom layer sequence of the corresponding bottom layer excitation of the top layer excitation, therefore, the generation of corresponding excitation of the bus is realized, and the application integrates different bus types into the same platform through hierarchical design, the excitation corresponding to the bus protocols of different buses can be generated, so that the reusability of the platform is greatly improved.
The hierarchical verification platform provided by the embodiment of the invention can further comprise a driving layer and a total sequence layer;
a total sequence layer to: acquiring bottom layer excitation generated by a sequence bottom layer, sending the acquired bottom layer excitation to a driving layer, and caching a backup of the acquired bottom layer excitation;
a drive layer to: and if the bottom layer excitation sent by the total sequence layer is successfully received, sending the received bottom layer excitation to the device under test, otherwise, indicating the total sequence layer to resend the cached backup of the bottom layer excitation to the drive layer.
The Driver acquires a required bottom layer excitation through interaction with a total sequence layer (sequence), specifically, the Driver can acquire a top layer sequence through get _ next _ item (), generate a corresponding top layer excitation by using the top layer sequence, judge the bottom layer excitation represented by a value of a variable of an enumeration type in the generated top layer excitation, initialize a bottom layer sequence corresponding to the bottom layer excitation, generate a corresponding bottom layer excitation by using the bottom layer sequence, and then send the bottom layer excitation to a DUT (device under test) by calling a driving task of the bottom layer sequence. The driving tasks and the bottom layer stimuli also have corresponding relations, and different driving tasks can drive different bottom layer stimuli to the interface and send the stimuli to the DUT. The driver layer is provided with a member variable seq _ item _ port, which is a port for connecting a driver and a sequence, the driver needs to send data from the port if the driver wants to send the data, the sequence needs to send the data to the driver through the port if the sequence has the data to be sent to the driver, and the get _ next _ item method of the port is called when the sequence requests the data from the port, specifically, the get _ next _ item (req) of the port.
It should be noted that, in order to improve reliability, the total sequence layer may also store a backup of the bottom layer stimulus in its cache while sending the bottom layer stimulus to the driver layer, so that when the driver layer does not successfully receive the bottom layer stimulus, the backup is sent to the driver layer again, and when the backup is sent to the driver layer again, a backup is also simultaneously retained, and so on.
In addition, when determining the value of a variable of an enumeration type included in the top-level stimulus, the value may be determined by the value of amba _ op in the top-level stimulus, and specifically, a statement for obtaining the top-level stimulus may be as follows:
Typedef enum{apb，ahb，axi，asb}amba_op_e；
class ahb_transacation extends uvm_sequence_item；
rand amba_op_e amba_op；
as can be seen, each time a top-level stimulus is generated, there is a random amba _ op value, with 0 representing the apb bus, 1 representing the ahb bus, 2 representing the axi bus, and 3 representing the asb bus.
In the hierarchical verification platform provided by the embodiment of the present invention, the driver layer may be further configured to: if the bottom layer excitation sent by the total sequence layer is successfully received, returning the information of successful reception to the total sequence layer;
the total sequence layer may also be used to: and if the information of successful receiving sent by the driving layer is received, deleting the cached backup of the bottom layer excitation.
In order to avoid the waste of cache resources in the total sequence layer, after the driver layer successfully receives the bottom layer excitation sent by the total sequence layer, the driver layer can return the information of successful reception to the total sequence layer, so that the total sequence layer deletes the cached corresponding backup after receiving the information.
The hierarchical verification platform provided by the embodiment of the invention can further comprise a monitoring layer, wherein the monitoring layer is used for: and counting the coverage rate obtained by the equipment in the test by utilizing the received bottom layer excitation, and when the coverage rate does not reach a coverage rate threshold value, indicating the equipment in the test to carry out random test until the coverage rate obtained by the equipment in the test reaching the coverage rate threshold value.
The monitoring layer can count the coverage rate, the automatic test of the platform is realized by using the script, the monitoring layer automatically acquires the coverage rate after the automatic test, if the coverage rate reaches a coverage rate threshold set according to actual needs, the test is determined to be finished, otherwise, the random test is instructed, and whether the coverage rate obtained after the test reaches the coverage rate threshold is monitored until the coverage rate reaches the coverage rate threshold, so that the automatic test is realized by the mode, and the test coverage rate is ensured to reach the standard. Specifically, after the coverage rate is collected and output to the text, the value of the coverage rate in the text is read by using the script, and then the corresponding control operation is realized.
In the hierarchical verification platform provided in the embodiment of the present invention, the monitoring layer may be further configured to: if the times of the random test of the equipment in the test reaches the time threshold and the coverage rate of the equipment in the test, which is obtained by realizing the test, does not reach the coverage rate threshold, outputting corresponding alarm information; and for: and if the times of the random test of the equipment in the test does not reach the time threshold value and the coverage rate of the equipment in the test for realizing the test reaches the coverage rate threshold value, outputting corresponding test completion information.
In order to facilitate the workers to know the random test condition and avoid resource waste caused by ceaselessly carrying out random test when the test is abnormal, corresponding information is output when the random test times reach the time threshold set according to actual needs and the coverage rate does not reach the coverage rate threshold, and the random test times do not reach the time threshold and the coverage rate reaches the coverage rate threshold, so that the workers can conveniently carry out corresponding work.
According to the hierarchical verification platform provided by the embodiment of the invention, the hierarchical verification platform can be built based on UVM, and the driving layer and the total sequence layer are both packaged in the env layer of the hierarchical verification platform.
Because the port of the tlm transaction level cannot be used in the platform due to different bottom layer excitation transmitted by the bottom layer sequence, uvm _ config _ db:: get and uvm _ config _ db:: set are used for data transmission between modules (a driving layer, a monitoring layer and the like); in order to further improve the interaction efficiency, the method and the device for packaging the network data cancel the packaging of the agent, and directly package the driver and the sequence in the env layer.
It should be noted that, when a driver wants to drive a transaction, it applies for a transaction to the sequence, and sends the transaction to the device under test after applying for the transaction, specifically, it can be implemented by the following statements:
class ahb_transacation extends uvm_sequence_item；
rand bit reset；
rand transfer_t trans_type[]；
rand bit[31:0]address[]；
rand size_t trans_size；
rand burst_t burst_mode；
rand rw_t read_write；
rand bit[31:0]write_data[]。
when defining the underlying stimulus, the method can also create more subdivided underlying stimuli by combining the functional points to be verified of the tested project, specify different constraints and generate different data frames or packets. Specifically, the upper and lower limits of the address can be constrained according to the division of the memory address, the transmitted data can also be constrained (according to what data is required by a specific module), and check bits can also be added as constraints; for example, when the upper and lower limits of the restricted address are used, a project divides each module into different address spaces, and addresses in the address space range can be accessed to the corresponding module. Where the statements specifying the corresponding constraints may be as follows:
the embodiment of the invention also provides a hierarchical verification method, which comprises the following steps:
s11: generating a corresponding top-level stimulus using the top-level sequence; wherein, different top-level sequences correspond to different top-level excitations, and the different top-level excitations correspond to different values of a variable of the same enumeration type, and the different values of the variable correspond to different bottom-level excitations;
s12: determining a bottom layer excitation corresponding to the generated top layer excitation, and generating the bottom layer excitation by using a bottom layer sequence corresponding to the bottom layer excitation; wherein different underlying sequences correspond to different underlying stimuli and the different underlying stimuli have different data formats corresponding to different buses.
The embodiment of the invention also provides a hierarchical verification device, which comprises:
a memory for storing a computer program;
a processor for implementing the steps of the above hierarchical verification method when executing the computer program.
Embodiments of the present invention further provide a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, may implement the steps of the above hierarchical verification method.
Parts of the technical solutions provided in the embodiments of the present invention that are consistent with the implementation principles of the corresponding technical solutions in the prior art are not described in detail, so as to avoid redundant description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A hierarchical verification platform is characterized by comprising an excitation top layer, an excitation bottom layer, a sequence top layer, a sequence bottom layer, a driving layer and a total sequence layer; wherein:
the excitation top layer is used for: defining top-level excitations, wherein each top-level excitation corresponds to different values of a variable of the same enumeration type, and the different values of the variable correspond to different bottom-level excitations;
the excitation substrate is used for: defining underlying stimuli, each of the underlying stimuli having a different data format, the different data formats corresponding to different buses;
the sequence top layer is used for: storing top layer sequences respectively corresponding to different top layer excitations, and generating corresponding top layer excitations by utilizing the top layer sequences;
the sequence bottom layer is used for: storing bottom layer sequences respectively corresponding to different bottom layer excitations, and generating the bottom layer excitations by utilizing the corresponding bottom layer sequences after determining the bottom layer excitations corresponding to the top layer excitations generated by the top layer of the sequences;
the total sequence layer is used for: acquiring bottom layer excitation generated by the sequence bottom layer, sending the acquired bottom layer excitation to the driving layer, and caching backup of the acquired bottom layer excitation; the total sequence layer is further to: if receiving the information of successful receiving sent by the driving layer, deleting the cached backup of the bottom layer excitation;
the driving layer is used for: if the bottom layer excitation sent by the total sequence layer is successfully received, sending the received bottom layer excitation to the device under test, otherwise, indicating the total sequence layer to resend the cached backup of the bottom layer excitation to the driving layer; the drive layer is further configured to: and if the bottom layer excitation sent by the total sequence layer is successfully received, returning the information of successful reception to the total sequence layer.
2. The platform of claim 1, further comprising a monitoring layer to: and counting the coverage rate obtained by the equipment under test by utilizing the received bottom layer excitation to realize the test, and indicating the equipment under test to carry out random test when the coverage rate does not reach the coverage rate threshold value until the coverage rate obtained by the equipment under test to realize the test reaches the coverage rate threshold value.
3. The platform of claim 2, wherein the monitoring layer is further to: and if the times of the random test of the equipment under test reach a time threshold value and the coverage rate of the equipment under test, which is obtained by realizing the test, does not reach the coverage rate threshold value, outputting corresponding alarm information.
4. The platform of claim 3, wherein the monitor layer is further to: and if the times of the random test of the equipment in the test does not reach the time threshold value and the coverage rate of the equipment in the test for realizing the test reaches the coverage rate threshold value, outputting corresponding test completion information.
5. The platform of claim 4, wherein the hierarchical verification platform is built based on UVM, and the driver layer and the overall sequence layer are both encapsulated in an env layer of the hierarchical verification platform.
6. A hierarchical verification method, comprising:
generating a corresponding top-level stimulus using the top-level sequence; wherein, different top-level sequences correspond to different top-level excitations, and the different top-level excitations correspond to different values of a variable of the same enumeration type, and the different values of the variable correspond to different bottom-level excitations;
determining a bottom layer excitation corresponding to the generated top layer excitation, and generating the bottom layer excitation by using a bottom layer sequence corresponding to the bottom layer excitation; wherein different underlying sequences correspond to different underlying stimuli, and the different underlying stimuli have different data formats, the different data formats corresponding to different buses;
sending the obtained bottom layer excitation generated by the sequence bottom layer to a driving layer by using a total sequence layer, and caching the backup of the obtained bottom layer excitation;
if the driving layer successfully receives the bottom layer excitation sent by the total sequence layer, the driving layer sends the bottom layer excitation to the device under test, and returns the information of successful reception to the total sequence layer; otherwise, instructing the total sequence layer to resend the cached backup of the bottom layer excitation to the driving layer;
and if the total sequence layer receives the information of successful receiving sent by the driving layer, deleting the cached backup of the bottom layer excitation.
7. A hierarchical authentication apparatus, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the hierarchical verification method as claimed in claim 6 when executing the computer program.
8. A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, carries out the steps of the hierarchical verification method as set forth in claim 6.
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