CN111859831A - Chip verification method and system, and storage medium - Google Patents

Abstract

The embodiment of the present application discloses a chip verification method and system, and a storage medium. The method includes: in response to request information from a chip, generating a request data packet according to the request information; buffering the request data packet in a first storage area; By executing the test case, the request data packet is obtained from the first storage area, and the second storage area is accessed via the preset access interface, and the response data packet corresponding to the request data packet is obtained from the second storage area; wherein, the preset access interface is global Interface; send the response data packet to the chip to verify the data processing capability of the chip.

Description

Chip verification method and system, and storage medium

technical field

The invention relates to the technical field of chip testing, in particular to a chip verification method and system, and a storage medium.

Background technique

With the rapid development of integrated circuits and the increase in chip scale, the verification work in chip design has become more difficult, and has become the most expensive work in the process, accounting for an increasing proportion of the entire design cycle. The workload of verification has accounted for 70% to 80% of the research and development of the entire integrated circuit (System-on-a-Chip, SOC). Therefore, how to effectively perform chip test verification has become critical.

At present, in the field of artificial intelligence technology, artificial intelligence chips based on Convolutional Neural Networks (CNN) mainly perform CNN operations through the artificial intelligence core module (AI Core) to achieve artificial intelligence acceleration. Specifically, the artificial intelligence core module needs to actively transfer data such as features, weights, and offsets from the out-of-core storage unit. Based on such an artificial intelligence core module design, verifiers often use a passive transaction unit to be attached to the active interface of the artificial intelligence module to verify the artificial intelligence chip, and the two work together to verify each other.

However, the verification process of the existing chip verification method is complicated in operation, and has low configurability and reusability, which makes it difficult to achieve efficient chip verification.

SUMMARY OF THE INVENTION

The embodiments of the present application provide a chip verification method and system, and a storage medium, which not only have simple operation in the verification process, but also have high reusability and configurability, further realizing efficient verification of chips.

The technical solutions of the embodiments of the present application are implemented as follows:

In a first aspect, an embodiment of the present application provides a chip verification method, the method comprising:

In response to the request information from the chip, a request data packet is generated according to the request information;

caching the request data packet to the first storage area;

By executing the test case, the request data packet is obtained from the first storage area, and the second storage area is accessed via a preset access interface, and the response data packet corresponding to the request data packet is obtained from the second storage area; Wherein, the preset access interface is a global interface;

The response data packet is sent to the chip to verify the data processing capability of the chip.

In a second aspect, an embodiment of the present application provides a chip verification system, wherein the chip verification system is provided with a monitoring module, a service transmission channel, a driver module, and a response module,

The monitoring module is configured to, after receiving the request information sent by the chip, in response to the request information, generate a request data packet according to the request information, and send the request data packet to the service transmission channel;

the service transmission channel, for buffering the request data packet to the first storage area after receiving the request data packet;

The response module is configured to read the request data packet from the first storage area by executing a test case, and access the second storage area via a preset access interface, and obtain the request from the second storage area The response data packet corresponding to the data packet; wherein, the preset access interface is a global interface;

The service transmission channel is further configured to send the response data packet to the drive module after receiving the response data packet;

The driving module is configured to send the response data packet to the chip after receiving the response data packet, so as to verify the data processing capability of the chip.

In a third aspect, an embodiment of the present application provides a chip verification system, the chip verification system includes a generating unit, a storage unit, a reading unit, an obtaining unit, and a sending unit,

The generating unit is configured to generate a request data packet according to the request information in response to the request information from the chip;

the storage unit, configured to cache the request data packet to the first storage area;

The obtaining unit is configured to obtain the request data packet from the first storage area by executing a test case; and access the second storage area via a preset access interface, and obtain the request data from the second storage area The response data packet corresponding to the packet; wherein, the preset access interface is a global interface;

The sending unit is configured to send the response data packet to the chip to verify the data processing capability of the chip.

Embodiments of the present application provide a chip verification method and system, and a storage medium. The chip verification system, in response to request information from a chip, generates a request data packet according to the request information; caches the request data packet in a first storage area; In the test case, the request data packet is obtained from the first storage area, and the second storage area is accessed via a preset access interface, and the response data packet corresponding to the request data packet is obtained from the second storage area; wherein, the preset access interface is a global interface; Send the response data packet to the chip to verify the data processing capability of the chip.

Specifically, in the embodiment of the present application, the chip verification system can process the request information sent by the chip and the response information returned to the chip through the monitoring module and the driving module respectively; at the same time, the chip verification system can also execute the test case from the first The request information is obtained from the storage area, and the response information corresponding to the request information is obtained from the second storage area via a preset access interface; wherein, the preset access interface is a global interface to realize data update and sharing among verification components. It can be seen that in the chip verification method and system proposed in this application, different modules are independent of each other to perform different verification functions, so that the chip verification system is highly reusable; at the same time, the request information and The interaction process of the response information can realize the access to the second storage area through the global access interface to update the data in the second storage area, which has high configurability and further realizes the efficient verification of the chip.

Description of drawings

Fig. 1 is the composition frame schematic diagram of UVM verification platform in the related art;

2 is a schematic diagram of the composition structure of a passive transaction unit in the related art;

FIG. 3 is a schematic diagram 1 of the implementation flow of the chip verification method proposed by the present application;

4 is a schematic diagram of the composition and structure of a chip verification system implemented based on the UVM verification methodology proposed by the application;

FIG. 5 is a second implementation flowchart of the chip verification method proposed by the present application;

FIG. 6 is a schematic diagram 1 of the composition structure of the chip verification system proposed by the present application;

FIG. 7 is a second schematic diagram of the composition and structure of the chip verification system proposed by the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It should be understood that the specific embodiments described herein are only used to explain the related application, but not to limit the application. In addition, it should be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings.

Before further describing the embodiments of the present invention in detail, the terms and terms involved in the embodiments of the present invention are described. The terms and terms involved in the embodiments of the present invention are applicable to the following explanations.

1) Design Under Test (DUT): In the modern integrated circuit (Integrated CircuitChip, IC) design process, when the designer completes the Register Transfer Level (RTL) code according to the design specification, the verifier starts. Validate these codes, often referred to as the module under test, or DUT.

2) Universal Verification Methodology (UVM): It is a verification platform development framework with the SystemVerilog class library as the main body, and its reusable components can be used to build a functional verification environment with a standardized hierarchy and interface. Find bugs in the DUT by placing the DUT into a built UVM verification platform.

Figure 1 is a schematic diagram of the composition framework of the UVM verification platform in the related art. As shown in Figure 1, the UVM verification platform includes the following basic components, such as: (11) the module to be tested DUT; (12) transaction unit agent: it is a container , encapsulate the driver driver, monitor monitor and sequencer sequencer in it, the transaction unit agent can instantiate the driver driver, monitor monitor and sequencer sequencer; wherein, the transaction unit agent includes In_Agent active transaction unit (121) and Out_Agent Passive transaction unit (122); (13) Monitor monitor: monitors the input and output signals of the DUT of the module to be tested, and converts the collected DUT port data into transaction-level information transaction, which is handed over to the subsequent reference model reference model and The scoreboard component is processed; (14) Driver: used to apply various incentives to the DUT of the module under test, and is responsible for driving transaction-level information transactions, which itself does not generate transaction-level information transactions; (15) Sequencer sequencer: It is used to detect whether there is a request to send transaction-level information transaction in the arbitration queue, and to detect whether the driver applies for transaction-level information transaction; (16) reference model reference model: simulate the functional behavior of the DUT of the module to be tested, and complete the DUT of the module to be tested. The same function, the expected result is obtained; and its output is received by the scoreboard scoreboard, which is used to compare with the actual output of the DUT of the module to be tested; (17) scoreboard scoreboard: According to the output of the DUT of the module to be tested, the output of the DUT of the module to be tested is judged. Whether the behavior is as expected, the implementation compares the output of the DUT with the output of the reference model.

With the rapid development of integrated circuits and the increase in chip scale, the verification work in chip design has become more difficult, and has become the most expensive work in the process, accounting for an increasing proportion of the entire design cycle. The workload of verification has accounted for 70% to 80% of the research and development of the entire integrated circuit (System-on-a-Chip, SOC). Therefore, how to effectively perform chip test verification has become critical.

At present, in the field of artificial intelligence technology, artificial intelligence chips based on CNN and other networks mainly perform CNN operations through the artificial intelligence core module (AI Core), thereby realizing artificial intelligence acceleration. Specifically, since the artificial intelligence core module needs to actively transfer data such as features, weights, and offsets from the out-of-core storage unit, based on the design of such an artificial intelligence core module, verifiers often use a passive transaction unit to plug in the artificial intelligence module. The verification process of the artificial intelligence chip is carried out by means of the active interface, and the two work together to verify each other.

FIG. 2 is a schematic diagram of the composition structure of the passive transaction unit in the related art. As shown in FIG. 2, when the function verification of the artificial intelligence core module is performed, the passive transaction unit agent (21) only passively receives the request and feeds it back to the waiting Therefore, in the passive transaction unit (21), only the monitor monitor (22) receives the request from the virtual interface (23), and then the monitor monitor (22) Instantiate the storage module (24); Concretely, the monitor monitor (22) updates or reads the data of the storage module (24) according to the read-write request received, and then generates the response data, and directly sends the response data to the virtual The interface (23) is used to drive the module under test DUT (21).

However, since an efficient verification scheme requires a high degree of reusability and configurability, the verification system based on Figure 2 has the following drawbacks: First, a storage module is instantiated in the monitor, and according to the storage module The data-driven response data is sent to the DUT of the module under test, and it also has the task of the driver driver, so that when the passive transaction unit is integrated and reused by the upper-level verification environment, only the monitoring function can be reused, and the function of driving the response cannot be reused, which leads to the verification environment. Less reusability. Secondly, the storage modules in the passive transaction unit often need to be configured in the top-level environment. Since the monitor is not directly called by the upper-level environment, it is difficult for the upper-level environment to operate the storage modules in it. Further, as can be seen from Figure 2, the interaction between the monitor monitor and the storage module is all in the monitor monitor, which leads to the inability of the upper-layer environment and test cases to control it (for example, changing the data in the storage module, or according to the test case scenario. Add response delay, etc.); it can be seen that the existing chip verification method has complicated verification process, low configurability and low reusability, and it is difficult to achieve efficient chip verification.

In order to solve the problems existing in the existing chip verification mechanism, the embodiments of the present application provide a chip verification method and system, and a storage medium. Specifically, in the chip verification system proposed in this application, the chip verification system can process the request information sent by the chip and the response information returned to the chip through the monitoring module and the driving module respectively; at the same time, the chip verification system can also be executed by executing the test case. The request information is obtained from the first storage area, and the response information corresponding to the request information is obtained from the second storage area via a preset access interface; wherein, the preset access interface is a global interface to realize data update and sharing between verification components . It can be seen that in the chip verification method and system proposed in this application, different modules are independent of each other to perform different verification functions, so that the chip verification system is highly reusable; at the same time, the request information and The interaction process of the response information can realize the access to the second storage area through the global access interface to update the data in the second storage area, which has high configurability and further realizes the efficient verification of the chip.

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application.

Optionally, in a preferred embodiment of the present application, the chip verification system can be implemented based on the UVM verification methodology, and the verification engineer can use the predefined classes as a starting point based on the schematic diagram of the composition and architecture of the UVM verification platform shown in FIG. 1 . A chip verification system with a standard structure is established. The driver module driver, monitoring module monitor and other components described below can be provided by the existing UVM verification platform. Verifiers can construct the chip verification system of the present application by instantiating different verification components.

An embodiment of the present application provides a chip verification method. FIG. 3 is a schematic diagram 1 of the implementation flow of the chip verification method proposed by the present application. As shown in FIG. 3 , in the embodiment of the present application, the chip verification system executes the chip verification method. The following steps can be included:

Step 101: In response to the request information from the chip, generate a request data packet according to the request information.

In the embodiment of the present application, the chip verification system may first receive the request information sent by the chip to be tested, and in response to the request information, further generate a request data packet corresponding to the request information.

It should be noted that, in the embodiments of the present application, the chip verification system may be constituted by at least one device. Optionally, the at least one device may be a physical server, a virtual server (such as a cloud server), a tablet computer, a personal computer (Personal Computer, PC), a notebook computer, and other devices with computing functions and storage functions. There is no specific limitation on the device to which the chip verification method is applied.

Further, in the specific implementation process, the creation of the chip verification system in the embodiment of the present application may be completed based on at least one device, that is, the chip verification method may be executed by one device alone, or may be performed by multiple devices. equipment cooperates.

It is understandable that in the process of completing the corresponding RTL code according to the design specification of the chip, due to the understanding deviation or negligence of the verifier, the obtained RTL code may not reflect all the characteristics of the chip. Therefore, the verifier often The basic functions of the chip are tested by building a corresponding verification environment.

Optionally, in the embodiment of the present application, the chip may be a core module with data handling capability, for example, an artificial intelligence chip based on a network such as CNN; thus, the data handling capability of the chip can be verified through a chip verification system.

Specifically, in the embodiment of the present application, the data handling capability of the chip includes the capability of reading data from the out-of-core storage unit and the capability of writing data to the out-of-core storage unit, that is, the chip obtained by the chip verification system. request information, including read data requests and write data requests. When the acquired request information is a data read request, it indicates the data read capability of the verification chip; when the acquired request information is a write data request, it indicates the verification chip's data write capability.

It should be noted that, in the embodiment of the present application, after the chip verification system receives the request information from the chip, since the data in the chip verification system is transmitted by transaction-level information, the chip verification system needs to send the request according to the timing protocol. The timing information corresponding to the information is converted into transaction-level information. Specifically, after receiving the request information from the chip, the chip verification system performs transaction-level information encapsulation processing on the request information in response to the request information, thereby generating a request data packet corresponding to the request information.

Exemplarily, in the embodiment of the present application, in the chip verification system implemented based on the UVM verification methodology, the chip verification system can instantiate the monitor monitor component, and the monitor monitor receives the data from the chip from the virtual interface (interface) through the monitor monitor. request information, and convert the timing information corresponding to the request information into transaction-level information, so as to obtain the request data packet corresponding to the request information.

Further, in the embodiment of the present application, after the chip verification system receives the request information sent by the chip, and in response to the request information, generates a request data packet corresponding to the request information, the chip verification system can further perform the request data packet. to store.

Step 102: Cache the request data packet in the first storage area.

In the embodiment of the present application, after the chip verification system generates a request data packet corresponding to the request information in response to the request information from the chip, the chip verification system may further cache the request data packet in the first storage area.

It should be noted that, in the embodiments of the present application, since the chip can send request information to realize the control of the out-of-core storage unit, such as different random access memory (Random Access Memory, RAM) or read-only memory (Read- Only Memory, ROM) access, and then perform data read and write operations. However, due to the limited bandwidth of the out-of-core storage unit, the request data packets of the chip that are continuously sent cannot be directly sent to the out-of-core storage unit. Therefore, the chip verification system designs a buffer space to cache the request data packets first. When certain conditions are met, the request packet is read from the cache space.

Specifically, the cache processing of the request data packet in this application refers to the storage operation performed according to the principle of "first in, first out". That is to say, the chip verification system caches the request data packets in the first storage area in the order in which the request data packets are sent. The storage area reads the request packet.

Exemplarily, in the embodiments of the present application, in the chip verification system implemented based on the UVM verification methodology, the chip verification system can instantiate the sequencer sequencer component, the sequencer sequencer is used as a data transmission channel, which can be used as a data transmission channel. The TLM1 transmits the unit layer model interface to receive the request data packets sent by the monitor monitor, and further buffers the request data packets into the built-in First Input First Output (FIFO) storage space, and then waits for the data packets to be read.

Further, in the embodiment of the present application, after the chip verification system caches the request data packet in the first storage area, the chip verification system can further obtain the request data packet from the first storage area by executing the test case, and perform response processing. .

Step 103: Obtain the request data packet from the first storage area by executing the test case, and access the second storage area via the preset access interface, and obtain the response data packet corresponding to the request data packet from the second storage area; wherein, the preset access The interface is a global interface.

In the embodiment of the present application, after the chip verification system caches the request data packet in the first storage area, the chip verification system can obtain the request data packet from the first storage area by executing the test case, and access the request data packet through the preset access interface The second storage area further acquires the response data packet corresponding to the request data packet from the second storage area, wherein the preset access interface is a global interface.

It should be noted that, in the embodiment of the present application, the test case is a response test task with multiple predetermined condition parameters set for the request information of the chip. Optionally, the predetermined condition parameter may be a variety of preset response conditions set for the request information. Specifically, the preset response condition may be a periodic response to the request information; or a response to the request information under a specific condition.

Further, the chip verification system can implement the response processing to the request data packet buffered in the first storage area by executing the test case. Specifically, when the chip verification system executes the test case, it can determine whether the preset response condition in the test case is currently satisfied. If it is determined that the preset response condition is satisfied, the chip verification system can obtain the corresponding request data packet from the first storage area. , and obtain the response data packet corresponding to the request data packet from the second storage area.

Optionally, when the preset response condition in the test case is the periodic response request information, the chip verification system can periodically read the request data packet from the first storage area and respond; when the preset response condition in the test case is When responding to the request information under specific conditions, the chip verification system can also read the request data packet from the first storage area and respond when the specific conditions are met. Specifically, the chip verification system sequentially reads the request data packets from the first storage area according to the "first-in, first-out" principle, and responds sequentially.

It should be noted that, in the embodiments of the present application, the second storage area corresponds to an out-of-core storage unit that stores data, and the chip can perform read and write operations on data in the out-of-core storage unit by accessing the second storage area. .

Further, in the embodiment of the present application, the chip verification system can access the second storage area via the preset access interface, and then obtain the response data packet corresponding to the above-mentioned request data packet from the second storage area, wherein the response data packet contains the response information corresponding to the above request information. Specifically, the chip verification system can acquire response information in different ways according to different types of request information.

It should be noted that, in the embodiments of the present application, the preset access interface is a global interface. It can be understood that the global interface follows the principle of "defined in one place, available everywhere", that is, in the chip verification system, each All verification components can implement global access to the second storage area through a preset access interface. Optionally, the chip verification system can access the second storage area through a preset access interface when executing the test case, and the chip verification system can also access the second storage area through the preset access interface through the system upper environment or other verification components.

Specifically, when the chip verification system executes the verification process of the chip, the upper-layer environment may access the second storage area through the preset access interface, so as to realize the "backdoor" access of the out-of-core storage unit, so as to configure and update the data; It can also be that when the test case is executed, the second storage area is accessed through the preset access interface, so as to realize the "front door" access of the out-of-core storage unit, so as to carry out the configuration update of the data; The configuration and update of the data of the out-of-core storage unit, the updated data can be shared among all components.

Exemplarily, in the embodiments of the present application, in the chip verification system implemented based on the UVM verification methodology, the chip verification system can instantiate the response sequence sequence component, and by executing the test case, the response sequence sequence can be made to meet the pre-determined conditions. When the response condition is set, the request data packet cached in the built-in FIFO storage space can be read, and the second storage area can be accessed through the preset access interface in the way of “front door” access according to the request data packet, and the second storage area can be accessed from the second storage area. The response data packet corresponding to the request information is obtained in the area. During the chip verification process, if you need to update the configuration of the data in the second storage area, you can also access the second storage area through the preset access interface through the upper-layer environment in the way of "backdoor" access to configure the data. and update.

Further, in the embodiment of the present application, the chip verification system reads the request data packet from the first storage area by executing the test case, and accesses the second storage area via the preset access interface, and starts from the second storage area. After obtaining the response data packet corresponding to the request data packet in the system, the chip verification system can further send the response data packet to the chip, so as to realize the verification of the data processing capability of the chip.

Step 104: Send the response data packet to the chip to verify the data processing capability of the chip.

In the embodiment of the present application, after the chip verification system reads the request data packet from the first storage area by executing the test case, and obtains the response data packet corresponding to the request data packet from the second storage area, the chip verification system can The response data packet is sent to the chip, thereby realizing the verification of the data processing capability of the chip.

It should be noted that, in the embodiments of the present application, since the data in the chip verification system is transmitted by transaction-level information, when transmitting the response data packet and the chip, it is necessary to first transmit the response according to the timing protocol. The transaction-level information corresponding to the data packet is converted into timing information, and then the timing information corresponding to the request response is sent to the chip.

Further, by testing whether the chip sends the request information and whether the chip can receive the response information corresponding to the request information, the verification of the data processing capability of the chip, that is, the capability of transferring data from the out-of-core storage unit, is realized.

Exemplarily, in the embodiment of the present application, in the chip verification system implemented based on the UVM verification methodology, the response sequence sequence meets the preset response condition, accesses the second storage area via the preset access interface, and accesses the second storage area from the second storage area. After the response packet corresponding to the request packet is obtained in the area, the response packet can be sent to the service transmission channel sequencer first, and then the TLM1 transmission unit layer model of the channel service transmission channel passes the response packet to the driver driver, that is It is said that the response data packet needs to complete its transmission between the response sequence and the driver through the service transmission channel. Further, after receiving the response data packet, the driver driver converts the transaction-level information corresponding to the response data packet into timing information, and The timing information is transmitted to the chip by calling the virtual interface, thereby realizing the verification of the data processing capability of the chip.

Exemplarily, FIG. 4 is a schematic diagram of the composition of the chip verification system (30) based on the UVM verification methodology proposed by the embodiment of the application, as shown in FIG. 4, specifically, the chip verification system passes the monitoring module monitor (31) The request information sent from the chip DUT (40) is received from the virtual interface (32), and the request data packet corresponding to the request information is generated, and then the request data packet is transmitted to the service transmission channel sequencer through the TLM2 transmission unit layer model (33). (34); After receiving the request data packet transmitted by the monitoring module (31), the service transmission channel (34) buffers the request data packet in the built-in FIFO storage space, and waits for the response module response sequence (35) to take it; Further, by executing the test case, the response module (35) starts to obtain the request data packet transmitted by the monitoring module (32) from the FIFO storage space of the service transmission channel (34) through the transmission unit (36), and accesses the second storage area (37), to obtain the request response from the second storage area (37), thereby further sending the response data packet to the driver module driver (39) through the TLM1 transmission unit layer model (38) of the service transmission channel, and through the virtual interface (32) Sent to chip DUT (40) in response to a request from chip DUT (40).

The monitoring module (31), the service transmission channel (34) and the driver (39) are all encapsulated in the passive transaction unit (310), and the transmission unit (36) and the second storage area (37) are encapsulated in the response sequence module (35). ); at the same time, the upper-layer environment can also access the second storage area through a preset access interface in the passive transaction unit (310), so as to implement configuration update of the data in the out-of-core storage unit. That is to say, in the chip verification system, the upper-layer environment can access the second storage area via the preset access interface, and perform data update processing on the second storage area; it is also possible to access the second storage area through the preset access interface when executing the test case The data update processing of the second storage area is implemented through the read and write operations on the data in the second storage area.

The embodiment of the present application provides a chip verification method. The chip verification system, in response to request information from the chip, generates a request data packet according to the request information; caches the request data packet in a first storage area; The storage area obtains the request data packet, and accesses the second storage area via the preset access interface, and obtains the response data packet corresponding to the request data packet from the second storage area; wherein, the preset access interface is a global interface; The response data packet is sent to chip to verify the data processing capability of the chip. Specifically, in the embodiment of the present application, the chip verification system can process the request information sent by the chip and the response information returned to the chip through the monitoring module and the driving module respectively; at the same time, the chip verification system can also execute the test case from the first The request information is obtained from the storage area, and the response information corresponding to the request information is obtained from the second storage area via a preset access interface; wherein, the preset access interface is a global interface to realize data update and sharing among verification components. It can be seen that in the chip verification method and system proposed in this application, different modules are independent of each other to perform different verification functions, so that the chip verification system is highly reusable; at the same time, the request information and The interaction process of the response information can realize the access to the second storage area through the global access interface to update the data in the second storage area, which has high configurability and further realizes the efficient verification of the chip.

Based on the above-mentioned embodiment, in another embodiment of the present application, FIG. 5 is a second schematic diagram of the implementation flow of the chip verification method proposed by the present application. As shown in FIG. 5 , in the embodiment of the present application, the chip verification system is pre- Assuming that the access interface accesses the second storage area, the method for obtaining the response data packet corresponding to the request data packet from the second storage area may include the following steps:

Step 201: Parse the request data packet to obtain request information.

In the embodiment of the present application, after the chip verification system reads the request data packet from the first storage area by executing the test case, the chip verification system may first parse the request data packet, and obtain corresponding request information therefrom. .

It should be noted that, in the embodiments of the present application, the data in the chip verification system is transmitted by transaction-level information, that is, the timing information is packaged and processed according to the timing protocol, and converted into transaction-level information in the chip verification system. Therefore, when the chip verification system performs response processing according to the request data packet, it needs to decapsulate the request data packet, and then parse the corresponding request information from the request data packet.

Exemplarily, in the chip verification system implemented based on the UVM verification methodology, after the response sequence sequence obtains the request data packet from the first storage area, the request data packet can be parsed and processed to obtain the corresponding data packet of the request data packet. Request information.

Further, in the embodiment of the present application, after obtaining the request data packet through parsing processing of the request data packet, the chip verification system may further obtain the response information corresponding to the request information from the second storage area.

Step 202: Access the second storage area via a preset access interface, and acquire response information corresponding to the request information from the second storage area.

In the embodiment of the present application, after obtaining the request data packet through the parsing process of the request data packet, the chip verification system can further access the second storage area through the preset access interface, and then obtain the request information from the second storage area corresponding response information.

It can be understood that, in the embodiment of the present application, the data handling capability of the chip includes the capability of reading data from the out-of-core storage unit and the capability of writing data to the out-of-core storage unit, that is, the chip verification system obtains the data. The request information to the chip, including read data request and write data request.

Specifically, when the acquired request information is a read data request, the chip verification system can access the second storage area via the preset access interface, and read the data from the second storage area according to the read data request and the read data request corresponding first target data, thereby determining the first target data as response information corresponding to the read data request.

Specifically, when the acquired request information is a write data request, wherein the write data request carries the second target data, the chip verification system can access the second storage area via the preset access interface, and according to the write data request, and write the second target data carried in the write data request into the second storage area. Further, during the write operation, the chip verification system will generate feedback information to indicate the completion result of the write operation through the feedback information, and the chip verification system can use the feedback information as the response information corresponding to the write data request.

Further, in the embodiment of the present application, when the second target data carried by the write data request is written into the second storage area, the data in the out-of-core storage unit corresponding to the second storage area is configured and updated, And the updated data can be shared among all components.

Exemplarily, in the embodiment of the present application, in the chip verification system based on the UVM verification methodology, the response sequence sequence not only reads the request data packet from the built-in FIFO storage space of the service transmission channel, but also parses out the request information. , and when accessing the second storage area to obtain response information, corresponding data read/write operations are performed according to different types of request information, so as to obtain response information corresponding to the request information.

Further, in the embodiment of the present application, after the chip verification system acquires the response information corresponding to the request information, the chip verification system may further generate a response data packet corresponding to the response information.

Step 203: Generate a response data packet according to the response information.

It should be noted that, in the embodiment of the present application, after the chip verification system obtains the response information corresponding to the request information of the chip, since the data in the chip verification system is transmitted by transaction-level information, the chip verification system needs to The timing information corresponding to the response information is converted into transaction-level information according to the timing protocol. Specifically, after acquiring the response information of the chip, the chip verification system performs encapsulation processing of transaction-level information on the response information, thereby generating a response data packet corresponding to the response information.

The embodiment of the present application provides a chip verification method. In the chip verification system, by executing the test case, the response module can not only read and parse the request data packet in the first storage area, but also can access via the global access interface The second storage area performs response processing in different ways according to the type of the obtained request information. The verification process is simple and highly reusable and configurable, further realizing the efficient verification of the chip.

In another embodiment of the present application, based on the schematic diagram of the composition and structure of the chip verification system shown in FIG. 4 , FIG. 6 is a compositional structure diagram 1 of the chip verification system proposed by the present application. As shown in FIG. 6 , the embodiment of the present application The proposed chip verification system 30 is provided with a monitoring module 31, a service transmission channel 34, a driving module 39, and a response module 35, wherein the monitoring module 31, the service transmission channel 34 and the driving module 39 are packaged with a passive transaction unit 310,

The monitoring module 31 is configured to, after receiving the request information sent by the chip, in response to the request information, generate a request data packet according to the request information, and send the request data packet to the service transmission channel;

The service transmission channel 34 is used for buffering the request data packet to the first storage area after receiving the request data packet;

The response module 35 is configured to obtain the request data packet from the first storage area by executing the test case, and access the second storage area via the preset access interface, and obtain the response data packet corresponding to the request data packet from the second storage area; The preset access interface is a global interface;

The service transmission channel 34 is also used to send the response data packet to the driver module after receiving the response data packet;

The driving module 39 is configured to, after receiving the response data packet, send the response data packet to the chip to verify the data processing capability of the chip.

Further, in the embodiment of the present application, the response module 35 is specifically configured to parse the request data packet to obtain the request information; and to access the second storage area via a preset access interface, from the Acquire response information corresponding to the request information in the second storage area; and generate the response data packet according to the response information.

Further, in the embodiment of the present application, the response module 35 is further specifically configured to read the first target data corresponding to the read data request from the second storage area; Data is determined as the response information.

Further, in the embodiment of the present application, the response module 35 is further specifically configured to store the second target data carried by the write data request in the second storage area, and obtain feedback information; and The feedback information is determined as the response information.

Further, in the embodiment of the present application, the response module 35 is further specifically configured to acquire the request data packet from the first storage area if it is determined that a preset response condition is satisfied when the test case is executed.

It should be noted that, in the embodiment of the present application, the chip verification system does not centrally configure the two processes of receiving the request information of the chip and sending the response information to the chip in the monitoring module, and the monitoring module does not have the function of driving response; It is to perform the receiving of the request information and the sending of the reply information through the monitoring module and the driving module respectively.

Specifically, the chip verification system receives the request information of the chip through the monitoring module, and converts the timing information corresponding to the request information into transaction-level information, that is, generates a request data packet corresponding to the request information. The request packet is sent to the service transmission channel.

Specifically, the chip verification system receives the response data packet corresponding to the request data packet transmitted by the service transmission channel through the driver module, and converts the transaction-level information corresponding to the response data packet into timing information. Further, the chip verification system passes the driver module. The response information is sent to the chip to verify the data processing capability of the chip.

It can be seen that, in the embodiment of the present application, the chip verification system differentiates the functions of each component, so that each module independently performs different functions, thereby facilitating the reuse of each verification component in the upper-layer environment.

It should be noted that, in the embodiment of the present application, the chip verification system no longer places the process of reading the request information and obtaining the response information by interacting with the storage unit in the monitoring module in the passive transaction unit, but sets up an independent monitoring module. The passive transaction unit and response module in the passive transaction unit receive the request information and the business transmission channel cache request information through the monitoring module in the passive transaction unit, and respond to the request information through the response module, that is, by executing the test case, the interaction between the request information and the response information The process is placed in the response module, and each component is connected through configuration to realize the transfer of request information and response information between the passive transaction unit and the response module.

Specifically, the chip verification system first buffers the received request data packet sent by the monitoring module into the first storage area through the service transmission channel, and waits for the response module to take it. Then, by executing the test case, the response module obtains the request data packet from the first storage area in the service transmission channel, and accesses the out-of-core storage unit corresponding to the second storage area through the preset access interface, so as to obtain the request data packet from the second storage area according to the request data packet. The corresponding response data packets are obtained in the storage area, and then the response module returns the obtained response data packets to the service transmission channel.

Further, in the embodiment of the present application, the preset access interface is a global interface. It can be understood that the global interface follows the principle of "defined in one place, available everywhere", that is, in the chip verification system, each verification component Both can realize global access to the second storage area through a preset access interface. Optionally, the chip verification system can access the second storage area through a preset access interface when executing the test case, and the chip verification system can also access the second storage area through the preset access interface through the system upper environment or other verification components.

Specifically, when the chip verification system executes the verification process of the chip, the upper-layer environment may access the second storage area through the preset access interface, so as to realize the "backdoor" access of the out-of-core storage unit, so as to configure and update the data; It can also be that when the test case is executed, the second storage area is accessed through the preset access interface, so as to realize the "front door" access of the out-of-core storage unit, so as to carry out the configuration update of the data; Configuration and update of out-of-core storage unit data, and the updated data can be shared among all components.

It can be seen that, in the embodiment of the present application, the chip verification system places the interaction process of the request information and the response information in the response module by executing the test case, and can access the second storage address via the global interface, so that the second storage address can be accessed through the global interface. The data in the storage area is controlled, which improves the configurability of the chip verification system.

Optionally, in the chip verification system, the upper-layer environment can access the second storage area through a preset access interface in the passive transaction unit, so as to configure and update the data in the out-of-core storage unit; In the service transmission channel, the second storage area is accessed through a preset access interface, so as to implement configuration update of the data in the out-of-core storage unit.

The embodiment of the present application provides a chip verification system, the chip verification system can process the request information sent by the chip and the response information returned to the chip through the monitoring module and the driving module respectively; The request information is obtained from the first storage area, and the response information corresponding to the request information is obtained from the second storage area via a preset access interface; wherein, the preset access interface is a global interface to realize data update sharing among verification components. It can be seen that in the chip verification method and system proposed in this application, different modules are independent of each other to perform different verification functions, so that the chip verification system is highly reusable; at the same time, the request information and The interaction process of the response information can realize the global access to the second storage area through the preset access interface to update the data in the second storage area, and has a high degree of configurability, which further realizes the efficient verification of the chip.

Based on the above-mentioned embodiment, in another embodiment of the present application, FIG. 7 is a second schematic diagram of the composition and structure of the chip verification system proposed by the present application. As shown in FIG. 7 , the chip verification system 30 proposed by the embodiment of the present application may include generating unit 311 , storage unit 312 , obtaining unit 313 and sending unit 314 .

The generating unit 311 is configured to, in response to the request information from the chip, generate a request data packet according to the request information;

the storage unit 312, configured to cache the request data packet to the first storage area;

The obtaining unit 313 is configured to obtain the request data packet from the first storage area by executing a test case; and access the second storage area via a preset access interface, and obtain the request from the second storage area The response data packet corresponding to the data packet; wherein, the preset access interface is a global interface;

The sending unit 314 is configured to send the response data packet to the chip to verify the data processing capability of the chip.

Further, in the embodiment of the present application, the obtaining unit 313 is specifically configured to parse the request data packet to obtain the request information; and to access the second storage area via a preset access interface, from the Acquire response information corresponding to the request information in the second storage area; and generate the response data packet according to the response information.

Further, in the embodiment of the present application, the obtaining unit 313 is further specifically configured to read the first target data corresponding to the read data request from the second storage area; Data is determined as the response information.

Further, in the embodiment of the present application, the obtaining unit 313 is further specifically configured to store the second target data carried by the write data request in the second storage area, and obtain feedback information; and The feedback information is determined as the response information.

Further, in the embodiment of the present application, the obtaining unit 313 is further specifically configured to obtain from the first storage area if it is determined that the preset response condition in the test case is satisfied when the test case is executed the request packet.

The embodiments of the present application provide a chip verification system, wherein different modules in the chip verification system are independent of each other to perform different verification functions, so that the chip verification system has a high degree of reusability; at the same time, it is completed by executing test cases. The interaction process of the request information and the response information can realize the access to the second storage area through the global access interface to update the data in the second storage area, which is highly configurable and further realizes the efficient verification of the chip. .

An embodiment of the present application provides a computer-readable storage medium, on which a program is stored, and is applied to a chip verification system. The chip verification system is provided with a monitoring module, a service transmission channel, a driver module, and a response module, and the program is processed by a processor. When executed, the chip verification method as described above is implemented.

Specifically, a program instruction corresponding to a chip verification method in this embodiment may be stored on a storage medium such as an optical disk, a hard disk, a U disk, etc. When the program instruction corresponding to a chip verification method in the storage medium is stored in a storage medium When the electronic device reads or is executed, it includes the following steps:

In response to the request information from the chip, a request data packet is generated according to the request information;

caching the request data packet to the first storage area;

By executing the test case, the request data packet is obtained from the first storage area, and the second storage area is accessed via a preset access interface, and the response data packet corresponding to the request data packet is obtained from the second storage area; Wherein, the preset access interface is a global interface;

The response data packet is sent to the chip to verify the data processing capability of the chip.

As will be appreciated by those skilled in the art, the embodiments of the present application may be provided as a method, a system, or a computer program product. Accordingly, the application may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein, including but not limited to disk storage, optical storage, and the like.

The present application is described with reference to schematic flowcharts and/or block diagrams of implementations of methods, apparatuses (systems), and computer program products according to embodiments of the present application. It will be understood that each process and/or block in the schematic flowchart illustrations and/or block diagrams, and combinations of processes and/or blocks in the schematic flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to the processor of a general purpose computer, special purpose computer, embedded processor or other programmable data processing device to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing device produce Means for implementing the functions specified in a process or processes and/or a block or blocks in the block diagrams.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions An apparatus implements the functions specified in a flow or flows of the implementation flow diagram and/or a block or blocks of the block diagram.

These computer program instructions can also be loaded on a computer or other programmable data processing device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process such that The instructions provide steps for implementing the functions specified in the flow or blocks of the implementing flow diagram and/or the block or blocks of the block diagram.

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the protection scope of the present application.

Claims (12)

1. a chip verification method, is characterized in that, described method comprises: In response to the request information from the chip, a request data packet is generated according to the request information; caching the request data packet to the first storage area; By executing the test case, the request data packet is obtained from the first storage area, and the second storage area is accessed via a preset access interface, and the response data packet corresponding to the request data packet is obtained from the second storage area; Wherein, the preset access interface is a global interface; The response data packet is sent to the chip to verify the data processing capability of the chip. 2. The method according to claim 1, wherein the accessing the second storage area via a preset access interface, and acquiring the response data packet corresponding to the request data packet from the second storage area, comprises: Parsing the request data packet to obtain the request information; accessing the second storage area via a preset access interface, and acquiring response information corresponding to the request information from the second storage area; The response data packet is generated according to the response information. 3. The method according to claim 2, wherein, when the request information is a data read request, the acquiring response information corresponding to the request information from the second storage area comprises: Read the first target data corresponding to the read data request from the second storage area; The first target data is determined as the response information. 4. The method according to claim 2, wherein when the request information is a data write request, the acquiring response information corresponding to the request information from the second storage area comprises: storing the second target data carried by the write data request in the second storage area, and obtaining feedback information; The feedback information is determined as the response information. 5. The method according to claim 1, wherein the obtaining the request data packet from the first storage area by executing a test case comprises: When executing the test case, if it is determined that the preset response condition in the test case is satisfied, the request data packet is acquired from the first storage area. 6. A chip verification system, wherein the chip verification system is provided with a monitoring module, a service transmission channel, a driver module and a response module, The monitoring module is configured to, after receiving the request information sent by the chip, in response to the request information, generate a request data packet according to the request information, and send the request data packet to the service transmission channel; the service transmission channel, for buffering the request data packet to the first storage area after receiving the request data packet; The response module is configured to obtain the request data packet from the first storage area by executing a test case, access the second storage area via a preset access interface, and obtain the request data from the second storage area The response data packet corresponding to the packet; wherein, the preset access interface is a global interface; The service transmission channel is further configured to send the response data packet to the drive module after receiving the response data packet; The driving module is configured to send the response data packet to the chip after receiving the response data packet, so as to verify the data processing capability of the chip. 7. The chip verification system according to claim 6, wherein, The response module is specifically configured to parse the request data packet and obtain the request information; and access the second storage area via a preset access interface, and obtain the corresponding request information from the second storage area. response information; and generating the response data packet according to the response information. 8. The chip verification system according to claim 7, wherein, The response module is further specifically configured to read the first target data corresponding to the read data request from the second storage area; and determine the first target data as the response information. 9. The chip verification system according to claim 7, wherein, The response module is further configured to store the second target data carried by the write data request in the second storage area, and obtain feedback information; and determine the feedback information as the response information. 10. The chip verification system according to claim 6, wherein, The response module is further specifically configured to acquire the request data packet from the first storage area if it is determined that a preset response condition is satisfied when the test case is executed. 11. A chip verification system, characterized in that the chip verification system comprises a generation unit, a storage unit, a reading unit, an acquisition unit and a sending unit, The generating unit is configured to generate a request data packet according to the request information in response to the request information from the chip; the storage unit, configured to cache the request data packet to the first storage area; The obtaining unit is configured to obtain the request data packet from the first storage area by executing a test case; and access the second storage area via a preset access interface, and obtain the request data from the second storage area The response data packet corresponding to the packet; wherein, the preset access interface is a global interface; The sending unit is configured to send the response data packet to the chip to verify the data processing capability of the chip. 12. A computer-readable storage medium on which a program is stored, applied in a chip verification system, wherein the chip verification system is provided with a monitoring module, a service transmission channel, a driver module and a response module, wherein the program is When executed by the processor, the method according to any one of claims 1-5 is implemented.

Images