CN111859831A - Chip verification method and system, and storage medium - Google Patents
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Abstract
The embodiment of the application discloses a chip verification method, a chip verification system and a storage medium, wherein the method comprises the following steps: responding to request information from the chip, and generating a request data packet according to the request information; caching the request data packet to a first storage area; acquiring a request data packet from a first storage area by executing a test case, accessing a second storage area through a preset access interface, and acquiring a response data packet corresponding to the request data packet from the second storage area; the preset access interface is a global interface; and sending the response data packet to the chip to verify the data processing capability of the chip.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a chip verification method and system and a storage medium.
Background
With the rapid development of integrated circuits and the increase of chip scale, verification work in chip design becomes more difficult, which becomes the most expensive work in the process and occupies a larger and larger proportion of the whole design cycle. The verification effort has been 70% to 80% of the development of the entire integrated circuit (SOC) Chip. Therefore, how to effectively perform the chip test verification has become critical.
At present, in the technical field of artificial intelligence, an artificial intelligence chip based on a Convolutional Neural Network (CNN) mainly performs CNN operation through an artificial intelligence Core module (AI Core), thereby realizing artificial intelligence acceleration. Specifically, the artificial intelligence core module needs to actively and continuously carry data such as features, weights, offsets and the like from the out-of-core storage unit. Based on the design of the artificial intelligence core module, the verification personnel usually adopt a mode that a passive transaction unit is hung outside an active interface of the artificial intelligence module to carry out verification processing on the artificial intelligence chip, and the passive transaction unit and the artificial intelligence module cooperate to carry out mutual verification.
However, the existing chip verification method has complex operation in the verification process, and is low in configurability and reusability, and thus it is difficult to realize efficient chip verification.
Disclosure of Invention
The embodiment of the application provides a chip verification method and system and a storage medium, not only is the verification process simple to operate, but also the reusability and the configurability are high, and the efficient verification of the chip is further realized.
The technical scheme of the embodiment of the application is realized as follows:
in a first aspect, an embodiment of the present application provides a chip verification method, where the method includes:
Responding to request information from a chip, and generating a request data packet according to the request information;
caching the request data packet to a first storage area;
acquiring the request data packet from the first storage area by executing a test case, accessing a second storage area through a preset access interface, and acquiring a response data packet corresponding to the request data packet from the second storage area; the preset access interface is a global interface;
and sending the response data packet to the chip to verify the data processing capability of the chip.
In a second aspect, an embodiment of the present application provides a chip verification system, where the chip verification system is provided with a monitoring module, a service transmission channel, a driving module, and a response module,
the monitoring module is used for responding to request information after receiving the request information sent by a chip, generating a request data packet according to the request information and sending the request data packet to the service transmission channel;
the service transmission channel is used for caching the request data packet into a first storage area after receiving the request data packet;
the response module is used for reading the request data packet from the first storage area by executing a test case, accessing a second storage area through a preset access interface, and acquiring a response data packet corresponding to the request data packet from the second storage area; the preset access interface is a global interface;
The service transmission channel is further configured to send the response data packet to the driving module after receiving the response data packet;
and the driving module is used for sending the response data packet to the chip after receiving the response data packet so as to verify the data processing capacity of the chip.
In a third aspect, an embodiment of the present application provides a chip verification system, which includes a generation unit, a storage unit, a reading unit, an obtaining unit, and a sending unit,
the generating unit is used for responding to request information from a chip and generating a request data packet according to the request information;
the storage unit is used for caching the request data packet to a first storage area;
the obtaining unit is used for obtaining the request data packet from the first storage area by executing a test case; accessing a second storage area through a preset access interface, and acquiring a response data packet corresponding to the request data packet from the second storage area; the preset access interface is a global interface;
and the sending unit is used for sending the response data packet to the chip so as to verify the data processing capacity of the chip.
The embodiment of the application provides a chip verification method and system and a storage medium, wherein the chip verification system responds to request information from a chip and generates a request data packet according to the request information; caching the request data packet to a first storage area; acquiring a request data packet from a first storage area by executing a test case, accessing a second storage area through a preset access interface, and acquiring a response data packet corresponding to the request data packet from the second storage area; the preset access interface is a global interface; and sending the response data packet to the chip to verify the data processing capability of the chip.
Specifically, in the embodiment of the present application, the chip verification system may respectively process request information sent by the chip and response information returned to the chip through the monitoring module and the driving module; meanwhile, the chip verification system can also acquire the request information from the first storage area by executing the test case, and acquire the response information corresponding to the request information from the second storage area through the preset access interface; the preset access interface is a global interface so as to realize data updating and sharing among the verification components. Therefore, in the chip verification method and the chip verification system provided by the application, different modules are mutually independent to execute different verification functions, so that the chip verification system has high reusability; meanwhile, the interaction process of the request information and the response information is completed by executing the test case, so that the access to the second storage area through the global access interface can be realized, the data in the second storage area can be updated, the configurability is high, and the efficient verification of the chip is further realized.
Drawings
FIG. 1 is a block diagram of a UVM verification platform in the related art;
FIG. 2 is a block diagram of a passive transaction unit according to the related art;
fig. 3 is a schematic flow chart of a first implementation of the chip verification method provided in the present application;
FIG. 4 is a schematic diagram of a chip verification system implemented based on a UVM verification methodology according to the present application;
fig. 5 is a schematic diagram of an implementation flow of the chip verification method provided in the present application;
FIG. 6 is a first schematic diagram of a chip verification system according to the present application;
fig. 7 is a schematic structural diagram of a chip verification system according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are illustrative of the relevant application and are not limiting of the application. It should be noted that, for the convenience of description, only the parts related to the related applications are shown in the drawings.
Before further detailed description of the embodiments of the present invention, terms and expressions mentioned in the embodiments of the present invention are explained, and the terms and expressions mentioned in the embodiments of the present invention are applied to the following explanations.
1) Module Under Test (Design Under Test, DUT): in a modern Integrated Circuit (IC) design process, after a designer completes Register Transfer Level (RTL) codes according to a design specification, a verifier starts verifying the codes, which are generally called as a module under test (DUT).
2) Universal Verification Methodology (UVM): the system is a verification platform development framework taking a SystemVerilog class library as a main body, and a functional verification environment with a standardized hierarchical structure and an interface can be constructed by utilizing reusable components of the system. And finding out the bug in the DUT by putting the DUT into a built UVM verification platform.
Fig. 1 is a schematic diagram of a block diagram of a UVM verification platform in the related art, as shown in fig. 1, the UVM verification platform includes the following basic components, for example: (11) a module to be tested DUT; (12) the transaction unit agent: the transaction unit agent can instantiate the driver, the monitor and the sequence generator; the transaction unit Agent comprises an In _ Agent active transaction unit (121) and an Out _ Agent passive transaction unit (122); (13) monitor: monitoring input and output signals of a DUT (device under test), converting collected port data of the DUT into transaction-level information transaction, and handing the transaction-level information transaction to subsequent reference model and scoreboard components for processing; (14) driver: the device is used for applying various stimuli to a module to be tested DUT and is responsible for driving transaction-level information transactions which do not generate the transaction-level information transactions per se; (15) sequence generator sequence: the device is used for detecting whether a request for sending transaction-level information transaction exists in an arbitration queue and whether a driver applies for the transaction-level information transaction; (16) reference model: simulating the functional behavior of a module to be tested DUT, completing the same functions as the module to be tested DUT, and obtaining an expected result; the output of the test module DUT is received by the scoreboard and is used for being compared with the actual output of the DUT; (17) scoreboard: and judging whether the behavior of the module to be tested DUT is consistent with the expectation or not according to the output of the module to be tested DUT, and comparing the output of the DUT with the output of the reference model.
With the rapid development of integrated circuits and the increase of chip scale, verification work in chip design becomes more difficult, which becomes the most expensive work in the process and occupies a larger and larger proportion of the whole design cycle. The verification effort has been 70% to 80% of the development of the entire integrated circuit (SOC) Chip. Therefore, how to effectively perform the chip test verification has become critical.
At present, in the technical field of artificial intelligence, an artificial intelligence chip based on a network such as a CNN mainly performs CNN operation through an artificial intelligence Core module (AI Core), thereby realizing artificial intelligence acceleration. Specifically, because the artificial intelligence core module needs to actively carry data such as characteristics, weight, offset and the like from the extra-core storage unit, on the basis of the design of the artificial intelligence core module, the verification personnel usually adopt a mode that a passive transaction unit is hung on the active interface of the artificial intelligence module to carry out verification processing on the artificial intelligence chip, and the artificial intelligence core module and the passive transaction unit are matched to work and verify each other.
Fig. 2 is a schematic diagram illustrating a composition architecture of a passive transaction unit in the related art, and as shown in fig. 2, when the artificial intelligence core module is functionally verified, in the passive transaction unit agent (21), since the request is only passively received and fed back to the module under test DUT (21) (e.g., the artificial intelligence core module), it is often only implemented in the passive transaction unit (21) that the monitor (22) receives the request from the virtual interface (23), and then the monitor (22) instantiates the storage module (24); specifically, the monitor (22) updates or reads the data of the storage module (24) according to the received read-write request, further generates response data, and directly sends the response data to the virtual interface (23) to drive the module to be tested DUT (21).
However, since a high degree of reusability and configurability is required due to an efficient verification scheme, the verification system based on fig. 2 has the following drawbacks: firstly, the storage module is instantiated in the monitor, response data is driven to the module to be tested according to the data of the storage module, and the task of the driver is achieved, so that when the passive transaction unit is integrated and reused by the upper verification environment, only the monitoring function can be reused, and the function of the drive response cannot be reused, so that the reusability of the verification environment is low. Secondly, the memory module in the passive transaction unit often needs to be configured in the top-level environment, and since the monitor is not directly called by the upper-level environment, the upper-level environment is difficult to operate on the memory module therein. Further, as can be seen from fig. 2, the interaction between the monitor and the memory module is in the monitor, so that the upper environment and the test case cannot control the monitor and the test case (for example, changing data in the memory module, or adding response delay according to the context of the test case, etc.); therefore, the existing chip verification mode has complex verification process operation, low configurability and reusability, and is difficult to realize efficient chip verification.
In order to solve the problems of the existing chip verification mechanism, embodiments of the present application provide a chip verification method and system, and a storage medium. Specifically, in the chip verification system provided by the present application, the chip verification system can respectively process request information sent by a chip and response information returned to the chip through a monitoring module and a driving module; meanwhile, the chip verification system can also acquire the request information from the first storage area by executing the test case, and acquire the response information corresponding to the request information from the second storage area through the preset access interface; the preset access interface is a global interface so as to realize data updating and sharing among the verification components. Therefore, in the chip verification method and the chip verification system provided by the application, different modules are mutually independent to execute different verification functions, so that the chip verification system has high reusability; meanwhile, the interaction process of the request information and the response information is completed by executing the test case, so that the access to the second storage area through the global access interface can be realized, the data in the second storage area can be updated, the configurability is high, and the efficient verification of the chip is further realized.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
Optionally, in a preferred embodiment of the present application, the chip verification system may be implemented based on a UVM verification methodology, and a verification engineer may establish the chip verification system with a standard structure based on a schematic configuration diagram of the UVM verification platform shown in fig. 1, with predefined classes as a starting point. The driver module driver, monitor module monitor, and other components described below may be provided by an existing UVM verification platform. The verification personnel can construct the chip verification system by instantiating different verification components.
An embodiment of the present application provides a chip verification method, fig. 3 is a schematic view illustrating an implementation flow of the chip verification method provided in the present application, and as shown in fig. 3, in the embodiment of the present application, a chip verification method executed by a chip verification system may include the following steps:
In the embodiment of the application, the chip verification system may first receive request information sent by a chip to be tested, and further generate a request data packet corresponding to the request information in response to the request information.
It should be noted that, in the embodiment of the present application, the chip verification system may be constituted by at least one device. Optionally, the at least one device may be a physical server, a virtual server (e.g., a cloud server), a tablet computer, a Personal Computer (PC), a notebook computer, or other devices having a computing function and a storage function, and in this embodiment, the device to which the chip verification method is applied is not specifically limited.
Further, in a specific implementation process, the creation of the chip verification system in the embodiment of the present application may be completed based on at least one device, that is, the chip verification method may be executed by one device alone, or may be executed by multiple devices in cooperation.
It can be understood that, in the process of completing the corresponding RTL code by a designer according to a design specification of a chip, because of an understanding deviation or negligence of a verifier, the obtained RTL code may not necessarily reflect all characteristics of the chip, and therefore, the verifier often tests the basic function of the chip by building a corresponding verification environment.
Optionally, in an embodiment of the present application, the chip may be a core module with data transport capability, for example, an artificial intelligence chip based on a network such as a CNN; therefore, the data carrying capacity of the chip is verified through the chip verification system.
Specifically, in the embodiment of the present application, the data handling capability of the chip includes a capability of reading data from the out-of-core storage unit and a capability of writing data into the out-of-core storage unit, that is, request information of the chip acquired by the chip verification system includes a read data request and a write data request. When the acquired request information is a data reading request, indicating the data reading capability of the verification chip; and when the acquired request information is a data writing request, indicating the data writing capability of the verification chip.
It should be noted that, in the embodiment of the present application, after the chip verification system receives the request information of the chip, since data in the chip verification system is transmitted as transaction-level information, the chip verification system needs to convert the timing information corresponding to the request information into transaction-level information according to a timing protocol. Specifically, after receiving request information of a chip, a chip verification system performs transaction-level information encapsulation processing on the request information in response to the request information, thereby generating a request data packet corresponding to the request information.
For example, in an embodiment of the present application, in a chip verification system implemented based on a UVM verification methodology, the chip verification system may instantiate a monitor component, receive request information from a chip through a virtual interface (interface), and convert timing information corresponding to the request information into transaction-level information, thereby obtaining a request packet corresponding to the request information.
Further, in the embodiment of the present application, after the chip verification system receives the request information sent by the chip and generates the request data packet corresponding to the request information in response to the request information, the chip verification system may further store the request data packet.
In an embodiment of the application, after the chip verification system generates a request packet corresponding to the request information in response to the request information from the chip, the chip verification system may further cache the request packet in the first storage area.
It should be noted that, in the embodiment of the present application, the chip can implement Access to an out-of-core storage unit, such as different Random Access Memories (RAMs) or Read-Only memories (ROMs), by sending the request information, and further perform a data Read/write operation. However, since the bandwidth of the out-of-core storage unit is limited, the request packet of the chip that is continuously sent cannot be directly sent to the out-of-core storage unit, so the chip verification system designs a buffer space to buffer the request packet first, and the external storage unit can read the request packet from the buffer space when a certain condition is satisfied.
Specifically, the buffering process of the request packet in the present application refers to a storing operation performed according to the principle of "first-in first-out". That is to say, the chip verification system buffers the request data packets to the first storage area in sequence according to the time sequence of sending the request data packets, and the subsequent data packet obtaining process reads the request data packets from the first storage area in sequence according to the first-in first-out principle.
Illustratively, in the embodiment of the present application, in the chip verification system implemented based on the UVM verification methodology, the chip verification system may instantiate a sequencer sequence component, which serves as a data transmission channel, and may receive a request packet sent by a monitor through a TLM1 transmission unit layer model interface, and further buffer the request packet into a built-in First-out (FIFO) storage space, and then wait for the reading of the packet.
Further, in the embodiment of the present application, after the chip verification system caches the request data packet in the first storage area, the chip verification system may further obtain the request data packet from the first storage area by executing the test case, and perform response processing.
103, acquiring a request data packet from the first storage area by executing the test case, accessing the second storage area through a preset access interface, and acquiring a response data packet corresponding to the request data packet from the second storage area; and the preset access interface is a global interface.
In an embodiment of the application, after the chip verification system caches the request data packet in the first storage area, the chip verification system may obtain the request data packet from the first storage area by executing the test case, access the second storage area through a preset access interface, and further obtain a response data packet corresponding to the request data packet from the second storage area, where the preset access interface is a global interface.
It should be noted that, in the embodiment of the present application, the test case is a response test task having a plurality of predetermined condition parameters, which is set for the request information of the chip. Alternatively, the predetermined condition parameter may be a variety of preset response conditions set for the request information. Specifically, the preset response condition may be a periodic response request message; or may respond to the request message under certain conditions.
Further, the chip verification system can implement response processing on the request data packet cached in the first storage area by executing the test case. Specifically, when the chip verification system executes the test case, it may be determined whether a preset response condition in the test case is currently satisfied, and if it is determined that the preset response condition is satisfied, the chip verification system may obtain a corresponding request data packet from the first storage area and obtain a response data packet corresponding to the request data packet from the second storage area.
Optionally, when the preset response condition in the test case is that the request information is periodically responded, the chip verification system may periodically read the request data packet from the first storage area and respond; when the preset response condition in the test case is a specific condition, the chip verification system can read the request data packet from the first storage area and respond when the specific condition is met. Specifically, the chip verification system reads the request data packets from the first storage area in sequence on the first-in first-out principle, and responds in sequence.
It should be noted that, in the embodiment of the present application, the second storage area corresponds to an out-of-core storage unit for storing data, and the chip may perform a read-write operation on the data in the out-of-core storage unit by accessing the second storage area.
Further, in an embodiment of the present application, the chip verification system may access the second storage area through a preset access interface, and further acquire a response data packet corresponding to the request data packet from the second storage area, where the response data packet includes response information corresponding to the request information. Specifically, the chip verification system may obtain the response information in different ways according to different types of request information.
It should be noted that, in the embodiment of the present application, the preset access interface is a global interface, and it is understood that the global interface follows a principle of "define at one place, available at any place", that is, in the chip verification system, each verification component can implement global access to the second storage area through the preset access interface. Optionally, the chip verification system may access the second storage area through a preset access interface when executing the test case, and in addition, the chip verification system may also access the second storage area through a system upper environment or other verification components through the preset access interface.
Specifically, in the process of executing the verification processing of the chip, the chip verification system may access the second storage area through a preset access interface in an upper layer environment, so as to realize the "back door" access of the extra-core storage unit, so as to configure and update the data; or when the test case is executed, the second storage area is accessed through a preset access interface, so that the front door access of the extra-core storage unit is realized, and the configuration update of the data is carried out; and no matter what way and what verification component are used for configuring and updating the data of the extra-core storage unit, the updated data can be shared in each component.
Illustratively, in the embodiment of the present application, in a chip verification system implemented based on the UVM verification methodology, the chip verification system may instantiate a response sequence component, so that the response sequence component can read a request packet cached in an internal FIFO storage space when a preset response condition is met by executing a test case, and access a second storage area via a preset access interface according to the manner that the request packet is accessed in a front door manner, and obtain a response packet corresponding to the request information from the second storage area. In the chip verification processing process, if the data in the second storage area needs to be configured and updated, the second storage area can also be accessed through the upper layer environment in a back door access mode through a preset access interface so as to configure and update the data.
Further, in the embodiment of the application, the chip verification system reads the request data packet from the first storage area by executing the test case, accesses the second storage area through the preset access interface, and after acquiring the response data packet corresponding to the request data packet from the second storage area, the chip verification system may further send the response data packet to the chip, thereby implementing verification of the data processing capability of the chip.
And 104, sending the response data packet to the chip to verify the data processing capacity of the chip.
In the embodiment of the application, after the chip verification system reads the request data packet from the first storage area and acquires the response data packet corresponding to the request data packet from the second storage area by executing the test case, the chip verification system can send the response data packet to the chip, so that the verification of the data processing capability of the chip is realized.
It should be noted that, in the embodiment of the present application, since data in the chip verification system is transmitted by transaction-level information, when the response packet is transmitted between the chips, the transaction-level information corresponding to the response packet needs to be converted into the timing information according to the timing protocol, and then the timing information corresponding to the request response is sent to the chip.
Further, by testing whether the chip sends the request information and whether the chip can receive the response information corresponding to the request information, the data processing capability of the chip, namely the capability of transporting data from the out-of-core storage unit, is verified.
Illustratively, in the embodiment of the present application, in the chip verification system implemented based on the UVM verification methodology, the response sequence is determined when a preset response condition is satisfied, the second storage area is accessed through the preset access interface, and after the response data packet corresponding to the request data packet is acquired from the second storage area, the response data packet may be sent to the service transmission channel sequence first, then the TLM1 transmission unit layer model of the channel service transmission channel transmits the response data packet to the driver, that is, the response data packet needs to be transmitted between the response sequence and the driver through the service transmission channel, further, the driver converts the transaction level information corresponding to the response data packet into time sequence information after receiving the response data packet, and the time sequence information is transmitted to the chip by calling the virtual interface, thereby realizing the verification of the data processing capacity of the chip.
Fig. 4 is a schematic diagram illustrating a component structure of a chip verification system (30) implemented based on a UVM verification methodology according to an embodiment of the present disclosure, as shown in fig. 4, specifically, the chip verification system receives request information sent from a chip DUT (40) from a virtual interface (32) through a monitor module monitor (31), generates a request data packet corresponding to the request information, and then transmits the request data packet to a traffic transmission channel sequence (34) through a TLM2 transport unit layer model (33); after receiving the request data packet transmitted by the monitoring module (31), the service transmission channel (34) buffers the request data packet into a built-in FIFO storage space, and waits for a response module response sequence (35) to take; further, by executing the test case, the response module (35) starts to obtain the request data packet delivered by the monitoring module (32) from the FIFO storage space of the traffic transmission channel (34) through the transmission unit (36), and accesses the second storage area (37) to obtain the request response from the second storage area (37), so as to further send the response data packet to the driver module driver (39) through the TLM1 transmission unit layer model (38) of the traffic transmission channel, and send the response data packet to the chip DUT (40) through the virtual interface (32) to respond to the request of the chip DUT (40).
Wherein the monitoring module (31), the traffic transmission channel (34) and the driver (39) are all encapsulated in a passive transaction unit (310), and the transmission unit (36) and the second storage area (37) are encapsulated in a response sequence module (35); meanwhile, the upper layer environment can also access the second storage area in the passive transaction unit (310) through a preset access interface, so that the data in the out-of-core storage unit can be configured and updated. That is to say, in the chip verification system, the upper environment may access the second storage area through the preset access interface, and perform data update processing on the second storage area; and when the test case is executed, the second storage area is accessed through the preset access interface, and the data in the second storage area is updated through the read-write operation of the data in the second storage area.
The embodiment of the application provides a chip verification method.A chip verification system responds to request information from a chip and generates a request data packet according to the request information; caching the request data packet to a first storage area; acquiring a request data packet from a first storage area by executing a test case, accessing a second storage area through a preset access interface, and acquiring a response data packet corresponding to the request data packet from the second storage area; the preset access interface is a global interface; and sending the response data packet to the chip to verify the data processing capability of the chip. Specifically, in the embodiment of the present application, the chip verification system may respectively process request information sent by the chip and response information returned to the chip through the monitoring module and the driving module; meanwhile, the chip verification system can also acquire the request information from the first storage area by executing the test case, and acquire the response information corresponding to the request information from the second storage area through the preset access interface; the preset access interface is a global interface so as to realize data updating and sharing among the verification components. Therefore, in the chip verification method and the chip verification system provided by the application, different modules are mutually independent to execute different verification functions, so that the chip verification system has high reusability; meanwhile, the interaction process of the request information and the response information is completed by executing the test case, so that the access to the second storage area through the global access interface can be realized, the data in the second storage area can be updated, the configurability is high, and the efficient verification of the chip is further realized.
Based on the foregoing embodiment, in another embodiment of the present application, fig. 5 is a schematic view of an implementation flow of a chip verification method provided by the present application, and as shown in fig. 5, in the embodiment of the present application, a method for accessing a second storage area by a chip verification system through a preset access interface and acquiring a response packet corresponding to a request packet from the second storage area may include the following steps:
In the embodiment of the application, after the chip verification system reads the request data packet from the first storage area by executing the test case, the chip verification system may analyze the request data packet and obtain the corresponding request information from the request data packet.
It should be noted that, in the embodiment of the present application, data in the chip verification system is transmitted by transaction-level information, that is, time-sequence information is encapsulated according to a time-sequence protocol and is converted into transaction-level information to be transmitted in the chip verification system, so that when the chip verification system executes response processing according to a request packet, the request packet needs to be decapsulated, and then corresponding request information is parsed from the request packet.
For example, in the chip verification system implemented based on the UVM verification methodology, after the request packet is obtained from the first storage region in response to the sequence, the request packet may be analyzed, so as to obtain the request information corresponding to the request packet.
Further, in the embodiment of the present application, after the chip verification system obtains the request packet through parsing of the request packet, the chip verification system may further obtain response information corresponding to the request information from the second storage area.
In the embodiment of the application, after the chip verification system obtains the request data packet through the parsing of the request data packet, the chip verification system may further access the second storage area through the preset access interface, and further obtain the response information corresponding to the request information from the second storage area.
It is understood that, in the embodiments of the present application, the data handling capability of the chip includes a capability of reading data from the out-of-core storage unit and a capability of writing data into the out-of-core storage unit, that is, request information of the chip acquired by the chip verification system includes a read data request and a write data request.
Specifically, when the acquired request information is a read data request, the chip verification system may access the second storage area via the preset access interface, and read the first target data corresponding to the read data request from the second storage area according to the read data request, so as to determine the first target data as response information corresponding to the read data request.
Specifically, when the acquired request information is a write data request, where the write data request carries second target data, the chip verification system may access the second storage area through a preset access interface, and write the second target data carried in the write data request into the second storage area according to the write data request. Further, during a write operation, the chip verification system may generate a feedback information to indicate a write operation completion result through the feedback information, and the chip verification system may use the feedback information as a response information corresponding to the write data request.
Further, in the embodiment of the application, when the second target data carried by the write data request is written into the second storage area, the data in the out-of-core storage unit corresponding to the second storage area is configured and updated, and the updated data can be shared in each component.
Illustratively, in the embodiment of the present application, in the chip verification system implemented based on the UVM verification methodology, the response sequence not only reads the request packet from the FIFO storage space built in the service transmission channel and parses the request information, but also when accessing the second storage area to obtain the response information, performs corresponding data read/write operations according to different types of request information, thereby obtaining the response information corresponding to the request information.
Further, in the embodiment of the present application, after the chip verification system acquires the response information corresponding to the request information, the chip verification system may further generate a response data packet corresponding to the response information.
It should be noted that, in the embodiment of the present application, after the chip verification system acquires the response information corresponding to the request information of the chip, since data in the chip verification system is transmitted as transaction-level information, the chip verification system needs to convert the timing information corresponding to the response information into transaction-level information according to a timing protocol. Specifically, after the chip verification system obtains the response information of the chip, the transaction-level information is encapsulated in the response information, so that a response data packet corresponding to the response information is generated.
The embodiment of the application provides a chip verification method, in a chip verification system, a response module can read and analyze a request data packet in a first storage area by executing a test case, can access a second storage area through a global access interface, and executes response processing in different modes according to the type of acquired request information, the verification process is simple to operate, high reusability and configurability are achieved, and efficient verification of a chip is further achieved.
In another embodiment of the present application, based on the schematic structural diagram of the chip verification system shown in fig. 4, fig. 6 is a structural diagram of the chip verification system, as shown in fig. 6, a chip verification system 30 provided in the embodiment of the present application is provided with a monitoring module 31, a service transmission channel 34, a driving module 39, and a response module 35, wherein the monitoring module 31, the service transmission channel 34, and the driving module 39 are packaged in a passive transaction unit 310,
the monitoring module 31 is configured to, after receiving request information sent by a chip, respond to the request information, generate a request data packet according to the request information, and send the request data packet to the service transmission channel;
The service transmission channel 34 is configured to, after receiving the request data packet, cache the request data packet in the first storage area;
the response module 35 is configured to obtain the request data packet from the first storage area by executing the test case, access the second storage area through the preset access interface, and obtain a response data packet corresponding to the request data packet from the second storage area; the preset access interface is a global interface;
the service transmission channel 34 is further configured to send the response data packet to the driving module after receiving the response data packet;
the driving module 39 is configured to send the response data packet to the chip after receiving the response data packet, so as to verify the data processing capability of the chip.
Further, in an embodiment of the present application, the response module 35 is specifically configured to parse the request data packet to obtain the request information; accessing a second storage area through a preset access interface, and acquiring response information corresponding to the request information from the second storage area; and generating the response data packet according to the response information.
Further, in this embodiment of the application, the response module 35 is further specifically configured to read the first target data corresponding to the read data request from the second storage area; and determining the first target data as the response information.
Further, in an embodiment of the present application, the response module 35 is further specifically configured to store second target data carried by the data writing request in the second storage area, and acquire feedback information; and determining the feedback information as the response information.
Further, in the embodiment of the present application, the response module 35 is further specifically configured to, when the test case is executed, obtain the request data packet from the first storage area if it is determined that a preset response condition is met.
It should be noted that, in the embodiment of the present application, the chip verification system does not centrally configure the two processes of receiving the request information of the chip and sending the response information to the chip in the monitoring module, and the monitoring module does not have a function of driving response; but the reception of the request information and the transmission of the response information are performed by the monitoring module and the driving module, respectively.
Specifically, the chip verification system receives request information of the chip through the monitoring module, converts time sequence information corresponding to the request information into transaction-level information, namely generates a request data packet corresponding to the request information, and further sends the request data packet to the service transmission channel through the monitoring module.
Specifically, the chip verification system receives a response data packet corresponding to a request data packet transmitted from a service transmission channel through a driving module, converts transaction-level information corresponding to the response data packet into time-sequence information, and further sends the response information to the chip through the driving module to verify the data processing capability of the chip.
Therefore, in the embodiment of the application, the chip verification system distinguishes the functions of the components, so that different functions are independently executed among the modules, and the verification components can be conveniently reused in an upper-layer environment.
It should be noted that, in the embodiment of the present application, the chip verification system does not set the monitoring module that reads the request information and places the processes of acquiring the response information by interacting with the storage unit in the passive transaction unit, but sets the independent passive transaction unit and the response module, so as to receive the request information and the service transmission channel cache request information by the monitoring module in the passive transaction unit, and respond to the request information by the response module, that is, by executing the test case, place the interaction process of the request information and the response information in the response module, and by configuring and opening each component, transfer of the request information and the response information between the passive transaction unit and the response module is achieved.
Specifically, the chip verification system caches a received request data packet sent by the monitoring module to a first storage area through a service transmission channel, and waits for a response module to take the request data packet. And then, by executing the test case, the response module acquires the request data packet from the first storage area in the service transmission channel, accesses the extra-core storage unit corresponding to the second storage area through the preset access interface, acquires the corresponding response data packet from the second storage area according to the request data packet, and then returns the acquired response data packet to the service transmission channel.
Further, in the embodiment of the present application, the preset access interface is a global interface, and it can be understood that the global interface follows a principle of "define at one place, available at all places", that is, in the chip verification system, each verification component can implement global access to the second storage area through the preset access interface. Optionally, the chip verification system may access the second storage area through a preset access interface when executing the test case, and in addition, the chip verification system may also access the second storage area through a system upper environment or other verification components through the preset access interface.
Specifically, in the process of executing the verification processing of the chip, the chip verification system may access the second storage area through a preset access interface in an upper layer environment, so as to realize the "back door" access of the extra-core storage unit, so as to configure and update the data; or when the test case is executed, the second storage area is accessed through a preset access interface, so that the front door access of the extra-core storage unit is realized, and the configuration update of the data is carried out; and no matter what way and what verification component are used for configuring and updating the data of the extra-core storage unit, the updated data can be shared in each component.
Therefore, in the embodiment of the application, the chip verification system places the interaction process of the request information and the response information in the response module by executing the test case, and can realize the access to the second storage address through the global interface to control the data in the second storage area, thereby improving the configurability of the chip verification system.
Optionally, in the chip verification system, the upper environment may access the second storage area through a preset access interface in the passive transaction unit, so as to implement configuration update on data in the out-of-core storage unit; or in a service transmission channel in the passive transaction unit, the second storage area is accessed through a preset access interface, so that the data in the out-of-core storage unit is configured and updated.
The embodiment of the application provides a chip verification system, which can respectively process request information sent by a chip and response information returned to the chip through a monitoring module and a driving module; meanwhile, the chip verification system can also acquire the request information from the first storage area by executing the test case, and acquire the response information corresponding to the request information from the second storage area through the preset access interface; the preset access interface is a global interface so as to realize data updating and sharing among the verification components. Therefore, in the chip verification method and the chip verification system provided by the application, different modules are mutually independent to execute different verification functions, so that the chip verification system has high reusability; meanwhile, the interaction process of the request information and the response information is completed by executing the test case, the global access to the second storage area can be realized through the preset access interface, so that the data in the second storage area can be updated, the configurability is high, and the efficient verification of the chip is further realized.
Based on the above embodiments, in another embodiment of the present application, fig. 7 is a schematic structural diagram of a composition of the chip verification system provided in the present application, and as shown in fig. 7, the chip verification system 30 provided in the embodiment of the present application may include a generating unit 311, a storing unit 312, an obtaining unit 313 and a sending unit 314.
The generating unit 311 is configured to generate a request data packet according to request information from a chip in response to the request information;
the storage unit 312 is configured to cache the request packet to a first storage area;
the obtaining unit 313 is configured to obtain the request data packet from the first storage area by executing a test case; accessing a second storage area through a preset access interface, and acquiring a response data packet corresponding to the request data packet from the second storage area; the preset access interface is a global interface;
the sending unit 314 is configured to send the response packet to the chip to verify the data processing capability of the chip.
Further, in an embodiment of the present application, the obtaining unit 313 is specifically configured to parse the request packet to obtain the request information; accessing a second storage area through a preset access interface, and acquiring response information corresponding to the request information from the second storage area; and generating the response data packet according to the response information.
Further, in this embodiment of the application, the obtaining unit 313 is further specifically configured to read the first target data corresponding to the read data request from the second storage area; and determining the first target data as the response information.
Further, in an embodiment of the present application, the obtaining unit 313 is further specifically configured to store second target data carried in the write data request in the second storage area, and obtain feedback information; and determining the feedback information as the response information.
Further, in this embodiment of the application, the obtaining unit 313 is further specifically configured to, when the test case is executed, obtain the request packet from the first storage area if it is determined that a preset response condition in the test case is met.
The embodiment of the application provides a chip verification system, wherein different modules in the chip verification system are mutually independent to execute different verification functions, so that the chip verification system has high reusability; meanwhile, the interaction process of the request information and the response information is completed by executing the test case, so that the access to the second storage area through the global access interface can be realized, the data in the second storage area can be updated, the configurability is high, and the efficient verification of the chip is further realized.
The embodiment of the application provides a computer-readable storage medium, on which a program is stored, and the program is applied to a chip verification system, the chip verification system is provided with a monitoring module, a service transmission channel, a driving module and a response module, and the program is executed by a processor to implement the chip verification method.
Specifically, the program instructions corresponding to a chip verification method in this embodiment may be stored in a storage medium such as an optical disc, a hard disc, a usb disk, or the like, and when the program instructions corresponding to a chip verification method in the storage medium are read or executed by an electronic device, the method includes the following steps:
responding to request information from a chip, and generating a request data packet according to the request information;
caching the request data packet to a first storage area;
acquiring the request data packet from the first storage area by executing a test case, accessing a second storage area through a preset access interface, and acquiring a response data packet corresponding to the request data packet from the second storage area; the preset access interface is a global interface;
and sending the response data packet to the chip to verify the data processing capability of the chip.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of implementations of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart block or blocks and/or flowchart block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks in the flowchart and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present application, and is not intended to limit the scope of the present application.
Claims (12)
1. A method of chip verification, the method comprising:
responding to request information from a chip, and generating a request data packet according to the request information;
caching the request data packet to a first storage area;
acquiring the request data packet from the first storage area by executing a test case, accessing a second storage area through a preset access interface, and acquiring a response data packet corresponding to the request data packet from the second storage area; the preset access interface is a global interface;
and sending the response data packet to the chip to verify the data processing capability of the chip.
2. The method according to claim 1, wherein the accessing the second storage area via the preset access interface and obtaining the response packet corresponding to the request packet from the second storage area comprises:
analyzing the request data packet to acquire the request information;
accessing a second storage area through a preset access interface, and acquiring response information corresponding to the request information from the second storage area;
and generating the response data packet according to the response information.
3. The method according to claim 2, wherein when the request information is a read data request, the obtaining response information corresponding to the request information from the second storage area includes:
reading first target data corresponding to the read data request from the second storage area;
and determining the first target data as the response information.
4. The method of claim 2, wherein when the request information is a request for writing data, the obtaining response information corresponding to the request information from the second storage area comprises:
storing second target data carried by the data writing request to the second storage area, and acquiring feedback information;
And determining the feedback information as the response information.
5. The method of claim 1, wherein the retrieving the request packet from the first storage area by executing the test case comprises:
and when the test case is executed, if the preset response condition in the test case is judged to be met, acquiring the request data packet from the first storage area.
6. A chip verification system is characterized in that the chip verification system is provided with a monitoring module, a service transmission channel, a driving module and a response module,
the monitoring module is used for responding to request information after receiving the request information sent by a chip, generating a request data packet according to the request information and sending the request data packet to the service transmission channel;
the service transmission channel is used for caching the request data packet into a first storage area after receiving the request data packet;
the response module is used for acquiring the request data packet from the first storage area by executing a test case, accessing a second storage area through a preset access interface, and acquiring a response data packet corresponding to the request data packet from the second storage area; the preset access interface is a global interface;
The service transmission channel is further configured to send the response data packet to the driving module after receiving the response data packet;
and the driving module is used for sending the response data packet to the chip after receiving the response data packet so as to verify the data processing capacity of the chip.
7. The chip verification system according to claim 6,
the response module is specifically configured to parse the request data packet to obtain the request information; accessing a second storage area through a preset access interface, and acquiring response information corresponding to the request information from the second storage area; and generating the response data packet according to the response information.
8. The chip verification system according to claim 7,
the response module is further specifically configured to read first target data corresponding to the read data request from the second storage area; and determining the first target data as the response information.
9. The chip verification system according to claim 7,
the response module is further specifically configured to store second target data carried by the write data request in the second storage area, and acquire feedback information; and determining the feedback information as the response information.
10. The chip verification system according to claim 6,
the response module is further specifically configured to, when the test case is executed, obtain the request packet from the first storage area if it is determined that a preset response condition is satisfied.
11. A chip verification system is characterized by comprising a generation unit, a storage unit, a reading unit, an acquisition unit and a sending unit,
the generating unit is used for responding to request information from a chip and generating a request data packet according to the request information;
the storage unit is used for caching the request data packet to a first storage area;
the obtaining unit is used for obtaining the request data packet from the first storage area by executing a test case; accessing a second storage area through a preset access interface, and acquiring a response data packet corresponding to the request data packet from the second storage area; the preset access interface is a global interface;
and the sending unit is used for sending the response data packet to the chip so as to verify the data processing capacity of the chip.
12. A computer-readable storage medium, on which a program is stored, for use in a chip authentication system, the chip authentication system being provided with a monitoring module, a traffic transmission channel, a driver module, and a response module, wherein the program, when executed by a processor, implements the method according to any one of claims 1 to 5.
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