CN116389357B - Hole address processing method, device, equipment and medium based on network on chip - Google Patents
Hole address processing method, device, equipment and medium based on network on chip Download PDFInfo
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- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention relates to the technical field of computers, and discloses a hole address processing method, device, equipment and medium based on a network on chip, wherein the method comprises the following steps: receiving a transaction request sent by a main device, wherein the transaction request comprises an access address; determining whether the access address is a hole address; generating first transaction response information based on the transaction request and transmitting the first transaction response information to the master device if the access address is a hole address; and under the condition that the access address is not the hole address, sending the transaction request to the corresponding slave device side network interface unit through the routing network so as to enable the corresponding slave device side network unit to send the transaction request to the corresponding slave device. The invention can enable the transaction request containing the hole address to obtain the corresponding response without being transmitted through the routing network, thereby not only realizing transaction integrity, but also effectively avoiding the waste of network-on-chip routing bandwidth.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a method, an apparatus, a device, and a medium for processing a hole address based on a network on chip.
Background
With the development of technology, the bus architecture on the chip has failed to meet the needs of high-performance high-throughput transactions, and Network On Chip (NOC) has grown. The network on chip is composed of a network interface unit NIU (Network interface unit, NIU) responsible for protocol conversion and a routing network comprising a plurality of routers. The network on chip can support simultaneous access from a plurality of master devices (masters) to a plurality of slave devices (slave), and in the process of access, the NIU can map the target address of the slave devices according to the access address in the transaction request sent by the master device, then find the position of the slave device corresponding to the target address and transmit the transaction request to the slave device through a routing packet.
However, in the case where the address in the transaction request issued by the host device is a hole address, the network-on-chip may have a running error because the transaction request cannot be processed. The hole address refers to an unused virtual memory address on the chip, i.e., an address that cannot be accessed. In order to avoid the running error of the network on chip caused by the fact that the master device sends out the hole address, a default slave device (default slave) is added on the slave device side in the related art, and all transaction requests containing the hole address are sent to the default slave device through the routing network for processing. However, such a processing manner not only results in that a piece of routing information needs to be configured between each master device and the default slave device, but also causes invalid data to occupy transmission resources of the network-on-chip, and causes waste of routing bandwidth of the network-on-chip.
Disclosure of Invention
In view of the above, the present invention provides a method, apparatus, device and medium for processing a transaction request based on a network-on-chip, so as to solve the problem in the prior art that the network-on-chip processes the hole address sent by the main device to cause the waste of the network-on-chip routing bandwidth.
In a first aspect, the present invention provides a transaction request processing method based on a network-on-chip, where the network-on-chip includes a master device side network interface unit, a slave device side network interface unit, and a routing network, and the method is applied to the master device side network interface unit; the method comprises the following steps: receiving a transaction request sent by a main device; the transaction request includes an access address; determining whether the access address is a hole address; the hole address refers to an unused virtual memory address in a virtual memory space of a chip where the network on chip is located; generating first transaction response information based on the transaction request and transmitting the first transaction response information to the master device if the access address is a hole address; if the access address is not a hole address, the transaction request is sent to a corresponding slave device side network interface unit through the routing network, so that the corresponding slave device side network unit can send the transaction request to the corresponding slave device; wherein the determining whether the access address is a hole address includes: determining whether a target address capable of being mapped exists in the access address or not based on pre-stored memory address mapping relation information; determining that the access address is not a hole address in the case that the access address has a mappable destination address; and determining that the access address is a hole address in the case that the access address does not have a destination address capable of being mapped.
In an alternative embodiment, in a case where the access address is a hole address, the method further includes: generating abnormal reminding information of the request; and sending the request abnormality reminding information to a central processing unit of the chip.
In an alternative embodiment, in a case where the access address is a hole address, the method further includes: in the process of converting the transaction request sent by the main equipment into a corresponding routing packet, not executing routing packet conversion processing on the transaction request containing the hole address; or after converting the transaction request sent by the master device into a corresponding routing packet, discarding the routing packet converted by the transaction request containing the hole address.
In an optional implementation manner, the sending, by the routing network, the transaction request to a corresponding slave-side network interface unit, where the access address is not a hole address, so that the corresponding slave-side network unit sends the transaction request to a corresponding slave device, includes: converting the transaction request into a first routing packet if the access address is not a hole address; determining a slave device corresponding to the destination address of the access address mapping and a slave device side network interface unit corresponding to the slave device; and sending the first routing packet to the corresponding slave device side network interface unit through the routing network, so that the corresponding slave device side network unit converts the first routing packet into the transaction request and sends the transaction request to the slave device.
In an optional implementation manner, after the sending, by the routing network, the transaction request to the corresponding slave-side network interface unit in the case where the access address is not a hole address, the method further includes: receiving a second routing packet from the routing network; the second routing packet is a routing packet after the slave device side network interface unit converts second transaction response information returned by the slave device; the second transaction response information is response information generated by the slave device according to the transaction request; converting the second routing packet into second transaction response information; and sending the second transaction response information to the master device.
In an alternative embodiment, the transaction request is a request initiated by the master device based on a preset communication protocol, the transaction request further comprising one or more of a read request and a write request.
In a second aspect, the present invention provides a transaction request processing apparatus based on a network on chip, where the network on chip includes a master device side network interface unit, a slave device side network interface unit, and a routing network, and the transaction request processing apparatus is configured in the master device side network interface unit; the device comprises: the receiving module is used for receiving a transaction request sent by the main equipment; the transaction request includes an access address; the address judging module is used for determining whether the access address is a hole address or not; the hole address refers to an unused virtual memory address in a virtual memory space of a chip where the network on chip is located; a backup slave device module, configured to generate first transaction response information based on the transaction request and send the first transaction response information to the master device if the access address is a hole address; the processing module is used for sending the transaction request to the corresponding slave device side network interface unit through the routing network when the access address is not the hole address, so that the corresponding slave device side network unit can send the transaction request to the corresponding slave device; the address judging module is also used for determining whether the access address has a mappable destination address or not based on the pre-stored memory address mapping relation information; determining that the access address is not a hole address in the case that the access address has a mappable destination address; and determining that the access address is a hole address in the case that the access address does not have a destination address capable of being mapped.
In a third aspect, the present invention provides a computer device comprising: the processor executes the computer instructions, thereby executing the transaction request processing method based on the network on chip according to the first aspect or any implementation manner corresponding to the first aspect.
In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon computer instructions for causing a computer to execute the network-on-chip based transaction request processing method of the first aspect or any of its corresponding embodiments.
The technical scheme of the invention has the following advantages.
The invention provides a hole address processing method, a device, equipment and a medium based on a network-on-chip, wherein the network-on-chip comprises a master equipment side network interface unit, a slave equipment side network interface unit and a routing network, and the method is applied to the master equipment side network interface unit; the hole address processing method based on the network on chip comprises the following steps: receiving a transaction request sent by a main device, wherein the transaction request comprises an access address; determining whether the access address is a hole address, wherein the hole address is an unused virtual memory address in a virtual memory space of a chip where the network on chip is located; transmitting the transaction request to the corresponding slave device side network interface unit through the routing network under the condition that the access address is not the hole address, so that the corresponding slave device side network unit can transmit the transaction request to the corresponding slave device; under the condition that the access address is a hole address, first transaction response information is generated based on the transaction request, and the first transaction response information is sent to the main equipment, so that the transaction request containing the hole address can obtain corresponding response without being transmitted through a routing network, transaction integrity can be achieved, transmission resources of the network-on-chip occupied by invalid information can be reduced under the condition that stable operation of a chip is ensured, and waste of network-on-chip routing bandwidth is effectively avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a transaction request processing method based on a network on chip according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a network on chip structure according to an embodiment of the present invention.
FIG. 3 is a flow chart of a method of determining whether an access address is a hole address according to an embodiment of the present invention.
Fig. 4 is a flow chart of another network-on-chip based transaction request processing method according to an embodiment of the present invention.
Fig. 5 is a flowchart of a method of transmitting a transaction request to a corresponding slave-side network interface unit over a routing network, according to an embodiment of the present invention.
Fig. 6 is a flow chart of yet another network-on-chip based transaction request processing method according to an embodiment of the present invention.
Fig. 7 is a transaction request processing device based on a network on chip according to an embodiment of the present invention.
Fig. 8 is a schematic structural view of a computer device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Fig. 1 is a flowchart of a transaction request processing method based on a network on chip according to an embodiment of the present invention. The network on chip is a novel communication architecture designed for a multi-core System on chip (SoC).
Fig. 2 is a schematic diagram of a network on chip structure according to an embodiment of the present invention. As shown in fig. 2, the network-on-chip 100 includes at least one master-side network interface unit (NIUm) 101, at least one slave-side Network Interface Unit (NIUs) 102, and a routing network 103, wherein the master-side network interface unit 101 and the slave-side network interface unit 102 are communicatively connected through the routing network 103.
The transaction request processing method based on the network on chip provided in fig. 1 in the embodiment of the invention is applied to the network interface unit at the main equipment side.
As shown in fig. 1, the transaction request processing method based on the network on chip includes the following steps: step S1-step S4.
Step S1, a transaction request sent by a main device is received.
The master device is a device capable of initiating information transmission and has the capability of actively initiating communication. A slave device is a device that cannot actively initiate the transfer of information.
The transaction request is a request initiated by the master device for access to the slave device. The transaction request contains an access address that characterizes a virtual memory address of a slave device that the master device wants to access, and control information that includes one or more of a read request and a write request.
In some embodiments, the transaction request is a request initiated by the master device based on a preset communication protocol, such as AXI protocol (Advanced eXtensible Interface, a bus protocol), AHB protocol (Advanced High Performance Bus, advanced high performance bus protocol), and the like.
Step S2, determining whether the access address is a hole address.
The hole address refers to an unused virtual memory address in a virtual memory space of a chip where the network on chip is located.
It should be noted that, in some related technologies, after the network interface unit at the host device side receives the transaction request sent by the host device, it will not check whether the address in the transaction request is a hole address, in this case, when the address in the transaction request sent by the host device is a hole address, the network on chip will have an operation error because the transaction request cannot be processed, which results in poor robustness of the network on chip and unable to operate stably. In the embodiment of the invention, the address judging function is added in the network interface unit at the main equipment side and is used for determining whether the access address is the hole address, so that the transaction request containing the hole address can be correspondingly processed in time under the condition that the access address is the hole address, and the robustness of the network on chip is improved.
And step S3, generating first transaction response information based on the transaction request and sending the first transaction response information to the master device when the access address is a hole address.
Wherein the first transaction response information is response information of the transaction request generated by the network interface unit at the main equipment side. The first transaction response information comprises a request identifier of a transaction request, and the request identifier is used for representing that the first transaction response information is response information corresponding to the transaction request.
It should be noted that, in other related art, in order to avoid an operation error of the network on chip caused by the master device sending out the hole address, a default slave device (default slave) is added in the slave device, and all transaction requests including the hole address are sent to the default slave device through the routing network for processing. However, such a processing manner not only results in that a piece of routing information needs to be configured between each master device and the default slave device, but also causes invalid data to occupy transmission resources of the network-on-chip, and causes waste of routing bandwidth of the network-on-chip. In the embodiment of the invention, the response function of the transaction request is added in the network interface unit at the main equipment side, so that the transaction request containing the hole address can be correspondingly responded without being transmitted through a routing network, the requirements of a communication protocol used for initiating the transaction request can be met, the transaction integrity is realized, the transmission resource of the network on chip occupied by invalid information can be reduced under the condition of ensuring the stable operation of the chip, and the waste of the routing bandwidth of the network on chip is effectively avoided.
And step S4, under the condition that the access address is not the hole address, sending the transaction request to the corresponding slave device side network interface unit through the routing network so that the corresponding slave device side network unit can send the transaction request to the corresponding slave device.
When the access address is not the hole address, the transaction request can be normally transmitted in the routing network, so that the transaction request is sent to the corresponding slave device side network interface unit through the routing network, so that the corresponding slave device side network unit sends the transaction request to the corresponding slave device, and the slave device processes the transaction request.
The embodiment of the invention provides a transaction request processing method based on a network-on-chip, wherein the network-on-chip comprises a master equipment side network interface unit, a slave equipment side network interface unit and a routing network, and the method is applied to the master equipment side network interface unit; the method comprises the following steps: receiving a transaction request sent by a main device, wherein the transaction request comprises an access address; determining whether the access address is a hole address, wherein the hole address is an unused virtual memory address in a virtual memory space of a chip where the network on chip is located; transmitting the transaction request to the corresponding slave device side network interface unit through the routing network under the condition that the access address is not the hole address, so that the corresponding slave device side network unit can transmit the transaction request to the corresponding slave device; under the condition that the access address is a hole address, first transaction response information is generated based on the transaction request, and the first transaction response information is sent to the main equipment, so that the transaction request containing the hole address can obtain corresponding response without being transmitted through a routing network, transaction integrity can be achieved, transmission resources of the network-on-chip occupied by invalid information can be reduced under the condition that stable operation of a chip is ensured, and waste of network-on-chip routing bandwidth is effectively avoided.
FIG. 3 is a flow chart of a method of determining whether an access address is a hole address according to an embodiment of the present invention. As shown in fig. 3, the step of determining whether the access address is a hole address (step S2 described above) includes: step S21 to step S23.
Step S21, determining whether the access address has a mappable destination address or not based on the pre-stored memory address mapping relation information.
The memory address mapping relation information is information containing mapping relation between virtual memory addresses and physical addresses in a chip where the network on chip is located. The destination address is the physical address of the slave device indicated by the access address.
In step S22, when there is a mappable destination address in the access address, it is determined that the access address is not a hole address.
When there is a destination address that can be mapped to the access address, it is described that the slave device that processes the transaction request can be found by the access address, and therefore the access address is valid and not a hole address.
Step S23, when the access address does not have a mappable destination address, it is determined that the access address is a hole address.
If the access address does not have a mappable destination address, it is indicated that the access address is an unused virtual memory address, and the slave device that handles the transaction request cannot be found by the access address, and therefore the access address is a hole address.
In the embodiment of the invention, the address judging function is added in the network interface unit at the main equipment side and is used for determining whether the access address is the hole address, so that the transaction request containing the hole address can be correspondingly processed in time under the condition that the access address is the hole address, and the robustness of the network on chip is improved.
Fig. 4 is a flow chart of another network-on-chip based transaction request processing method according to an embodiment of the present invention. As shown in fig. 4, in the case that the access address is a hole address, the network-on-chip-based transaction request processing method further includes: step S5-step S6.
And S5, generating request abnormality reminding information.
The abnormal reminding information is used for reminding that the access address in the transaction request is abnormal. The abnormal reminding information comprises information such as an identification of the main equipment, a request identification of a transaction request, an abnormal log and the like.
And S6, sending the request abnormality reminding information to a central processing unit of the chip.
Wherein the chip is the chip where the network on chip is located.
In the embodiment of the invention, the abnormality reminding information can be sent to the central processing unit of the chip in an interrupt mode, so that the central processing unit can timely acquire that the abnormality exists in the access address in the transaction request sent by the main equipment, and the central processing unit can acquire that the abnormality exists in the transaction request without acquiring that the abnormality exists after the transaction request is processed, thereby being capable of maintaining the running stability of the chip.
In one embodiment, in the case that the access address is a hole address, the network-on-chip-based transaction request processing method includes: in the process of converting the transaction request sent by the main device into the corresponding routing packet, the routing packet conversion processing is not executed on the transaction request containing the hole address.
It should be noted that, in general, the network interface unit at the master device side will convert the transaction request sent by the master device into a corresponding routing packet, and transmit the routing packet through the routing network. However, the transaction request including the hole address belongs to invalid information, network bandwidth of the routing network is wasted when the transaction request is transmitted in the routing network, and in the embodiment of the invention, a response function to the transaction request is added in the network interface unit at the main equipment side, so that the transaction request including the hole address can be correspondingly responded without being transmitted through the routing network. Therefore, the network interface unit at the main equipment side can not execute the route packet conversion processing on the transaction request containing the hole address in the process of converting the transaction request sent by the main equipment into the corresponding route packet, and does not generate the route packet corresponding to the transaction request, so that the stable operation of the chip is ensured, the transmission resource of the network on chip occupied by invalid information is reduced, and the waste of the network on chip route bandwidth is effectively avoided.
In another embodiment, in the case that the access address is a hole address, the network-on-chip-based transaction request processing method includes: after converting the transaction request sent by the master device into a corresponding routing packet, the routing packet converted by the transaction request containing the hole address is discarded.
It should be noted that, in general, the network interface unit at the master device side will convert the transaction request sent by the master device into a corresponding routing packet, and transmit the routing packet through the routing network. However, the transaction request including the hole address belongs to invalid information, network bandwidth of the routing network is wasted when the transaction request is transmitted in the routing network, and in the embodiment of the invention, a response function to the transaction request is added in the network interface unit at the main equipment side, so that the transaction request including the hole address can be correspondingly responded without being transmitted through the routing network. Therefore, under the condition that the network interface unit at the main equipment side converts the transaction request into the corresponding routing packet, the routing packet converted by the transaction request containing the hole address is discarded, so that the stable operation of the chip is ensured, the transmission resource of the network-on-chip occupied by invalid information is reduced, and the waste of the network-on-chip routing bandwidth is effectively avoided.
Fig. 5 is a flowchart of a method of transmitting a transaction request to a corresponding slave-side network interface unit over a routing network, according to an embodiment of the present invention. As shown in fig. 5, in the case that the access address is not a hole address, a step of sending the transaction request to the corresponding slave-side network interface unit through the routing network, so that the corresponding slave-side network unit sends the transaction request to the corresponding slave (step S4 above), includes: step S41 to step S43.
Step S41, if the access address is not a hole address, the transaction request is converted into a first routing packet.
The first routing packet is formed by converting a transaction request sent by the master device by the network interface unit at the master device side.
In some embodiments, the transaction request is a request initiated by the master device based on a preset communication protocol, so that the network interface unit at the master device side can perform route packet conversion based on the preset communication protocol, so as to meet the requirement of the communication protocol and improve the running stability of the network on chip.
Step S42, determining the slave device corresponding to the destination address of the access address mapping and the slave device side network interface unit corresponding to the slave device.
The slave device corresponding to the destination address of the access address mapping can be determined based on pre-stored memory address mapping relation information, wherein the memory address mapping relation information is information of mapping relation between a virtual memory address and a physical address in a chip where the network on chip is located.
The network interface unit at the slave device side corresponding to the slave device is a network interface unit with communication connection with the slave device, namely, all information sent to the slave device in the routing network is forwarded to the slave device through the network interface unit at the slave device side.
Step S43, the first routing packet is sent to the corresponding slave device side network interface unit through the routing network, so that the corresponding slave device side network unit converts the first routing packet into the transaction request and sends the transaction request to the slave device.
In the embodiment of the invention, under the condition that the access address is not a hole address, the transaction request is converted into a first routing packet, then the slave device corresponding to the destination address mapped by the access address and the slave device side network interface unit corresponding to the slave device are determined, and finally the first routing packet is sent to the corresponding slave device side network interface unit through the routing network, so that the corresponding slave device side network unit converts the first routing packet into the transaction request, and sends the transaction request to the slave device, thereby realizing the transmission processing of the normal transaction request.
In one embodiment, after the slave-side network element sends the transaction request to the slave, the slave may process the transaction request. The processing process comprises the following steps: executing control information in the transaction request, the control information including one or more of a read request and a write request; and generating second transaction response information based on the execution result, wherein the second transaction response information comprises the execution result. For example, in the case where the control information is a read request, the execution result may be the corresponding read content; in the case where the control information is a write request, the execution result may be information such as whether the writing was successful or not, and the location of the writing.
Fig. 6 is a flow chart of yet another network-on-chip based transaction request processing method according to an embodiment of the present invention. As shown in fig. 6, in the case where the access address is not a hole address, after sending the transaction request to the corresponding slave-side network interface unit through the routing network (step S4 above), the method further includes: step S44 to step S46.
Step S44, receiving a second routing packet from the routing network.
The second routing packet is a routing packet after the slave device side network interface unit converts second transaction response information returned from the slave device.
The second transaction response information is response information generated by the slave device in accordance with the transaction request.
Step S45, converting the second routing packet into second transaction response information.
Step S46, the second transaction response information is sent to the master device.
In the embodiment of the invention, when the access address is not the hole address, the transaction request is sent to the corresponding slave device side network interface unit through the routing network, and then the second routing packet is received from the routing network, wherein the second routing packet is the routing packet obtained by converting the second transaction response information returned from the slave device by the slave device side network interface unit, then the second routing packet is converted into the second transaction response information, and the second transaction response information is sent to the master device, so that the integrity of the transaction process can be realized, and the stable operation of the chip is ensured.
The embodiment also provides a transaction request processing device based on the network on chip, which is used for implementing the above embodiment and the preferred implementation manner, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
Fig. 7 is a transaction request processing device based on a network on chip according to an embodiment of the present invention. The network-on-chip comprises a master device side network interface unit, a slave device side network interface unit and a routing network, and the transaction request processing device is configured in the master device side network interface unit. As shown in fig. 7, the apparatus includes: a receiving module 71, an address discriminating module 72, a backup slave module 73 and a processing module 74.
And the receiving module 71 is configured to receive a transaction request sent by the master device, where the transaction request includes an access address.
The address determining module 72 is configured to determine whether the access address is a hole address, where the hole address is an unused virtual memory address in a virtual memory space of a chip where the network on chip is located.
In one embodiment, the address discriminating module is used for determining whether the access address has a mappable destination address based on the pre-stored memory address mapping relation information; determining that the access address is not a hole address under the condition that the access address has a mappable destination address; in the case where the access address does not have a destination address that can be mapped, it is determined that the access address is a hole address.
The backup slave device module 73 is configured to generate first transaction response information based on the transaction request and send the first transaction response information to the master device in a case where the access address is a hole address.
In one embodiment, the transaction request processing device further comprises an anomaly alert module.
The abnormality reminding module is used for generating request abnormality reminding information and sending the request abnormality reminding information to a central processing unit of the chip under the condition that the access address is a hole address.
In one embodiment, the transaction request processing device further comprises a control module.
The control module is used for not executing route packet conversion processing on the transaction request containing the hole address in the process of converting the transaction request sent by the main equipment into the corresponding route packet; alternatively, after converting the transaction request sent by the master device into a corresponding routing packet, the routing packet converted by the transaction request including the hole address is discarded.
The processing module 74 is configured to send the transaction request to the corresponding slave-side network interface unit through the routing network, where the access address is not a hole address, so that the corresponding slave-side network unit sends the transaction request to the corresponding slave.
In one embodiment, the processing module 74 is configured to translate the transaction request into a first routing packet if the access address is not a hole address; determining a slave device corresponding to a destination address of the access address mapping and a slave device side network interface unit corresponding to the slave device; transmitting the first routing packet to the corresponding slave device side network interface unit through the routing network so that the corresponding slave device side network unit converts the first routing packet into a transaction request and transmits the transaction request to the slave device
In one embodiment, the apparatus further comprises a network receiving module, a converting module, and a transmitting module.
A network receiving module for receiving a second routing packet from the routing network; the second routing packet is a routing packet obtained by converting second transaction response information returned by the slave device through the slave device side network interface unit; the second transaction response information is response information generated by the slave device in accordance with the transaction request.
And the conversion module is used for converting the second routing packet into second transaction response information.
And the sending module is used for sending the second transaction response information to the master device.
The embodiment of the invention provides a transaction request processing device based on a network-on-chip, wherein the network-on-chip comprises a main equipment side network interface unit, a slave equipment side network interface unit and a routing network, and the transaction request processing device is configured in the main equipment side network interface unit; the device comprises: the receiving module is used for receiving a transaction request sent by the main equipment, wherein the transaction request comprises an access address; the address judging module is used for determining whether the access address is a hole address, wherein the hole address is an unused virtual memory address in a virtual memory space of a chip where the network on chip is located; transmitting the transaction request to the corresponding slave device side network interface unit through the routing network under the condition that the access address is not the hole address, so that the corresponding slave device side network unit can transmit the transaction request to the corresponding slave device; the backup slave device module is used for generating first transaction response information based on the transaction request and sending the first transaction response information to the master device under the condition that the access address is a hole address, so that the transaction request containing the hole address can be correspondingly responded without being transmitted through a routing network, transaction integrity can be realized, transmission resources of the network on chip are reduced under the condition that stable operation of the chip is ensured, and waste of network on chip routing bandwidth is effectively avoided.
Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.
The network-on-chip based transaction request processing device in this embodiment is presented in the form of functional units, where the units refer to ASIC (Application Specific Integrated Circuit ) circuits, processors and memories executing one or more software or firmware programs, and/or other devices that can provide the above-described functionality.
The embodiment of the invention also provides computer equipment, which is provided with the transaction request processing device based on the network on chip shown in the figure 7.
Fig. 8 is a schematic structural view of a computer device according to an embodiment of the present invention. As shown in fig. 8, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 8.
The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.
Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform the methods shown in implementing the above embodiments.
The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.
The computer device also includes a communication interface 30 for the computer device to communicate with other devices or communication networks.
The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.
Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.
Claims (8)
1. The network-on-chip based transaction request processing method is characterized in that the network-on-chip comprises a master device side network interface unit, a slave device side network interface unit and a routing network, and the method is applied to the master device side network interface unit; the method comprises the following steps:
receiving a transaction request sent by a main device; the transaction request includes an access address;
determining whether the access address is a hole address; the hole address refers to an unused virtual memory address in a virtual memory space of a chip where the network on chip is located;
generating first transaction response information based on the transaction request and transmitting the first transaction response information to the master device if the access address is a hole address;
if the access address is not a hole address, the transaction request is sent to a corresponding slave device side network interface unit through the routing network, so that the corresponding slave device side network unit can send the transaction request to the corresponding slave device;
The determining whether the access address is a hole address includes:
determining whether a target address capable of being mapped exists in the access address or not based on pre-stored memory address mapping relation information; the memory address mapping relation information is information containing the mapping relation between a virtual memory address and a physical address in a chip where the network on chip is located, and the destination address is the physical address of the slave device indicated by the access address;
determining that the access address is not a hole address in the case that the access address has a mappable destination address; determining that the access address is a hole address when the access address does not have a mappable destination address;
in the case where the access address is a hole address, the method further includes:
in the process of converting the transaction request sent by the main equipment into a corresponding routing packet, not executing routing packet conversion processing on the transaction request containing the hole address;
or after converting the transaction request sent by the master device into a corresponding routing packet, discarding the routing packet converted by the transaction request containing the hole address.
2. The method of claim 1, wherein in the event that the access address is a hole address, the method further comprises:
Generating abnormal reminding information of the request;
and sending the request abnormality reminding information to a central processing unit of the chip.
3. The method according to claim 1, wherein said sending the transaction request to the corresponding slave-side network interface unit via the routing network for the corresponding slave-side network unit to send the transaction request to the corresponding slave device if the access address is not a hole address, comprises:
converting the transaction request into a first routing packet if the access address is not a hole address;
determining a slave device corresponding to the destination address of the access address mapping and a slave device side network interface unit corresponding to the slave device;
and sending the first routing packet to the corresponding slave device side network interface unit through the routing network, so that the corresponding slave device side network unit converts the first routing packet into the transaction request and sends the transaction request to the slave device.
4. A method according to claim 3, wherein, in the case where the access address is not a hole address, after the transaction request is sent to the corresponding slave-side network interface unit through the routing network, further comprising:
Receiving a second routing packet from the routing network; the second routing packet is a routing packet after the slave device side network interface unit converts second transaction response information returned by the slave device; the second transaction response information is response information generated by the slave device according to the transaction request;
converting the second routing packet into second transaction response information;
and sending the second transaction response information to the master device.
5. The method of any of claims 1-4, wherein the transaction request is a request initiated by the master device based on a preset communication protocol, the transaction request further comprising one or more of a read request and a write request.
6. The network-on-chip-based transaction request processing device is characterized by comprising a master device side network interface unit, a slave device side network interface unit and a routing network, wherein the transaction request processing device is configured in the master device side network interface unit; the device comprises:
the receiving module is used for receiving a transaction request sent by the main equipment; the transaction request includes an access address;
the address judging module is used for determining whether the access address is a hole address or not; the hole address refers to an unused virtual memory address in a virtual memory space of a chip where the network on chip is located;
A backup slave device module, configured to generate first transaction response information based on the transaction request and send the first transaction response information to the master device if the access address is a hole address;
the processing module is used for sending the transaction request to the corresponding slave device side network interface unit through the routing network when the access address is not the hole address, so that the corresponding slave device side network unit can send the transaction request to the corresponding slave device;
the address judging module is used for determining whether the access address has a mappable destination address or not based on pre-stored memory address mapping relation information; the memory address mapping relation information is information containing the mapping relation between a virtual memory address and a physical address in a chip where the network on chip is located, and the destination address is the physical address of the slave device indicated by the access address;
determining that the access address is not a hole address in the case that the access address has a mappable destination address; determining that the access address is a hole address when the access address does not have a mappable destination address;
In the case where the access address is a hole address, the apparatus further includes:
in the process of converting the transaction request sent by the main equipment into a corresponding routing packet, not executing routing packet conversion processing on the transaction request containing the hole address;
or after converting the transaction request sent by the master device into a corresponding routing packet, discarding the routing packet converted by the transaction request containing the hole address.
7. A computer device, comprising:
a memory and a processor in communication with each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the network-on-chip based transaction request processing method of any of claims 1 to 5.
8. A computer-readable storage medium having stored thereon computer instructions for causing a computer to perform the network-on-chip-based transaction request processing method of any one of claims 1 to 5.
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