CN111834325A - Chip packaging structure and manufacturing method thereof - Google Patents
Chip packaging structure and manufacturing method thereof Download PDFInfo
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- CN111834325A CN111834325A CN201910514572.4A CN201910514572A CN111834325A CN 111834325 A CN111834325 A CN 111834325A CN 201910514572 A CN201910514572 A CN 201910514572A CN 111834325 A CN111834325 A CN 111834325A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 26
- 238000007789 sealing Methods 0.000 claims abstract description 25
- 230000000149 penetrating effect Effects 0.000 claims abstract description 15
- 238000005553 drilling Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 8
- 229920000620 organic polymer Polymers 0.000 claims description 7
- 238000005538 encapsulation Methods 0.000 claims description 6
- 238000009832 plasma treatment Methods 0.000 claims description 5
- 239000008393 encapsulating agent Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 67
- 238000000465 moulding Methods 0.000 description 13
- 150000001875 compounds Chemical class 0.000 description 7
- 239000004020 conductor Substances 0.000 description 6
- 238000002161 passivation Methods 0.000 description 6
- LIMFPAAAIVQRRD-BCGVJQADSA-N N-[2-[(3S,4R)-3-fluoro-4-methoxypiperidin-1-yl]pyrimidin-4-yl]-8-[(2R,3S)-2-methyl-3-(methylsulfonylmethyl)azetidin-1-yl]-5-propan-2-ylisoquinolin-3-amine Chemical compound F[C@H]1CN(CC[C@H]1OC)C1=NC=CC(=N1)NC=1N=CC2=C(C=CC(=C2C=1)C(C)C)N1[C@@H]([C@H](C1)CS(=O)(=O)C)C LIMFPAAAIVQRRD-BCGVJQADSA-N 0.000 description 5
- 239000012790 adhesive layer Substances 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 238000007788 roughening Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides a chip packaging structure which comprises a first chip, a second chip, a first mold packaging body, a plurality of first through mold guide holes, a plurality of second through mold guide holes and a first circuit layer. The second chip is stacked on the first chip. The first mold package covers the first chip and the second chip. The first through mold via is located in the first mold package and electrically connected to the first chip. The second die through guide hole is positioned in the first die seal body and is electrically connected to the second chip. The first circuit layer is arranged on the first mold sealing body and is electrically connected with the first mold through guide hole and the second mold through guide hole. A first interval is formed among the first die penetrating guide holes. And a second interval is formed among the second die penetrating guide holes. The first pitch is greater than the second pitch. A method for manufacturing the chip package structure is also provided.
Description
Technical Field
The present disclosure relates to electronic devices, and particularly to a chip package structure and a method for manufacturing the same.
Background
In the fabrication of electronic devices such as Panel Level Packaging (PLP) or Wafer Level Packaging (WLP), the masks used for photolithography are expensive.
Disclosure of Invention
The invention provides a chip packaging structure and a manufacturing method thereof, wherein the manufacturing method is simple and low in cost.
The chip packaging structure comprises a first chip, a second chip, a first mold packaging body, a plurality of first mold through guide holes, a plurality of second mold through guide holes and a first circuit layer. The second chip is stacked on the first chip. The first mold package covers the first chip and the second chip. The first through mold via is located in the first mold package and electrically connected to the first chip. The second die through guide hole is positioned in the first die seal body and is electrically connected to the second chip. The first circuit layer is arranged on the first mold sealing body and is electrically connected with the first mold through guide hole and the second mold through guide hole. A first interval is formed among the first die penetrating guide holes. And a second interval is formed among the second die penetrating guide holes. The first pitch is greater than the second pitch.
The manufacturing method of the chip packaging structure comprises the following steps. A carrier plate is provided. A first chip is disposed on the carrier. The second chip is configured on the first chip. And forming a first mold sealing body on the carrier plate, wherein the first mold sealing body covers the first chip and the second chip. A plurality of first through mold vias are formed in the first mold package and electrically connected to the first chip. And forming a plurality of second die through guide holes in the first die encapsulation body, wherein the plurality of second die through guide holes are electrically connected to the second chip. And forming a first circuit layer on the first mold sealing body, wherein the first circuit layer is electrically connected to the first mold through holes and the second mold through holes. After the first circuit layer is formed, the carrier plate is removed.
In view of the above, in the chip package structure, the chip and the circuit layer are separated from each other by the mold package body, and the chip and the circuit layer are electrically connected to each other by the through-mold via. Therefore, the manufacturing method of the chip packaging structure is simple and low in cost.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A to 1J are schematic side views illustrating a method for manufacturing a portion of a chip package structure according to an embodiment of the invention.
Fig. 2A and 2B are schematic partial top views illustrating a method for manufacturing a chip package structure according to an embodiment of the invention.
[ notation ] to show
100: chip packaging structure
110: first chip
111: first connecting pad
112: protective layer
110 a: a first active surface
110 b: first back surface
110 s: first side wall
120: second chip
121: second connecting pad
122: protective layer
120 a: second active surface
120 b: second back surface
120 s: second side wall
130: first mold package
130 a: the top surface
131: first die penetration opening
131 s: first inner wall
132: second die opening
132 s: second inner wall
141: first die-through guide hole
141 a: first top end
141 b: first bottom end
141 d: first aperture
141 h: first height
142: second die-through guide hole
142 a: second top end
142 b: second bottom end
142 d: second aperture
142 h: second height
145: first circuit layer
150: second mold package
150 a: the top surface
151: third die opening
151 s: third inner wall
161: third die-through guide hole
165: second circuit layer
170: third mold package
181: fourth die-through guide hole
185: third circuit layer
190: conductive terminal
10: support plate
11: release layer
12: adhesive layer
13. 14: ion plasma
P1: first interval
P2: second pitch
Detailed Description
Directional phrases used herein (e.g., upper, lower, right, left, front, rear, top, bottom) are used only as referring to the drawings and are not intended to imply absolute orientation.
Unless expressly stated otherwise, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a specific order.
The present invention will be described more fully with reference to the accompanying drawings of the present embodiments. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The thickness, dimensions, or dimensions of layers, elements, or regions in the figures may be exaggerated for clarity. The same or similar reference symbols denote the same or similar layers, elements or regions, and the following paragraphs will not be repeated.
Fig. 1A to 1J are schematic side views illustrating a method for manufacturing a portion of a chip package structure according to an embodiment of the invention. Fig. 2A and 2B are schematic partial top views illustrating a method for manufacturing a chip package structure according to an embodiment of the invention. Fig. 2A may be a partial top view schematic diagram of the structure of fig. 1A. Fig. 2B may be a partial top view schematic diagram of the structure of fig. 1E. For clarity, some of the layers or members are not shown in fig. 1A to 1J and fig. 2A and 2B. For example, the first circuit layer 145 is omitted from fig. 2B.
Referring to fig. 1A and fig. 2A, a carrier 10 is provided. The carrier 10 may be made of glass, wafer substrate, metal or other suitable materials, as long as the materials can support the structures or components formed thereon in the subsequent process.
In this embodiment, the carrier 10 may have a release layer 11 thereon. The release layer 11 may be a Light To Heat Conversion (LTHC) adhesive layer, but the present invention is not limited thereto.
Referring to fig. 1A and fig. 2A, the first chip 110 is disposed on the carrier 10. The first chip 110 may have a first active surface 110a, a first back surface 110b opposite to the first active surface 110a, and a first sidewall 110s connected to the first active surface 110a and the first back surface 110 b. The first chip 110 may include a passivation layer (passivation layer)112 and a plurality of first connection pads 111. The passivation layer 112 is disposed on the first active surface 110a, and the first connecting pad 111 is exposed from the passivation layer 112.
With reference to fig. 1A and fig. 2A, the second chip 120 is disposed on the first chip 110. The second chip 120 may have a second active surface 120a, a second back surface 120b opposite to the second active surface 120a, and a second sidewall 120s connected to the second active surface 120a and the second back surface 120 b. The second chip 120 may include a protection layer 122 and a plurality of second connection pads 121. The passivation layer 122 is disposed on the second active surface 120a, and the passivation layer 122 exposes the second connecting pad 121. After the second chip 120 is disposed on the first chip 110, the first connection pads 111 of the first chip 110 do not overlap the second chip 120.
In the present embodiment, the size of the first chip 110 is larger than that of the second chip 120, but the present invention is not limited thereto. In an embodiment not shown, the size of the first chip 110 may be equal to the size of the second chip 120, and the first chip 110 and the second chip 120 may be stacked alternately. For example, the second chip 120 may be stacked on the first chip 110 by rotating 90 degrees. As such, the cross-sectional area of the first chip 110 may be different from the cross-sectional area of the second chip 120 in a side view direction (e.g., the direction shown in FIG. 1A).
The first chip 110 and the second chip 120 may be homogeneous chips or heterogeneous chips, which is not limited in the present invention. For example, the first chip 110 and the second chip 120 may be the same or similar logic chips. For another example, one of the first chip 110 and the second chip 120 may be a logic chip, and the other of the first chip 110 and the second chip 120 may be a memory chip.
In the embodiment, the first pitch P1 is between the adjacent first connection pads 111, the second pitch P2 is between the adjacent second connection pads 121, and the first pitch P1 is greater than the second pitch P2, but the invention is not limited thereto. Thus, the process window (process window) can be improved in the subsequent steps.
In the present embodiment, the first chip 110 and the second chip 120 may have an adhesive layer 12 therebetween. The adhesive layer 12 is, for example, a Die Attached Film (DAF), but the present invention is not limited thereto.
It should be noted that the sequence of disposing the first chip 110 on the carrier 10 and disposing the second chip 120 on the first chip 110 is not limited in the present invention. In an embodiment, the first chip 110 may be disposed on the carrier 10, and then the second chip 120 may be disposed on the first chip 110 on the carrier 10. In another embodiment, the first chip 110 and the second chip 120 having a stacked type may be disposed on the carrier 10 after the second chip 120 is disposed on the first chip 110.
Referring to fig. 1B, a first mold package 130 is formed on the carrier 10, and the first mold package 130 covers the first chip 110 and the second chip 120.
For example, the first mold sealing body 130 is formed by molding process or other suitable method to form an uncured organic polymer (e.g., molding compound) on the carrier 10. Then, the uncured organic polymer is cured, and the first mold sealing body 130 may be formed.
In the present embodiment, the first molding compound 130 covers the first active surface 110a and the first sidewall 110s of the first chip 110, and the first molding compound 130 covers the second active surface 120a and the second sidewall 120s of the second chip 120. In other words, in this step, the first chip 110 and the second chip 120 are not exposed, and the first chip 110 and the second chip 120 can be fixed by the first mold package 130 on the carrier 10.
Referring to fig. 1C, a plurality of first mold through openings 131 and a plurality of second mold through openings 132 are formed in the first mold sealing body 130 by drilling. The through-mold openings (e.g., the first through-mold opening 131 and the second through-mold opening 132) are formed by drilling, which is simpler and less expensive than photolithography. In addition, the forming sequence of the first die through opening 131 and the second die through opening 132 is not limited in the present invention.
In the embodiment, the first through mold openings 131 expose the corresponding first connection pads 111 of the first chip 110, and the second through mold openings 132 expose the corresponding second connection pads 121 of the second chip 120. That is, compared to the mechanical drilling method, the laser drilling method can reduce the possibility of damage to the first bonding pads 111 of the first chip 110 and the second bonding pads 121 of the second chip 120.
Referring to fig. 1D, in the present embodiment, a plasma treatment (plasma) may be performed on the first mold sealing body 130. The plasma treatment may be a surface modification (surface modification) or a surface roughening (surface roughening) performed on the surface of the first mold seal 130 (e.g., the top surface 130a of the first mold seal 130, the first inner wall 131s of the first through-mold opening 131, and/or the second inner wall 132s of the second through-mold opening 132) by the plasma 13, so as to improve the adhesion between the first mold seal 130 and a film layer (e.g., the first through-mold via 141 and the second through-mold via 142, shown in fig. 1E) or a film layer (e.g., the first line layer 145, shown in fig. 1E) subsequently formed in the first mold seal 130, and reduce the possibility of peeling (peeling) of the film layer formed in or on the first mold seal 130. On the other hand, the plasma treatment performed on the first through-mold opening 131 and the second through-mold opening 132 can also reduce the amount of the smear (smear) that may remain in the first through-mold opening 131 and the second through-mold opening 132, so as to improve the electrical conductivity between the conductive film layer (e.g., the first through-mold via 141 and the second through-mold via 142, shown in fig. 1E) and the chip connection pads (e.g., the first connection pad 111 of the first chip 110 and/or the second connection pad 121 of the second chip 120) formed in the first mold package 130.
Referring to fig. 1E, a first through mold via 141 is formed in the first through mold opening 131, a second through mold via 142 is formed in the second through mold opening 132, and a first circuit layer 145 is formed on the first mold package 130, wherein the first circuit layer 145 is electrically connected to the first through mold vias 141 and the second through mold vias 142.
For example, the conductive material may be formed on the first mold sealing body 130 through a deposition process and/or an electroplating process. In addition, the conductive material may further fill the first through mold opening 131 and the second through mold opening 132 to form a first through mold via 141 electrically connected to the first connection pad 111 and a second through mold via 142 electrically connected to the second connection pad 121. Subsequently, the conductive material covering the surface of the first mold sealing body 130 may be patterned through, for example, photolithography and etching processes to form the first circuit layer 145. In addition, the conductive material may include a metal in consideration of conductivity, but the invention is not limited thereto. The conductive material may be a single layer structure or a multi-layer structure, for example, a seed layer (seed layer) and a plating layer, but the invention is not limited thereto.
Referring to fig. 1E and fig. 2B, in a top view, the first through via 141 may be disposed in a manner similar to that of the first connection pad 111, and the second through via 142 may be disposed in a manner similar to that of the second connection pad 121. That is, adjacent first through-mold vias 141 (with reference to the center of each first through-mold via 141) may have a first pitch P1 therebetween, adjacent second through-mold vias 142 (with reference to the center of each second through-mold via 142) may have a second pitch P2 therebetween, and the first pitch P1 is greater than the second pitch P2.
With continued reference to fig. 1E and fig. 2B, the shape (shape) of the first through-mold via 141 may substantially correspond to the first through-mold opening 131, and the shape of the second through-mold via 142 may substantially correspond to the second through-mold opening 132. That is, the first through mold via 141 has a first top end 141a far from the first chip 110 and a first bottom end 141b near the first chip 110, the second through mold via 142 has a second top end 142a far from the second chip 120 and a second bottom end 142b near the second chip 120, the first top end 141a has a first aperture 141d, the second top end 142a has a second aperture 142d, and the first aperture 141d may be substantially larger than the second aperture 142d, but the invention is not limited thereto. In an embodiment not shown, the first aperture (similar to the first aperture 141d described above) may be substantially equal to the second aperture (similar to the second aperture 142d described above).
Referring to fig. 1F, in the present embodiment, after the first circuit layer 145 is formed, the second mold package body 150 may be formed on the first mold package body 130, and the second mold package body 150 covers the first circuit layer 145.
In an embodiment, the second molding compound 150 may be made of the same or similar material or forming manner as the first molding compound 130, but the invention is not limited thereto. In another embodiment, the material of the second molding compound 150 may include an organic polymer, and may be formed by a lamination process (lamination process), a coating process, or other suitable methods.
Referring to fig. 1G, in the present embodiment, a plurality of third through mold openings 151 may be formed in the second mold package body 150 by drilling, and the first circuit layer 145 is exposed by the plurality of third through mold openings 151. The third through mold opening 151 may be formed in the same or similar manner as the first through mold opening 131 or the second through mold opening 132, and therefore, the description thereof is omitted.
Referring to fig. 1G, in the present embodiment, the surface of the second mold sealing body 150 (e.g., the top surface 150a of the second mold sealing body 150 and/or the third inner wall 151s of the third through mold opening 151) may be plasma-treated by the ion plasma 14, but the invention is not limited thereto.
Referring to fig. 1H, in the present embodiment, a plurality of third through mold vias 161 are formed in the plurality of third through mold openings 151, a second circuit layer 165 is formed on the second mold package body 150, the plurality of third through mold vias 161 are electrically connected to the first circuit layer 145, and the second circuit layer 165 is electrically connected to the plurality of third through mold vias 161.
The third tsv 161 may be formed in the same or similar manner as the first tsv 141 or the second tsv 142, and the second circuit layer 165 may be formed in the same or similar manner as the first circuit layer 145, so that the description thereof is omitted.
In an embodiment not shown, the steps of forming the second mold sealing body 150, forming the plurality of third through mold openings 151, forming the third through mold vias 161 and the second circuit layer 165 may be sequentially repeated a plurality of times.
Referring to fig. 1I, in the present embodiment, after the second circuit layer 165 is formed, a third mold package 170 may be formed on the second mold package 150, and the third mold package 170 covers the second circuit layer 165. The third molding compound 170 may be made of the same or similar materials or forming methods as the second molding compound 150, and therefore, the description thereof is omitted.
Referring to fig. 1I, in the present embodiment, a plurality of fourth through mold vias 181 may be formed in the third mold package 170, a third circuit layer 185 is formed on the third mold package 170, the plurality of fourth through mold vias 181 are electrically connected to the second circuit layer 165, and the third circuit layer 185 is electrically connected to the plurality of fourth through mold vias 181. The fourth tsv 181 may be formed in the same or similar manner as the third tsv 161, and the third circuit layer 185 may be formed in the same or similar manner as the second circuit layer 165, which is not described herein again.
Referring to fig. 1J, after the above steps are completed (e.g., after the first circuit layer 145 is formed, or after the first circuit layer 145 and the second circuit layer 165 (if any) are formed, or after the first circuit layer 145, the second circuit layer 165 (if any) and the third circuit layer 185 (if any) are formed), the carrier 10 may be removed. In this way, the first encapsulant 130 may expose the first back surface 110b of the first chip 110.
Referring to fig. 1J, in the present embodiment, a plurality of conductive terminals 190 may be disposed on the third through via 161 and the third circuit. The conductive terminal 190 may be a conductive pillar (conductive pillar), a solder ball (solder ball), a conductive bump (conductive bump), or a conductive structure with other forms or shapes. Conductive terminals 190 may be formed by electroplating, deposition, ball placement, reflow, and/or other suitable processes.
In one embodiment, the fourth through mold via 181 and the third circuit layer 185 located between the conductive terminal 190 and the third mold package 170 may be referred to as under-bump-metallurgy (UBM).
Referring to fig. 1J, in the present embodiment, a dicing process or a singulation process may be performed to cut through the first mold package 130, the second mold package 150 (if any), and/or the third mold package 170 (if any) to form a plurality of chip package structures 100.
It should be noted that the present invention does not limit the sequence of removing the carrier 10, disposing the plurality of conductive terminals 190 (if any), and performing the cutting process or the singulation process (if any).
The fabrication of the chip package structure 100 of the present embodiment can be substantially completed through the above steps.
Referring to fig. 1J, the chip package structure 100 includes a first chip 110, a second chip 120, a first mold package 130, a plurality of first through mold vias 141, a plurality of second through mold vias 142, and a first circuit layer 145. The second chip 120 is stacked on the first chip 110. The first encapsulant 130 covers the first chip 110 and the second chip 120. The first through mold via 141 is located in the first mold sealing body 130 and electrically connected to the first chip 110. The second through-mold via 142 is located in the first mold package 130 and electrically connected to the second chip 120. The first circuit layer 145 is disposed on the first mold package body 130 and electrically connected to the first through-mold via 141 and the second through-mold via 142. The first plurality of feed-through holes 141 have a first pitch P1 (shown in fig. 2B). A second pitch P2 (shown in fig. 2B) exists between the second plurality of feed-through holes 142. The first pitch P1 is greater than the second pitch P2.
In the present embodiment, the first molding compound 130 covers the first active surface 110a and the first sidewall 110s of the first chip 110 and the second active surface 120a and the second sidewall 120s of the second chip 120.
In the present embodiment, the first encapsulant 130 exposes the first back surface 110b of the first chip 110. As a result, the heat dissipation capability can be improved when the chip package structure 100 is in operation.
In this embodiment, the first through via 141 can be formed by drilling the first mold package 130 and then filling the first through via with a conductive material. In this way, the first through via 141 can have a larger aspect ratio (i.e., the ratio of the first height 141h divided by the first aperture 141d), and can be suitable for stacked chip packages. In an embodiment, an aspect ratio (aspect ratio) of the first through via 141 may be greater than 2, but the present invention is not limited thereto.
In the present embodiment, the first height 141h of the first guiding hole 141 is greater than the second height 142h of the second guiding hole 142, and the first aperture 141d (shown in fig. 2B) of the first guiding hole 141 is greater than the second aperture 142d (shown in fig. 2B) of the second guiding hole 142.
In this embodiment, the chip package structure 100 may further include a second mold package body 150, a plurality of third through mold vias 161, and a second circuit layer 165. The second molding compound 150 is disposed on the first molding compound 130 and covers the first circuit layer 145. The third through-mold via 161 is disposed in the second mold package body 150 and electrically connected to the first circuit layer 145. The second circuit layer 165 is disposed on the second mold sealing body 150 and electrically connected to the plurality of third through mold vias 161. The material of the second molding compound 150 includes organic polymer.
In summary, in the chip package structure of the present invention, the chip and the circuit layer are separated from each other by the mold package body, and the chip and the circuit layer are electrically connected to each other by the through-mold via. Therefore, the manufacturing method of the chip packaging structure is simple and low in cost.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (10)
1. A chip package structure, comprising:
a first chip;
a second chip stacked on the first chip;
a first mold sealing body covering the first chip and the second chip;
a plurality of first die through vias in the first die package and electrically connected to the first chip;
a plurality of second die through vias located in the first die encapsulation and electrically connected to the second chip; and
a first circuit layer on the first mold sealing body and electrically connected to the first through mold vias and the second through mold vias, wherein:
a first interval is formed among the first die penetrating guide holes;
a second interval is formed among the second die penetrating guide holes; and is
The first pitch is greater than the second pitch.
2. The chip packaging structure according to claim 1, wherein:
each first die-penetrating guide hole is provided with a first top end and a first bottom end which are opposite to each other;
the first top end is far away from the first chip than the first bottom end;
the first tip has a first aperture;
each second die penetrating guide hole is provided with a second top end and a second bottom end which are opposite to each other;
the second top end is far away from the second chip than the second bottom end;
the second tip has a second aperture; and is
The first aperture is larger than the second aperture.
3. The chip packaging structure according to claim 1, wherein:
the first mold sealing body covers the active surface and the side wall of the first chip; and is
The first mold package covers the active surface and the side wall of the second chip.
4. The chip packaging structure according to claim 1, wherein the first mold package exposes a back surface of the first chip.
5. The chip package structure of claim 1, wherein an aspect ratio of the plurality of first through mold vias is greater than 2.
6. The chip packaging structure of claim 1, further comprising:
the second mold sealing body is positioned on the first mold sealing body and covers the first circuit layer;
a plurality of third through mold vias located in the second mold package and electrically connected to the first circuit layer; and
a second circuit layer located on the second mold sealing body and electrically connected to the third through mold guide holes, wherein:
the material of the second mold sealing body comprises organic polymer.
7. A manufacturing method of a chip packaging structure comprises the following steps:
providing a carrier plate;
configuring a first chip on the carrier plate;
configuring a second chip on the first chip;
forming a first mold package body on the carrier plate, wherein the first mold package body covers the first chip and the second chip;
forming a plurality of first die through vias in the first die encapsulation, wherein the plurality of first die through vias are electrically connected to the first chip;
forming a plurality of second die through vias in the first die encapsulation, wherein the plurality of second die through vias are electrically connected to the second chip;
forming a first circuit layer on the first mold sealing body, wherein the first circuit layer is electrically connected to the first mold through vias and the second mold through vias; and
and removing the carrier plate after the first circuit layer is formed.
8. The method of claim 7, wherein the first encapsulant body comprises an organic polymer, and the step of forming the first and second through mold vias comprises:
forming a plurality of first die through openings in the first die encapsulation in a drilling mode, wherein the first die through openings expose the first chip;
forming a plurality of second die through openings in the first die package in a drilling mode, wherein the second die through openings expose the second chip;
performing plasma treatment on the first die penetrating openings and the second die penetrating openings;
forming a plurality of first die penetrating guide holes in the plurality of first die penetrating openings; and
and forming a plurality of second die penetrating guide holes in the plurality of second die penetrating openings.
9. The method of manufacturing a chip package structure according to claim 7, further comprising:
forming a second mold package on the first mold package, wherein the second mold package covers the first circuit layer;
forming a plurality of third die through guide holes in the second die encapsulation body, wherein the plurality of third die through guide holes are electrically connected to the first circuit layer; and
forming a second circuit layer on the second mold sealing body, and electrically connecting the second circuit layer to the third through mold vias, wherein:
the step of removing the carrier plate is after the second circuit layer is formed.
10. The method for manufacturing a chip package structure according to claim 9, wherein the material of the second mold package body comprises an organic polymer, and the step of forming the plurality of third through mold vias comprises:
forming a plurality of third die through openings in the second die seal body in a drilling mode, wherein the first circuit layer is exposed out of the third die through openings;
performing plasma treatment on the third through-mold openings; and
and forming a plurality of third die penetrating guide holes in the plurality of third die penetrating openings.
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| Application Number | Priority Date | Filing Date | Title |
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| TW108113478A TWI697080B (en) | 2019-04-17 | 2019-04-17 | Chip package structure and manufacturing method thereof |
| TW108113478 | 2019-04-17 |
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| CN111834325A true CN111834325A (en) | 2020-10-27 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106960800A (en) * | 2016-01-11 | 2017-07-18 | 美光科技公司 | Package on package component and the method for making semiconductor devices |
| CN106981475A (en) * | 2016-01-19 | 2017-07-25 | 台湾积体电路制造股份有限公司 | Device, the semiconductor devices of encapsulation and semiconductor packages method |
| TWI638439B (en) * | 2017-04-17 | 2018-10-11 | 力成科技股份有限公司 | Semiconductor package structure and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US10026716B2 (en) * | 2016-04-15 | 2018-07-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC formation with dies bonded to formed RDLs |
| US11417569B2 (en) * | 2017-09-18 | 2022-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure having integrated circuit component with conductive terminals of different dimensions |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106960800A (en) * | 2016-01-11 | 2017-07-18 | 美光科技公司 | Package on package component and the method for making semiconductor devices |
| CN106981475A (en) * | 2016-01-19 | 2017-07-25 | 台湾积体电路制造股份有限公司 | Device, the semiconductor devices of encapsulation and semiconductor packages method |
| TWI638439B (en) * | 2017-04-17 | 2018-10-11 | 力成科技股份有限公司 | Semiconductor package structure and manufacturing method thereof |
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| TWI697080B (en) | 2020-06-21 |
| TW202040766A (en) | 2020-11-01 |
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