CN111829800A

CN111829800A - System function testing device

Info

Publication number: CN111829800A
Application number: CN201910331230.9A
Authority: CN
Inventors: 张顺凯; 黄彦舜; 郑君伍
Original assignee: Hiwin Technologies Corp
Current assignee: Hiwin Technologies Corp
Priority date: 2019-04-23
Filing date: 2019-04-23
Publication date: 2020-10-27
Anticipated expiration: 2039-04-23
Also published as: CN111829800B

Abstract

The system function testing device comprises a first timer, a second timer and a processor. The second timer is coupled to the first timer. The processor is coupled to the first timer and the second timer, and receives the system signal. The first timer and the second timer establish a power-on and power-off test time sequence. In the power-on and power-off test time sequence, and when the system signal comprises error information, the processor locks the state of the first timer and stops the power-on and power-off test time sequence.

Description

System function testing device

Technical Field

The present invention relates to mechanical equipment, and is especially one kind of system function testing device for mechanical equipment.

Background

Before leaving the factory, the mechanical system (equipment) is strictly subjected to function test to verify whether various functions are normal, and the system functions can be effectively tested by executing the startup operation and shutdown operation of the mechanical system. Conventionally, in the test of the power-on operation and the power-off operation, the operator repeatedly executes the power-on function and the power-off function to the mechanical system, so that not only is labor and time consumed, but also the reason for the error cannot be efficiently kept, and therefore, after the error occurs, the operator needs to check the whole mechanical system in detail, and the efficiency of error elimination is poor.

Although the current test is performed by hardware, software or a combination of both, the test of the power-on operation and the power-off operation cannot be stopped at a proper time when an error occurs, and therefore, the current technology cannot retain the cause of the error and cannot efficiently eliminate the error.

Disclosure of Invention

In view of the above disadvantages, the system function testing apparatus of the present invention can timely stop the testing of the power-on operation and the power-off operation when the system has an error state, so as to retain the cause of the error, which is beneficial to eliminating the error.

In order to achieve the above object, the system function testing device of the present invention includes a first timer, a second timer and a processor. The second timer is coupled to the first timer. The processor is coupled to the first timer and the second timer, and receives the system signal. The first timer and the second timer establish a power-on and power-off test time sequence. In the power-on and power-off test time sequence, and when the system signal comprises error information, the processor locks the state of the first timer and stops the power-on and power-off test time sequence.

Therefore, the function of the system (such as a mechanical operation system) can be effectively tested through the startup and shutdown test timing sequence, so as to verify whether the function of the system is normal or not. Moreover, when the system signal of the system has error information, the system function testing device of the invention can lock the error state through the processor to reserve the error state of the system, therefore, the system function testing device of the invention can effectively eliminate the error.

The present invention will be described in detail with reference to the following embodiments, which are provided to illustrate the components, features, circuits and methods of the system function test apparatus. However, it will be understood by those skilled in the art that the detailed description and specific examples, while indicating the specific embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.

Drawings

FIG. 1 is a block diagram of a system for testing system function of the present invention;

FIG. 2 is a circuit diagram of the system function test apparatus of the present invention of FIG. 1;

FIG. 3 is a timing diagram of the system function test apparatus of FIG. 1 without error information in system signals;

FIG. 4 is a timing diagram illustrating the system function testing apparatus of FIG. 1 when the system signal has error information.

Description of the symbols:

100 system function testing device 110 first timer 111 power switching unit

113 first timing selection unit 115 output unit 130 second timer

131 charging unit 133 second timing selection unit 150 processor

300 system 310 power supply 330 system power supply

S_U1First output signal S_U2Second output signal S_sSystem signal

R1 first resistor R2 second resistor R3 third resistor

R4 fourth resistor R5 fifth resistor R6 sixth resistor

R7 seventh resistor R8 eighth resistor R9 ninth resistor

R10 tenth resistor R11 eleventh resistor R12 twelfth resistor

Q1 first transistor Q2 second transistor Q3 third transistor

Q4 fourth transistor Q5 fifth transistor Q6 sixth transistor

Q7 seventh transistor Q8 eighth transistor Q9 ninth transistor

Q10 tenth transistor C1 first capacitor C2 second capacitor

U1 first comparator U2 second comparator D1 first diode

D2 second diode SW Power switch SS1 first selection switch

SS2 second selection switch Vcc power supply

ERR error information T_ONBoot time T_OFFTime of shutdown

Detailed Description

The technical features and effects of the system function testing device of the present invention will be described below with reference to the accompanying drawings. However, the operation, composition and circuit of the system function test apparatus in each drawing are only for illustrating the technical features of the present invention, and the present invention is not limited thereto.

Referring to fig. 1, fig. 1 is a block diagram of a system function testing device according to the present invention connected to a power supply and a system. The function test is to test the system for power-on operation and power-off operation. The booting operation is the operation performed by the system 300, including power generation, data initialization, and system loading. The shutdown operation is the operation performed by the system 300, including starting the shutdown process, storing data, and sequentially shutting down the power supply. The system 300 may be an operation of an automated device, robotic arm, or other mechanical operation.

The system function testing apparatus 100 verifies the function of the system 300 through the power-on and power-off operations to ensure the quality of the system 300. The system function testing device 100 includes a first timer 110, a second timer 130, and a processor 150. The second timer 130 is coupled to the first timer 110. The processor 150 is coupled to the first timer 110 and the second timer 130.

The first timer 110 and the second timer 130 establish a power-on and power-off test timing sequence, so that the system 300 performs a test of continuous power-on and power-off operations according to the power-on and power-off test timing sequence.

The first timer 110 includes a power switching unit 111, a first timing selecting unit 113, and an output unit 115. The power switching unit 111 is connected to the first timing selection unit 113 and a system power path, which is a line connecting the power source 310 to the system power supply 330. The input terminal of the output unit 115 is connected to the first timing selection unit 113, the output terminal of the output unit 115 is connected to the power switching unit 111 and the second timer 130, the output unit 115 is charged by the first timing selection unit 113, and outputs the first output signal S according to the charging status of the first timing selection unit 113_U1To control the operation of the power switching unit 111 and the second timer 130. The operation of the power switching unit 111 includes turning on and off. At the outputWhen the unit 115 controls the power switching unit 111 to be turned on, the power of the power source 310 may be supplied to the system power supply 330, and when the output unit 115 controls the power switching unit 111 to be turned off, the power of the power source 310 may not be supplied to the system power supply 330.

The second timer 130 receives the first output signal S_U1And according to the first output signal S_U1And (6) operating. The second timer 130 outputs a second output signal S_U2。

The processor 150 receives the second output signal S_U2And a system signal S_S. Under normal conditions, in the test time sequence of power-on and power-off, and the system signal S_SWhen there is no error information, the processor 150 continuously performs the test of the power-on operation and the power-off operation according to the power-on and power-off test timing sequence. In case of abnormality, in the test time sequence of power-on and power-off, and system signal S_SWhen there is an error message, the processor 150 locks the operation status of the first timer 110, i.e. interrupts the test timing, to reserve an error status for checking the reason of the error occurrence of the system 300.

The reasons for the error message of the system 300 in the power-on state include that the system power is not normally started, the initialization of the system data fails (e.g., power timing, noise interference, power glitch, software design, etc. errors), and the system configuration is loaded (e.g., power timing, noise interference, power glitch, software design, etc. errors). Reasons for the error message of the system 300 in the shutdown state include a failure of the system startup shutdown process (circuit hardware problem, system software shutdown), a failure of system data storage (incorrect shutdown procedure, failure or damage of circuit storage element), a failure of system power shutdown in sequence (circuit hardware problem, system software shutdown), and the like.

As shown in fig. 2, fig. 2 is a circuit diagram of the system function testing device of the present invention, in other embodiments, the circuit diagram of the system function testing device may also be composed of other components or circuits, and therefore, the circuit diagram of the system function testing device is not limited to the circuit diagram shown in fig. 2.

The power switching unit 111 includes a first transistor Q1 and a power switch SW. The first timing selection unit 113 includes a first selection switch SS1, a first resistor R1, a second resistor R2, a third resistor R3, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4. The output unit 115 includes a first capacitor C1, a fourth resistor R4, and a first comparator U1.

The drain of the first transistor Q1 is connected to the power supply Vcc, the gate of the first transistor Q1 is connected to the common point of the first selection switch SS1, and the source of the first transistor Q1 is connected to the power supply switch SW. The power switch SW is used to control whether the power 310 is supplied to the system power supply 330.

The power supply Vcc connects the first resistor R1, the second resistor R2, and the third resistor R3 in series. Three output terminals of the first selection switch SS1 are connected to the gate of the second transistor Q2, the gate of the third transistor Q3, and the gate of the fourth transistor Q4, respectively. The source of the second transistor Q2 is connected to the line of the first resistor R1 in series with the second resistor R2, the source of the third transistor Q3 is connected to the line of the second resistor R2 in series with the third resistor R3, and the source of the fourth transistor Q4 is connected to the third resistor R3. One end of the first capacitor C1 is connected to the drain of the second transistor Q2, the drain of the third transistor Q3 and the drain of the fourth transistor Q4, and the other end of the first capacitor C1 is connected to the ground terminal. The fourth resistor R4 connects the first capacitor C1 and the positive (+) input of the first comparator U1. The negative (-) input of the first comparator U1 receives the first reference signal S_R1First reference signal S_R1Is the transition voltage value of the first comparator U1, which may be a fixed value. The output terminal of the first comparator U1 is connected to the common point of the gate of the first transistor Q1 and the first selection switch SS 1.

The second timer 130 includes a charging unit 131 and a second timing selecting unit 133. The charging unit 131 is connected to the output terminal of the output unit 115, the second timing selection unit 133 and the processor 150, and outputs a first output signal S_U1The charging unit 131 is controlled to be charged, and the charging unit 131 is discharged through the second timing selection unit 133. In the discharging state of the charging unit 131, the system signal S_SWithout error information, the processing unit 150 allows the output unit 115 to discharge. System signal S_SWhen there is an error message, the processing unit 150 does not allow the output unit 115 to discharge.

The charging unit 131 includes a fifth resistor R5, a fifth transistor Q5, and a second capacitor C2. The fifth resistor R5 is connected in series with the power supply Vcc and the source of the fifth transistor Q5. The gate of the fifth transistor Q5 is connected to the output of the first comparator U1. The second capacitor C2 is connected in series to the drain of the fifth transistor Q5 and the ground terminal.

The second timing selecting unit 133 includes a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, and a second selection switch SS 2.

The drain of the sixth transistor Q6, the drain of the seventh transistor Q7, and the drain of the eighth transistor Q8 are connected to a second capacitor C2. A source of the sixth transistor Q6 is connected in series to the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, and the ground. The source of the seventh transistor Q7 is connected to the series path of the sixth resistor R6 and the seventh resistor R7. The source of the eighth transistor Q8 is connected to the series path of the seventh resistor R7 and the eighth resistor R8. The gate of the sixth transistor Q6, the gate of the seventh transistor Q7, and the gate of the eighth transistor Q8 are connected to the output node of the second selection switch SS2, respectively. The common point of the second selection switch SS2 is connected to the output terminal of the first comparator U1.

The processor 150 includes a second comparator U2, a first diode D1, a second diode D2, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a ninth transistor Q9, and a tenth transistor Q10.

The positive (+) input terminal of the second comparator U2 is connected to the second capacitor C2. The negative (-) input terminal of the second comparator U2 is connected with the second reference signal S_R2A second reference signal S_R2Is the transition voltage value of the second comparator U2, which may be a fixed value. The first diode D1 is connected in series to the output of the second comparator U2 and the ninth resistor R9. The second diode D2 is connected to the system 300 and the ninth resistor R9, and receives the system signal S_S. The tenth resistor R10 is connected to the ninth resistor R9 and ground. The base of the ninth transistor Q9 is connected to the ninth resistor R9, and the emitter of the ninth transistor Q9 is connected to ground. An eleventh resistor R11 connected to power supply Vcc anda collector of the ninth transistor Q9. The collector of the ninth transistor Q9 is connected to the gate of the tenth transistor Q10. The twelfth resistor R12 is connected to the source of the tenth transistor Q10 and ground. The drain of the tenth transistor Q10 is connected to the first capacitor C1.

The power-on and power-off test timing sequence may be adjusted by the first timer 110 and the second timer 130, and the power-on and power-off test timing sequence includes a power-on time and a power-off time, and the power-on time and the power-off time may be adjusted by the first timer 110 and the second timer 130 in a ratio. In this embodiment, the first selection switch SS1 of the first timing selection unit 113 and the second selection switch SS2 of the second timing selection unit 133 are adjusted to change the charging time of the first capacitor C1 by adjusting the first selection switch SS1, and the discharging time of the second capacitor C2 by adjusting the second selection switch. Therefore, the timing times of the first timer 110 and the second timer 130 can be determined before the functional test is performed. In other embodiments, the timing manner of the first timer 110 and the second timer 130 can be achieved by other timing circuits or integrated circuits.

Before the functional test is ready, the initial voltage of the first capacitor C1 and the second capacitor C2 are both 0 volt (V), in this embodiment, the power supply Vcc selects the second transistor Q2 as the charging path of the first capacitor C1 according to the first selection switch SS1, and the second selection switch SS2 selects the sixth transistor Q6 as the discharging path of the second capacitor C2, so that it can be understood from the circuit diagram of fig. 2 that the ratio of the power-on time and the power-off time of the power-on and power-off test timing can be effectively adjusted by changing the resistance values of the first timing selector 113 and the second timing selector 133.

As shown in FIG. 3, initially, the output of the first comparator U1 is at a low level (e.g., 0), and therefore, the voltage V of the first capacitor C1_C1Establishing a current I through a first resistor R1_R1Charging, current I_R1The current flowing through the path formed by the first resistor R1 and the second transistor Q2 charges from 0V to a high voltage level, and triggers the first comparator U1 to transition from a low level to a high level (e.g., 1), wherein the transition represents that the voltage value of the first capacitor C1 exceeds the first reference signal S_R1And the first selection switch SS1 is touchedThe second transistor Q2 is turned off, i.e. the charging of the first capacitor C1 is stopped.

When the first comparator U1 changes from the low level to the high level, the first transistor Q1 is triggered to turn on to control the power switch SW to allow the power 310 to be supplied to the system power supply 330, and then the functional test is started. When the first comparator U1 changes from the low level to the high level, it is the boot time T for performing the boot and shutdown test procedure_ON。

Initially, the output of the first comparator U1 is low, and the fifth transistor Q5 is turned on, so that the voltage V is established across the second capacitor C2_C2Voltage V of_C2Is the current I of the fifth resistor R5_R5Charging a second capacitor C2 with a current I_R5The voltage across the fifth transistor Q5 and the fifth resistor R5 charges the second capacitor C2, and the voltage across the second capacitor C2 controls whether the second comparator U2 is turned on. After the first comparator U1 changes from the low level to the high level, the fifth transistor Q5 is turned off, i.e., the charging of the second capacitor C2 is stopped, and the sixth transistor Q6 is triggered to be turned on, so that the sixth transistor Q6, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 form a discharging path of the second capacitor C2.

Subsequently, the system 300 does not generate or output the system signal S of the error information (ERR)_SAnd when the second capacitor C2 is discharged to a relatively low voltage value through the second timing selection unit 133 and the second comparator U2 transitions from high to low, the ninth transistor Q9 is triggered to turn off (e.g., V of the ninth transistor Q9 in fig. 3)_CEQ9Change is the voltage change between collector and emitter), so that the power Vcc triggers the tenth transistor Q10 to turn on, and the first capacitor C1 discharges through the turned-on tenth transistor Q10 and the twelfth resistor R12 (e.g., the current I of the twelfth resistor R12 in fig. 3)_R12) Then, the first capacitor C1 is discharged from the fully charged high voltage to the low voltage, so that the first comparator U1 changes state from the high level to the low level, and enters the shutdown time T of the startup and shutdown test procedure_OFFThen, the above steps are repeated to charge the first capacitor C1 and the second capacitor C2 again to continuously perform the power-on and power-off testsAnd (5) testing the program.

As shown in FIG. 4, when the system 300 generates or outputs a system signal S with error information (ERR)_SWhen the error information ERR in the graph is changed from low level to high level, the system signal S_SThe ninth transistor Q9 is triggered to conduct preferentially by the second diode D2 and the ninth resistor R9, so that the fully charged first capacitor C1 cannot be discharged by the processor 150, i.e. the processor 150 does not allow the output unit 115 to discharge, and therefore, after the transition, the current I of the first resistor R1_R1Voltage V of the first capacitor C1_C1And the output level of the first comparator U1 is maintained at the state of transition, and the current I of the twelfth resistor R12_R12The discharging phenomenon does not occur, so, the starting and shutdown test time sequence is stopped, and the state of the first timer is locked, namely the error information of the system is locked.

In summary, the system function testing apparatus of the present invention can change the ratio of the power-on time and the power-off time of the power-on and power-off testing sequence by adjusting the first timer and the second timer, and can implement repeated execution of the system power-on operation and the system power-off operation by the processor, and lock the system error information when the system has an error, so as to determine the cause of the error, thereby improving the efficiency of testing and error elimination of the system.

Finally, it is emphasized that the sequence of steps and components disclosed in the foregoing embodiments is merely exemplary and not intended to limit the scope of the present disclosure, and other changes in the sequence of steps, substitutions and alterations of equivalent components, and other embodiments are also intended to be covered by the claims of the present disclosure.

Claims

1. A system function testing apparatus comprising:

a first timer;

a second timer coupled to the first timer; and

and the processor is coupled with the first timer and the second timer and receives a system signal, wherein the first timer and the second timer establish a starting-up and shutdown test time sequence, and the processor locks the state of the first timer and stops the starting-up and shutdown test time sequence when the starting-up and shutdown test time sequence and the system signal comprise error information.

2. The apparatus for system function testing according to claim 1, wherein the second timer notifies the processor to allow the first timer to continue executing the power-on and power-off test sequence when the system signal does not include the error message.

3. The apparatus of claim 1, wherein the power-on and power-off test timing sequence comprises a power-on time and a power-off time, the power-on time defining a system executing a power-on operation, and the power-off time defining the system executing a power-off operation.

4. The system function testing device of claim 3, wherein the first timer comprises a first timing selection unit, the second timer comprises a second timing selection unit, and the first timing selection unit and the second timing selection unit change the power-on time and the power-off time by adjusting resistance values.

5. The system function testing device of claim 4, wherein the first timer further comprises a power switching unit and an output unit, the power switching unit is connected to the first timing selecting unit and a system power path, an input terminal of the output unit is connected to the first timing selecting unit, an output terminal of the output unit is connected to the power switching unit and the second timer, the output unit is charged by the first timing selecting unit, and outputs a first output signal to control the power switching unit and the second timer according to a charging status.

6. The system function testing device of claim 5, wherein the second timer further comprises a charging unit, the charging unit is connected to the output terminal of the output unit, the second timing selection unit and the processor, the first output signal controls the charging unit to charge, and the charging unit discharges through the second timing selection unit.

7. The system function test apparatus of claim 6, wherein the processing unit allows the output unit to discharge when the charging unit is in a discharging state and the system signal does not have the error message, and does not allow the output unit to discharge when the system signal has the error message.