CN111816729B - LED/ZnO nanowire array integrated photoelectric transistor chip and preparation method thereof - Google Patents
LED/ZnO nanowire array integrated photoelectric transistor chip and preparation method thereof Download PDFInfo
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Abstract
An LED/ZnO nanowire array integrated photoelectric transistor chip and a preparation method thereof are disclosed. The N electrode of the LED is used as a transistor grid, one end of the ZnO nanowire array is used as a source electrode, a P electrode of the LED, namely an LED and ZnO heterojunction interface, is used as a drain electrode, the luminous power of the LED is adjusted through the voltage of the grid electrode, and the photoconduction size of the ZnO nanowire array is further adjusted and controlled. According to the invention, the LED and the ZnO nanowire array are integrated by utilizing the excellent photosensitive characteristic of the ZnO nanowire array to near ultraviolet light, and the GaN-based photoelectric interconnection is realized, so that a photoelectric integrated transistor chip is obtained.
Description
Technical Field
The invention relates to the technical field of integrated phototransistors, in particular to an LED/ZnO nanowire array integrated phototransistor chip and a preparation method thereof.
Background
At present, optoelectronic integration is one of the solutions to the limitation of signal transmission rate, and the conventional electronic transmission transistor has been developed to approach the limit with the continuous reduction of size. The integration of a light source and a detector on the same chip has become an active research direction in the field of integrated circuit research, and in the traditional silicon process, direct luminescence is difficult to realize due to the physical characteristic of indirect band gap of silicon, so that the integration of the light source and the detector becomes the bottleneck of silicon-based photoelectric integration. The GaN-based light emitting chip is mature, and the light emitting band covers the ultraviolet to infrared region. Meanwhile, low dimensional materials are also a hot research in the field of semiconductor materials and devices in recent years. The ZnO material has the characteristics of unique light sensitivity, gas sensitivity, pressure sensitivity and the like, is very wide in research in various fields, particularly, the ZnO nanowire array has a large light absorption surface area, and the photonic crystal-like array can enable light absorption to be more sufficient, so that the array has excellent detection performance on ultraviolet light.
Disclosure of Invention
In view of the above, the present invention is directed to an LED/ZnO nanowire array integrated phototransistor chip and a method for manufacturing the same, so as to at least partially solve at least one of the above-mentioned problems.
In order to achieve the purpose, the technical scheme of the invention is as follows:
an LED/ZnO nanowire array integrated phototransistor die comprising:
a substrate (1);
the UVA waveband LED is grown on the substrate (1) and comprises an N electrode (6), a P electrode (7) and an insulating protective layer (8) of silicon dioxide;
a vertical ZnO nanowire array detection layer (9) growing on the LED; a graphene current spreading layer (10) is arranged at the top end of the vertical ZnO nanowire array detection layer (9), and a top end electrode (11) is formed on the graphene current spreading layer (10);
the N electrode (6) of the LED is used as a grid electrode of the LED/ZnO nanowire array integrated photoelectric transistor, the P electrode (7) of the LED, namely an LED and ZnO heterojunction interface, is used as a drain electrode of the LED/ZnO nanowire array integrated photoelectric transistor, and the top electrode (11) is used as a source electrode of the LED/ZnO nanowire array integrated photoelectric transistor.
Specifically, the substrate (1) is a sapphire substrate.
Specifically, the N electrode (6), the P electrode (7) and the top electrode (11) are respectively and independently selected from Ti, Al or Au.
Specifically, the LED in the UVA band further includes the following structure:
a u-GaN layer (2) grown on the substrate (1) to a thickness of between 3 and 4 μm;
an n-GaN layer (3) grown on the u-GaN layer (2) and having a thickness of 1-2 μm;
the multiple quantum well layer (4) is grown on the n-GaN layer (3), the number of quantum well groups ranges from 5 groups to 10 groups, and the thickness ranges from 100nm to 200 nm;
and the p-GaN layer (5) is grown on the multi-quantum well layer (4) and has the thickness of 0.5 mu m to I mu m.
Specifically, the insulating protection layer (8) grows on the substrate (1), the N electrode (6), the N-GaN layer (3) and the P electrode (7) and on the side walls of the u-GaN layer (2), the N-GaN layer (3), the multi-quantum well layer (4) and the P-GaN layer (5), and the thickness of the insulating protection layer is between 100nm and 200 nm.
Specifically, the vertical ZnO nanowire array detection layer (9) grows on the p-GaN layer (5), the height of the vertical ZnO nanowire array detection layer ranges from 1.5 micrometers to 2 micrometers, and the diameter of the vertical ZnO nanowire array detection layer ranges from 400nm to 600 nm.
Specifically, the number of graphene current spreading layers (10) is between 3 and 6.
Specifically, the N electrode is grown on the N-GaN layer (3), and the P electrode is grown on the P-GaN layer (5).
A preparation method of an LED/ZnO nanowire array integrated photoelectric transistor chip comprises the following steps:
step A: manufacturing an LED emitting light in UVA wave band, wherein the manufacturing comprises manufacturing an N electrode (6) and a P electrode (7);
and B: an insulating protective layer (8) of silicon dioxide is grown to protect and isolate the N electrode (6) and the P electrode (7);
and C: growing a vertical ZnO nanowire array detection layer (9) on the LED;
step D: growing a graphene current expansion layer (10) on the vertical ZnO nanowire array detection layer (9);
step E: and manufacturing a top electrode (11) on the graphene current spreading layer (10).
Specifically, the step a further includes:
step A1: growing a u-GaN epitaxial layer (2) on a sapphire substrate;
step A2: growing an n-GaN epitaxial layer (3) on the material obtained in the step A1;
step A3: growing a multiple quantum well light-emitting layer (4) on the material obtained in step a 2;
step A4: growing a p-GaN epitaxial layer (5) on the material obtained in the step A3; step A5: partially etching the material obtained in the step A4 to expose the surface of the N-GaN epitaxial layer (3) corresponding to the N electrode (6); step A6: and respectively manufacturing an N electrode (6) and a P electrode (7) on the N-GaN layer (3) and the P-GaN layer (5).
In particular, the method comprises the following steps of,
in the steps A1, A2, A3 and A4, the materials of each layer are grown by MOCVD equipment;
in step A5, performing partial etching by using an inductively coupled plasma etching method;
in the step A6, an electron beam evaporation method is adopted to manufacture an N electrode (6) and a P electrode (7), wherein the material of the N electrode (6) and the material of the P electrode (7) are selected from Ti, Al or Au;
the method also comprises the following steps after the step A6: and annealing the N electrode (6) and the P electrode (7), wherein the treatment temperature is between 700 and 1000 ℃, and the annealing time is between 30 and 60 seconds.
Specifically, in the step B, an insulating protective layer (8) of silicon dioxide is grown by adopting a plasma enhanced chemical vapor deposition method;
the growth thickness is between 100nm and 200nm, and the growth temperature is between 25 ℃ and 30 ℃.
Specifically, in the step C, the ZnO nanowire array in the ZnO nanowire array detection layer (9) is grown by a hydrothermal method, two materials of zinc nitrate and hexamethylenetetramine are directly and vertically grown on the p-GaN layer (5), the reaction temperature is between 85 ℃ and 95 ℃, and the reaction time is between 150 minutes and 210 minutes.
Specifically, in the step D, the graphene current spreading layer (10) is realized by a method of transferring a single-layer graphene transparent conductive layer for multiple times.
Specifically, in step E, the top electrode (11) is grown by electron beam evaporation.
Based on the technical scheme, compared with the prior art, the LED/ZnO nanowire array integrated photoelectric transistor chip and the preparation method thereof have at least one of the following beneficial effects:
(1) according to the invention, the LEDs in UVA wave band are integrated with the vertical ZnO nanowire array in series, so that an integrated single chip of the ultraviolet wave band light source and the detector is obtained, and the difficulty of integration of the light source and the detector on the single chip in the prior art is alleviated. The output characteristic of the transistor is realized, the GaN-based photoelectric interconnection is realized, and the purpose of manufacturing a photoelectric integrated chip is achieved;
(2) the LED/ZnO nanowire array integrated photoelectric transistor chip and the preparation method thereof provided by the invention adjust the LED luminous power by using the grid voltage, and further adjust and control the photoconduction size of the ZnO nanowire array, thereby realizing the adjustment of the grid voltage on the source-drain current and realizing the electrical characteristic function of the photoelectric transistor.
Drawings
FIG. 1 is a schematic structural diagram of an LED/ZnO nanowire array integrated phototransistor chip in an embodiment of the present invention;
FIG. 2 is a flowchart of a method for manufacturing an LED/ZnO nanowire array integrated phototransistor chip according to an embodiment of the present invention.
In the above drawings, the reference numerals have the following meanings:
1-a substrate;
a 2-u-GaN layer;
a 3-n-GaN layer;
4-a multi-quantum well layer;
a 5-p-GaN layer;
a 6-N electrode;
a 7-P electrode;
8-a silicon dioxide insulating protective layer;
9-vertical ZnO nanowire array detection layer;
10-a graphene current spreading layer;
11-top electrode.
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
It should be noted that in the drawings or description, the same drawing reference numerals are used for similar or identical parts. Implementations not depicted or described in the drawings are of a form known to those of ordinary skill in the art. Additionally, while exemplifications of parameters including particular values may be provided herein, it is to be understood that the parameters need not be exactly equal to the respective values, but may be approximated to the respective values within acceptable error margins or design constraints. In addition, directional terms such as "upper", "lower", "left", "right", "front", "rear", and the like, referred to in the following embodiments, are directions only referring to the drawings. Accordingly, the directional terminology is used for purposes of illustration and is in no way limiting. In addition, references to positions between two elements of the present invention, such as "above," "upper," "above," "below," "lower," "below," "left" or "right," may indicate that the two elements are in direct contact, or may indicate that the two elements are not in direct contact.
And the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure. Furthermore, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.
The invention discloses an LED/ZnO nanowire array integrated photoelectric transistor chip and a preparation method thereof.
According to the LED/ZnO nanowire array integrated photoelectric transistor chip, the vertical ZnO nanowire array is grown on the UVA waveband LED, and the top end of the vertical ZnO nanowire array is used as a current expansion layer to manufacture an electrode; the N electrode of the LED is used as a transistor grid, one end of the ZnO nanowire array is used as a source electrode, a P electrode of the LED, namely an LED and ZnO heterojunction interface, is used as a drain electrode, the luminous power of the LED is adjusted through the voltage of the grid electrode, and the photoconduction size of the ZnO nanowire array is further adjusted and controlled. According to the invention, the LED and the ZnO nanowire array are integrated by utilizing the excellent photosensitive characteristic of the ZnO nanowire array to near ultraviolet light, and the GaN-based photoelectric interconnection is realized, so that a photoelectric integrated transistor chip is obtained.
According to an aspect of the present invention, there is provided an LED/ZnO nanowire array integrated phototransistor chip, including: a substrate; the near ultraviolet light emitting LED of the UVA wave band grows on the substrate and comprises an N electrode and a P electrode; a silicon dioxide insulating protective layer; a vertical ZnO nanowire array detection layer; a graphene current spreading layer; a tip electrode; the N electrode is a transistor grid electrode, the P electrode is a transistor drain electrode, and the top electrode is a transistor source electrode.
In a further embodiment, the substrate is a sapphire substrate.
In a further embodiment, the LED/ZnO nanowire array integrated phototransistor chip, wherein the N electrode, the P electrode, and the top electrode are made of materials comprising: ti, Al, Au.
In a further embodiment, the UVA band near-ultraviolet emitting LED structure further comprises: a u-GaN layer grown on the substrate and having a thickness of 3-4 μm; an n-GaN layer grown on the u-GaN layer and having a thickness of 1-2 μm; the multiple quantum well layer grows on the n-GaN layer, the number of the quantum well groups ranges from 5 groups to 10 groups, and the thickness ranges from 100nm to 200 nm; and the p-GaN layer is grown on the multi-quantum well layer and has the thickness of 0.5-1 mu m.
In a further embodiment, the silicon dioxide insulating protective layer is grown on the substrate, the N electrode, the N-GaN layer, the P electrode and the side walls of the u-GaN layer, the N-GaN layer, the multi-quantum well layer and the P-GaN layer, and has a thickness of 100nm to 200 nm.
In a further embodiment, the vertical ZnO nanowire array detection layer is grown on the p-GaN layer, and has a height of between 1.5 μm and 2 μm and a diameter of between 400nm and 600 nm.
In a further embodiment, the graphene current spreading layer is positioned on the vertical ZnO nanowire array detection layer, and the number of layers is between 3 and 6.
In further embodiments, the N electrode is grown on the N-GaN layer, the P electrode is grown on the P-GaN layer, and the top electrode is grown on the graphene current spreading layer.
According to another aspect of the invention, a method for preparing an LED/ZnO nanowire array integrated phototransistor chip is provided, which comprises the following steps: step A: manufacturing a UVA wave band luminous LED; manufacturing an N electrode and a P electrode; and B: growing a silicon dioxide insulating protective layer; and C: growing a vertical ZnO nanowire array detection layer; step D: growing a graphene current expansion layer; step E: and manufacturing a top electrode.
In further embodiments, said step a comprises: step A1: growing a u-GaN epitaxial layer on a sapphire substrate; step A2: growing an n-GaN epitaxial layer on the material obtained in the step A1; step A3: growing a multiple quantum well light-emitting layer on the material obtained in the step A2; step A4: growing a p-GaN epitaxial layer on the material obtained in the step A3; step A5: etching the material layer obtained in the steps A1, A2, A3 and A4 to expose the surface of the n-GaN layer; step A6: after the above steps a1, a2, A3, a4, a5, N electrodes and P electrodes were fabricated on the N-GaN layer and the P-GaN layer, respectively.
In a further embodiment, in the steps of A1, A2, A3 and A4, the growth of each layer of material is carried out by using MOCVD equipment; in the step A5, etching is carried out by using an inductively coupled plasma etching method; in the step A6, an electron beam evaporation method is adopted to manufacture electrodes, and the electrode materials comprise Ti, Al and Au. Wherein after the step A6, the method further comprises the following steps: and annealing the electrode, wherein the treatment temperature is between 700 and 1000 ℃, and the annealing time is between 30 and 60 seconds.
In a further embodiment, in the step B, the silicon dioxide insulating protective layer is grown by using a plasma enhanced chemical vapor deposition method. The growth thickness is between 100nm and 200nm, and the growth temperature is between 25 ℃ and 30 ℃.
In a further embodiment, in the step C, the ZnO nanowire array is grown by a hydrothermal method, and the vertical growth is directly performed on the p-GaN layer by using two materials, namely zinc nitrate and hexamethylenetetramine, wherein the reaction temperature is between 85 ℃ and 95 ℃ and the reaction time is between 150 minutes and 210 minutes.
In a further embodiment, in the step D, the graphene current spreading layer is formed by transferring a single graphene transparent conductive layer for multiple times.
In a further embodiment, in step E, the top electrode is grown by electron beam evaporation.
Example 1
An LED and ZnO nanowire array integrated phototransistor chip as shown in fig. 1, comprising: the substrate comprises a substrate 1, wherein the substrate 1 is a sapphire substrate; the UVA wave band near ultraviolet light emitting LED grows on the substrate 1, and comprises an N electrode 6 and a P electrode 7, and further comprises: a u-GaN layer 2 grown on the substrate 1 to a thickness of 3-4 μm; an n-GaN layer 3 grown on the u-GaN layer 2 to a thickness of 1-2 μm; the multiple quantum well layer 4 grows on the n-GaN layer 3, the number of quantum well groups ranges from 5 groups to 10 groups, and the thickness ranges from 100nm to 200 nm; a p-GaN layer 5 grown on the multiple quantum well layer 4 and having a thickness of 0.5 μm to 1 μm; a silicon dioxide insulating protection layer 8 is grown on the substrate 1, the N electrode 6, the N-GaN layer 3 and the P electrode 7 and on the side walls of the u-GaN layer 2, the N-GaN layer 3, the multi-quantum well layer 4 and the P-GaN layer 5, and the thickness of the silicon dioxide insulating protection layer is between 100nm and 200 nm; the vertical ZnO nanowire array detection layer 9 is grown on the p-GaN layer 5, the height of the vertical ZnO nanowire array detection layer is between 1.5 and 2 micrometers, and the diameter of the vertical ZnO nanowire array detection layer is between 400 and 600 nm; the graphene current spreading layer 10 is positioned on the vertical ZnO nanowire array detection layer 9, and the number of layers is between 3 and 6; a tip electrode 11; wherein, the N electrode 6 is a transistor gate electrode grown on the N-GaN layer 3, the P electrode 7 is a transistor drain electrode grown on the P-GaN layer 5, the top electrode 11 is a transistor source electrode grown on the graphene current spreading layer 10, and the N electrode 6, the P electrode 7 and the top electrode 11 are made of: ti, Al, Au.
Example 2
A preparation method of a phototransistor chip integrated by an LED and a ZnO nanowire array is disclosed, as shown in figure 2, and the preparation method comprises the following steps: step A: manufacturing a UVA wave band luminous LED; growing a u-GaN epitaxial layer 2 on a sapphire substrate, then growing an n-GaN epitaxial layer 3 on the u-GaN epitaxial layer, continuing to grow a multiple quantum well light-emitting layer 4 on the obtained material, and growing a p-GaN epitaxial layer 5 on the obtained material, wherein the materials of all layers grow by adopting MOCVD equipment. Etching the material layer obtained by the steps by using an inductively coupled plasma etching method to expose the n-GaN layer on the surface; after the above steps, an N electrode 6 and a P electrode 7 are respectively manufactured on the N-GaN layer 3 and the P-GaN layer 5 by adopting an electron beam evaporation method. Wherein after the above steps further comprising: and annealing the electrode, wherein the treatment temperature is between 700 and 1000 ℃, and the annealing time is between 30 and 60 seconds. And B: growing a silicon dioxide insulating protective layer 8 by adopting a plasma enhanced chemical vapor deposition method, wherein the growth thickness is between 100nm and 200nm, and the growth temperature is between 25 ℃ and 30 ℃; and C: growing by a hydrothermal method, and directly and vertically growing a ZnO nanowire array detection layer 9 on the p-GaN layer 5 by adopting two materials of zinc nitrate and hexamethylenetetramine, wherein the reaction temperature is between 85 and 95 ℃, and the reaction time is between 150 and 210 minutes; step D: growing a graphene current expansion layer 10 by adopting a method of transferring a single-layer graphene transparent conducting layer for multiple times; step E: the top electrode 11 is fabricated by electron beam evaporation.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. An LED/ZnO nanowire array integrated phototransistor chip, comprising:
a substrate (1);
the UVA waveband LED is grown on the substrate (1) and comprises an N electrode (6), a P electrode (7) and an insulating protective layer (8) of silicon dioxide;
a vertical ZnO nanowire array detection layer (9) growing on the LED; a graphene current spreading layer (10) is arranged at the top end of the vertical ZnO nanowire array detection layer (9), and a top end electrode (11) is formed on the graphene current spreading layer (10);
the N electrode (6) of the LED is used as a grid electrode of the LED/ZnO nanowire array integrated photoelectric transistor, the P electrode (7) of the LED is positioned at the interface of the LED and the ZnO heterojunction and used as a drain electrode of the LED/ZnO nanowire array integrated photoelectric transistor, and the top electrode (11) is used as a source electrode of the LED/ZnO nanowire array integrated photoelectric transistor.
2. The LED/ZnO nanowire array integrated phototransistor chip as claimed in claim 1, wherein the substrate (1) is a sapphire substrate;
the N electrode (6), the P electrode (7) and the top electrode (11) are made of materials selected from Ti, Al or Au respectively and independently.
3. The LED/ZnO nanowire array integrated phototransistor chip of claim 1, wherein the UVA band LED further comprises the structure:
a u-GaN layer (2) grown on the substrate (1) to a thickness of between 3 and 4 μm;
an n-GaN layer (3) grown on the u-GaN layer (2) and having a thickness of 1-2 μm;
the multiple quantum well layer (4) is grown on the n-GaN layer (3), the number of quantum well groups ranges from 5 groups to 10 groups, and the thickness ranges from 100nm to 200 nm;
and the p-GaN layer (5) is grown on the multi-quantum well layer (4) and has the thickness of 0.5-1 μm.
4. The LED/ZnO nanowire array integrated phototransistor chip of claim 3, wherein:
the insulating protection layer (8) grows on the substrate (1), the N electrode (6), the N-GaN layer (3) and the P electrode (7) and on the side walls of the u-GaN layer (2), the N-GaN layer (3), the multi-quantum well layer (4) and the P-GaN layer (5), and the thickness of the insulating protection layer is between 100nm and 200 nm;
the N electrode is grown on the N-GaN layer (3), and the P electrode is grown on the P-GaN layer (5).
5. The LED/ZnO nanowire array integrated phototransistor chip as claimed in claim 3, wherein the vertical ZnO nanowire array detection layer (9) is grown on the p-GaN layer (5) with a height between 1.5 μm and 2 μm and a diameter between 400nm and 600 nm;
the number of layers of the graphene current spreading layer (10) is between 3 and 6.
6. A preparation method of an LED/ZnO nanowire array integrated photoelectric transistor chip is characterized by comprising the following steps:
step A: manufacturing an LED emitting light in UVA wave band, wherein the manufacturing comprises manufacturing an N electrode (6) and a P electrode (7);
and B: an insulating protective layer (8) of silicon dioxide is grown to protect and isolate the N electrode (6) and the P electrode (7);
and C: growing a vertical ZnO nanowire array detection layer (9) on the LED;
step D: growing a graphene current expansion layer (10) on the vertical ZnO nanowire array detection layer (9);
step E: manufacturing a top electrode (11) on the graphene current spreading layer (10);
the N electrode (6) of the LED is used as a grid electrode of the LED/ZnO nanowire array integrated photoelectric transistor, the P electrode (7) of the LED is positioned at the interface of the LED and the ZnO heterojunction and used as a drain electrode of the LED/ZnO nanowire array integrated photoelectric transistor, and the top electrode (11) is used as a source electrode of the LED/ZnO nanowire array integrated photoelectric transistor.
7. The method of claim 6, wherein the step A further comprises:
step A1: growing a u-GaN epitaxial layer (2) on a sapphire substrate;
step A2: growing an n-GaN epitaxial layer (3) on the material obtained in the step A1;
step A3: growing a multiple quantum well light-emitting layer (4) on the material obtained in step a 2;
step A4: growing a p-GaN epitaxial layer (5) on the material obtained in the step A3;
step A5: partially etching the material obtained in the step A4 to expose the surface of the N-GaN epitaxial layer (3) corresponding to the N electrode (6);
step A6: and respectively manufacturing an N electrode (6) and a P electrode (7) on the N-GaN layer (3) and the P-GaN layer (5).
8. The method of claim 7, wherein:
in the steps A1, A2, A3 and A4, the materials of each layer are grown by MOCVD equipment;
in step a5, a partial etch is performed using an inductively coupled plasma etch.
9. The method of claim 7, wherein:
in the step A6, an electron beam evaporation method is adopted to manufacture an N electrode (6) and a P electrode (7), wherein the material of the N electrode (6) and the material of the P electrode (7) are selected from Ti, Al or Au;
the method also comprises the following steps after the step A6: and annealing the N electrode (6) and the P electrode (7), wherein the treatment temperature is between 700 and 1000 ℃, and the annealing time is between 30 and 60 seconds.
10. The method of claim 6, wherein:
in the step B, an insulating protective layer (8) of silicon dioxide is grown by adopting a plasma enhanced chemical vapor deposition method; the growth thickness is between 100nm and 200nm, and the growth temperature is between 25 ℃ and 30 ℃;
in the step C, growing the ZnO nanowire array in the ZnO nanowire array detection layer (9) by a hydrothermal method, directly and vertically growing the ZnO nanowire array on the p-GaN layer (5) by using two materials of zinc nitrate and hexamethylenetetramine, wherein the reaction temperature is between 85 and 95 ℃, and the reaction time is between 150 and 210 minutes;
in the step D, the graphene current spreading layer (10) is realized by adopting a method of transferring a single-layer graphene transparent conducting layer for multiple times;
in step E, the top electrode (11) is grown by electron beam evaporation.
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