CN111799271A - Memory cell and operation method and preparation method thereof - Google Patents
Memory cell and operation method and preparation method thereof Download PDFInfo
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- CN111799271A CN111799271A CN202010622390.1A CN202010622390A CN111799271A CN 111799271 A CN111799271 A CN 111799271A CN 202010622390 A CN202010622390 A CN 202010622390A CN 111799271 A CN111799271 A CN 111799271A
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
Abstract
A memory cell and an operation method and a preparation method thereof, wherein the memory cell comprises: the semiconductor device comprises a substrate, a source electrode, a drain electrode, a stacked gate and a side wall, wherein the source electrode and the drain electrode are arranged in the substrate; the stacked gate is arranged on the substrate between the source electrode and the drain electrode and comprises a tunneling oxide layer, a charge trapping layer, an anti-ferroelectric thin film layer and a gate electrode which are sequentially arranged along the direction far away from the substrate; the gate electrode is used for providing a control voltage; the antiferroelectric thin film layer is used for enhancing an electric field on the tunneling oxide layer under the action of the control voltage and increasing the bending degree of an energy band of the tunneling oxide layer; the charge trapping layer is for trapping charge injected from the substrate to store information. The memory cell of the invention has low working voltage, high access speed and low power consumption.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a storage unit and an operation method and a preparation method thereof.
Background
The memory is a memory device used for storing information in modern information technology, is one of basic core components of an electronic system, and is a guarantee for normal operation of the system. For example, all information in the computer, including the raw data entered, the computer program, intermediate run results, and final run results, is stored in memory.
Flash memory (Flash) is currently the mainstream of non-volatile memory. However, Flash has the disadvantages of high operating voltage (typically greater than 10V, even 15V) and slow access speed (-1 ms), making it difficult to meet the development of future information technology.
Disclosure of Invention
Objects of the invention
The invention aims to provide a storage unit with low working voltage, high access speed and low power consumption, an operation method and a preparation method thereof.
(II) technical scheme
To solve the above problem, a first aspect of the present invention provides a memory cell, including: the semiconductor device comprises a substrate, a source electrode, a drain electrode, a stacked gate and a side wall, wherein the source electrode and the drain electrode are arranged in the substrate; the stacked gate is arranged on the substrate between the source electrode and the drain electrode and comprises a tunneling oxide layer, a charge trapping layer, an anti-ferroelectric thin film layer and a gate electrode which are sequentially arranged along the direction far away from the substrate; the gate electrode is used for providing a control voltage; the antiferroelectric thin film layer is used for enhancing an electric field on the tunneling oxide layer under the action of the control voltage and increasing the bending degree of an energy band of the tunneling oxide layer; the charge trapping layer is for trapping charge injected from the substrate to store information.
Further, the anti-ferroelectric film layer is made of an anti-ferroelectric film material.
Further, the antiferroelectric thin film material comprises Hf1-xZrxO2(0.5<x≤1)、Hf1-xSixO2(0.05<x<0.1)、Hf1-xAlxO2(0.06<x<0.1) Al doped Hf1-xZrxO2(0.5<x is less than or equal to 1) and Si is doped with Hf1-xZrxO2(0.5<x is less than or equal to 1).
Further, the thickness of the anti-ferroelectric thin film layer is not more than 50 nm.
Further, the charge trapping layer is silicon nitride (Si)3N4)、HfNx(x is not more than 1.3), heavily doped polysilicon, TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax、NiTax、MoNxTiSiN, TiCN, TaAlC, TiAlN, Ti, Ta, TaN, W and RuOxAny one or more of them.
Further, the gate electrode is made of heavily doped polysilicon, TaC, TiN, HfN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN or RuTax、NiTax、MoNxAny one or more of TiSiN, TiCN, TaAlC, TiAlN, TaN, Mo, Ti, Al, Cr, Au, Cu, Ag, W, and RuOx.
A second aspect of the present invention provides an operating method, applied to the above memory cell, the operating method including: when the memory cell is programmed, a forward control voltage is applied to the gate electrode, downward polarization is generated in the anti-ferroelectric thin film layer, and a larger downward electric field is generated in the tunneling oxide layer, so that electrons in the substrate tunnel through the tunneling oxide layer into and stay on the charge trapping layer; then removing the forward control voltage on the gate electrode, and greatly reducing or reducing the polarization in the antiferroelectric film layer to 0, and simultaneously keeping a large number of electrons in the charge trapping layer; when the memory unit is erased, a negative control voltage is applied to the gate electrode or a positive voltage is applied to the substrate, upward polarization is generated in the antiferroelectric thin film layer, and a larger upward electric field is generated in the tunneling oxide layer at the moment, so that electrons staying in the charge trapping layer enter the substrate through the tunneling oxide layer; then the negative voltage on the gate electrode is removed, the polarization in the antiferroelectric film layer is greatly reduced or reduced to 0, and meanwhile, the electrons reserved in the charge trapping layer are fewer and can be ignored; when the memory cell is read, applying a control voltage in a preset range on the gate electrode, applying a drain voltage on the drain electrode of the memory cell, and judging the magnitude of current passing through the source electrode and the drain electrode: if the current is larger than a preset current value, the memory unit is in an erasing state; and if the current is smaller than the current preset value, the memory cell is in a programming state.
The third aspect of the invention provides a preparation method of a memory unit, which comprises the steps of providing a substrate with a source electrode, a drain electrode and a side wall; depositing a tunneling oxide layer on the surface of the substrate between the side walls; depositing a charge trapping layer on the surface of the tunneling oxide layer; depositing an antiferroelectric film layer on the surface of the charge trapping layer; and forming a gate electrode on the surface of the anti-ferroelectric film layer.
Further, the providing the substrate with the source electrode, the drain electrode and the side wall comprises: forming a dummy gate stack on a substrate; forming side walls on two sides of the dummy gate stack; forming a source electrode and a drain electrode between the side wall and the substrate; and removing the dummy gate stack.
Further, the forming a gate electrode on the surface of the antiferroelectric thin film layer includes:
and depositing a gate electrode material on the surface of the anti-ferroelectric film layer, carrying out thermal annealing treatment, and then carrying out planarization treatment.
(III) advantageous effects
The technical scheme of the invention has the following beneficial technical effects:
the invention can enhance the electric field acting on the tunneling oxide layer by using the polarization characteristic of the antiferroelectric film layer during programming/erasing, increase the bending degree of the energy band of the tunneling oxide layer, greatly promote the tunneling efficiency of electrons, reduce the working voltage of the storage unit and improve the erasing speed of the storage unit by arranging the antiferroelectric film layer. Moreover, the antiferroelectric thin film layer material can be compatible with the existing silicon-based process, and is beneficial to the integration of the storage unit provided by the invention. In addition, the memory unit provided by the invention has a simpler structure, and the preparation method relates to the existing mature process, so that the low-cost manufacture can be realized.
Drawings
FIG. 1 is a schematic structural diagram of a memory cell according to embodiment 1 of the present invention;
fig. 2 is a polarization charge-voltage curve of the anti-ferroelectric thin film layer of example 1 of the present invention;
FIG. 3 is a flow chart of a method for fabricating a memory cell according to embodiment 3 of the present invention;
fig. 4 is a schematic view of a manufacturing process of a memory cell according to embodiment 3 of the present invention.
Fig. 5 is a schematic structural diagram of forming a dummy gate stack on a substrate according to embodiment 3 of the present invention.
Reference numerals:
1: a substrate; 21: a source electrode; 22: a drain electrode; 3: a side wall; 4: stacking a dummy gate; 5: stacking the grids; 51: tunneling through the oxide layer; 52: a charge trapping layer; 53: an antiferroelectric thin film layer; 54: and a gate electrode.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings in conjunction with the following detailed description. It should be understood that the description is intended to be exemplary only, and is not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.
In the drawings a schematic view of a layer structure according to an embodiment of the invention is shown. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
FIG. 1 is a schematic structural diagram of a memory cell according to embodiment 1 of the present invention;
fig. 2 is a polarization charge-voltage curve of the anti-ferroelectric thin film layer of example 1 of the present invention.
As shown in fig. 1 and 2, the present embodiment provides a memory cell including: the structure comprises a substrate 1, a source electrode 21 and a drain electrode 22 arranged in the substrate 1, a stacked gate 5 and a side wall 3; the stack gate 5 is arranged on the substrate 1 between the source electrode 21 and the drain electrode 22, and comprises a tunneling oxide layer 51, a charge trapping layer 52, an anti-ferroelectric thin film layer 53 and a gate electrode 54 which are arranged in sequence from bottom to top; the gate electrode 54 is used to provide a voltage; the antiferroelectric thin film layer 53 is used for enhancing an electric field on the tunneling oxide layer 51 under the action of the voltage, and increasing the bending degree of the energy band of the tunneling oxide layer 51; the charge trapping layer 52 serves to trap charge stored information injected from the substrate 1.
By arranging the antiferroelectric film layer 53, the electric field acting on the tunneling oxide layer 51 can be increased by utilizing the polarization characteristic of the antiferroelectric film layer 53 during working (programming/erasing), the tunneling efficiency of electrons is greatly promoted, the working voltage of the storage unit can be reduced, the erasing speed of the storage unit can be increased, and further, the access speed is increased, and the power consumption is reduced.
Specifically, the anti-ferroelectric thin film layer 1 is made of an anti-ferroelectric thin film material. The antiferroelectric thin film material includes but is not limited to Hf1-xZrxO2(0.5<x≤1)、Hf1-xSixO2(0.05<x<0.1)、Hf1-xAlxO2(0.06<x<0.1) Al doped Hf1-xZrxO2(0.5<x is less than or equal to 1) and Si is doped with Hf1-xZrxO2(0.5<x is less than or equal to 1).
Optionally, the thickness of the antiferroelectric thin film layer 53 is not greater than 50 nm.
Alternatively, the substrate 1 is any one of silicon, germanium, silicon-on-insulator (SOI), and germanium-on-insulator (GOI).
Alternatively, the charge trapping layer 52 is silicon nitride (Si)3N4)、HfNx(x is not more than 1.3), heavily doped polysilicon, TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax、NiTax、MoNxTiSiN, TiCN, TaAlC, TiAlN, Ti, Ta, TaN, W and RuOxAny one or more of them.
Optionally, gate electrode 54 is heavily doped polysilicon, TaC, TiN, HfN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax、NiTax，MoNxTiSiN, TiCN, TaAlC, TiAlN, TaN, Mo, Ti, Al, Cr, Au, Cu, Ag, W and RuOxAny one or more of.
Example 2
In the programming process, a forward control voltage is applied to the gate electrode 54, a polarization in a downward direction is generated in the antiferroelectric thin film layer 53 (the polarization charge on the control gate electrode 54 is positive, corresponding to point a in fig. 2), and at this time, a large electric field is generated in the tunnel oxide layer 51, so that electrons in the substrate 1 tunnel through the tunnel oxide layer 51 into and stay on the charge trapping layer 52; then, the forward control voltage on the control gate electrode 54 is removed, the polarization in the antiferroelectric film layer will be greatly reduced or decreased to 0, and if the antiferroelectric film is an ideal antiferroelectric film, the polarization is decreased to 0, which corresponds to the point O in fig. 2, and a large number of electrons are retained in the charge trapping layer 52;
during erasing, a negative control voltage is applied to the gate electrode 54 or a positive voltage is applied to the substrate 1, an upward polarization is generated in the anti-ferroelectric thin film layer 53 (the polarization charge on the control gate electrode 54 is negative, corresponding to point B in fig. 2), and at this time, a large reverse electric field is generated in the tunnel oxide layer 51, so that electrons staying in the charge trapping layer 52 enter the substrate 1 through the tunnel oxide layer 51; then, the negative control voltage on the control gate electrode 54 is removed, the polarization in the anti-ferroelectric thin film layer 53 will be greatly reduced or decreased to 0, and if the anti-ferroelectric thin film is an ideal anti-ferroelectric thin film, the polarization will be decreased to 0 (corresponding to point O in fig. 2); and fewer, negligible electrons remain in charge trapping layer 52.
Example 3
FIG. 3 is a flow chart of a method for fabricating a memory cell according to embodiment 3 of the present invention; fig. 4 is a schematic view of a manufacturing process of a memory cell according to embodiment 3 of the present invention.
As shown in fig. 3 and fig. 4, the present embodiment provides a method for manufacturing a memory cell, providing a substrate 1 having a source 21, a drain 22 and sidewalls 3 (as shown in fig. 4 a); depositing a tunneling oxide layer 51 on the surface of the substrate 1 between the side walls 3 (as shown in fig. 4 b); depositing a charge trapping layer 52 on the surface of the tunnel oxide layer 51 (see fig. 4 c); depositing an anti-ferroelectric thin film layer 53 on the surface of the charge trapping layer 52 (see fig. 4 d); a gate electrode 54 is formed on the surface of the antiferroelectric thin film layer 53 (see fig. 4 e).
The memory cell manufactured by the manufacturing method of this embodiment is provided with the antiferroelectric thin film layer, and a larger electric field can be applied to the tunneling oxide layer 51 during operation (programming/erasing) by utilizing the polarization characteristic of the antiferroelectric thin film layer 53, so that the tunneling efficiency of electrons is greatly promoted, the operating voltage of the memory cell can be reduced, the erasing speed of the memory cell can be increased, the access speed is increased, the power consumption is reduced, and the fatigue resistance is improved.
Fig. 5 is a schematic structural diagram of forming a dummy gate stack on a substrate according to embodiment 3 of the present invention.
As shown in fig. 5, in an alternative embodiment of the present embodiment, providing a substrate 1 having a source 21, a drain 22 and a sidewall 3 includes: forming a dummy gate stack 4 on a substrate 1; forming sides on both sides of the dummy gate stack 4; a source electrode 21 and a drain electrode 22 are arranged between the side wall 3 and the substrate 1 in a shape of a middle (as shown in figure 5); the dummy gate stack 4 is removed.
In an alternative embodiment of this embodiment, forming the gate electrode 54 on the surface of the antiferroelectric thin film layer 53 includes: and depositing a gate electrode 54 material on the surface of the anti-ferroelectric thin film layer 53, performing thermal annealing treatment, and then performing planarization treatment.
The invention aims to protect a memory cell and an operation method and a manufacturing method thereof, wherein the memory cell comprises: the gate electrode 54, the antiferroelectric thin film layer 53, the tunneling oxide layer 51, the charge trapping layer 52, the sidewall 3, the source 21, the drain 22, the substrate 1, the gate electrode 54, the antiferroelectric thin film layer 53, the charge trapping layer 52, and the tunneling oxide layer 51 are sequentially arranged from inside to outside. By arranging the antiferroelectric thin film layer 53, a larger electric field can be applied to act on the tunneling oxide layer 51 during operation (programming/erasing) by utilizing the polarization characteristic of the antiferroelectric thin film layer 53, thereby greatly promoting the tunneling efficiency of electrons, reducing the operating voltage of the memory cell and increasing the erasing speed of the memory cell. In addition, the semiconductor memory unit provided by the invention has a simpler structure, and the manufacturing method involves the existing mature process, so that the low-cost manufacturing can be realized.
It is to be understood that the above-described embodiments of the present invention are merely illustrative of or explaining the principles of the invention and are not to be construed as limiting the invention. Therefore, any modification, equivalent replacement, improvement and the like made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. Further, it is intended that the appended claims cover all such variations and modifications as fall within the scope and boundaries of the appended claims or the equivalents of such scope and boundaries.
Claims (10)
1. A memory cell, comprising: the transistor comprises a substrate (1), a source electrode (21) and a drain electrode (22) which are arranged in the substrate (1), a stacked gate (5) and a side wall (3);
the stack gate (5) is arranged on the substrate (1) between the source electrode (21) and the drain electrode (22) and comprises a tunneling oxide layer (51), a charge trapping layer (52), an anti-ferroelectric thin film layer (53) and a gate electrode (54) which are sequentially arranged along the direction far away from the substrate (1);
the gate electrode (54) is used for providing a control voltage;
the antiferroelectric thin film layer (53) is used for enhancing an electric field on the tunneling oxide layer (51) under the action of the control voltage and increasing the bending degree of an energy band of the tunneling oxide layer (51);
the charge trapping layer (52) is for trapping charge injected from the substrate (1) to store information.
2. The memory cell of claim 1,
the anti-ferroelectric film layer (1) is made of an anti-ferroelectric film material.
3. The memory cell of claim 2,
the antiferroelectric thin film material comprises Hf1-xZrxO2(0.5<x≤1)、Hf1-xSixO2(0.05<x<0.1)、Hf1-xAlxO2(0.06<x<0.1) Al doped Hf1-xZrxO2(0.5<x is less than or equal to 1) and Si is doped with Hf1-xZrxO2(0.5<x is less than or equal to 1).
4. The memory cell according to claims 1-3,
the thickness of the anti-ferroelectric film layer (53) is not more than 50 nm.
5. The memory cell of claim 1, wherein the charge trapping layer (52) is silicon nitride (Si)3N4)、HfNx(x is not more than 1.3), heavily doped polysilicon, TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax、NiTax、MoNxTiSiN, TiCN, TaAlC, TiAlN, Ti, Ta, TaN, W and RuOxAny one or more of them.
6. The memory cell of claim 1, wherein the gate electrode (54) is heavily doped polysilicon, TaC, TiN, HfN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax、MoNxTiSiN, TiCN, TaAlC, TiAlN, TaN, Mo, Ti, Al, Cr, Au, Cu, Ag, W and RuOxAny one or more of.
7. An operating method applied to the storage unit according to any one of claims 1 to 6, wherein the operating method comprises:
when the memory cell is programmed, a forward control voltage is applied to the gate electrode (54), a polarization in a downward direction is generated in the antiferroelectric thin film layer (53), and a larger downward electric field is generated in the tunneling oxide layer (51), so that electrons in the substrate (1) tunnel through the tunneling oxide layer (51) into and stay in the charge trapping layer (52); then removing the forward control voltage on the gate electrode, and greatly reducing or reducing the polarization in the antiferroelectric film layer to 0, and simultaneously keeping a large number of electrons in the charge trapping layer;
when the memory cell is erased, applying a negative control voltage on the gate electrode (54) or applying a positive voltage on the substrate (1), an upward polarization is generated in the antiferroelectric thin film layer (53), and a larger upward electric field is generated in the tunneling oxide layer (51), so that electrons staying in the charge trapping layer (52) enter the substrate (1) through the tunneling oxide layer (51); then, when the negative voltage on the gate electrode (54) is removed, the polarization in the antiferroelectric thin film layer (53) will be greatly reduced or decreased to 0, and the electrons retained in the charge trapping layer (53) are less and negligible;
when the memory cell is read, a control voltage in a preset range is applied to the gate electrode (54), a drain voltage is applied to the drain (22) of the memory cell, and the magnitude of current passing through the source (21) and the drain (22) is judged: if the current is larger than a preset current value, the memory unit is in an erasing state; and if the current is smaller than the current preset value, the memory cell is in a programming state.
8. A method of manufacturing a memory cell, comprising,
providing a substrate (1) with a source (21), a drain (22) and side walls (3);
depositing a tunneling oxide layer (51) on the surface of the substrate (1) between the side walls (3);
depositing a charge trapping layer (52) on the surface of the tunneling oxide layer (51);
depositing an anti-ferroelectric thin film layer (53) on the surface of the charge trapping layer (52);
a gate electrode (54) is formed on the surface of the antiferroelectric thin film layer (53).
9. Method for manufacturing a memory cell according to claim 8, wherein said providing a substrate (1) with a source (21), a drain (22) and side walls (3) comprises:
forming a dummy gate stack (4) on a substrate (1);
forming side walls (3) on two sides of the dummy gate stack (4);
forming a source (21) and a drain (22) in between the sidewall spacer (3) and the substrate (1);
and removing the dummy gate stack (4).
10. The method for manufacturing a memory cell according to claim 8, wherein the forming a gate electrode (54) on the surface of the antiferroelectric thin film layer (53) comprises:
and depositing a gate electrode (54) material on the surface of the anti-ferroelectric film layer (53), carrying out thermal annealing treatment, and then carrying out planarization treatment.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112397392A (en) * | 2020-11-16 | 2021-02-23 | 西交利物浦大学 | Bionic synaptic transistor and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040041180A1 (en) * | 2002-08-28 | 2004-03-04 | Klaus Dimmler | Ferroelectric transistor with enhanced data retention |
| CN106537509A (en) * | 2014-07-23 | 2017-03-22 | 纳姆实验有限责任公司 | Charge storage ferroelectric memory hybrid and erase scheme |
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2020
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040041180A1 (en) * | 2002-08-28 | 2004-03-04 | Klaus Dimmler | Ferroelectric transistor with enhanced data retention |
| CN106537509A (en) * | 2014-07-23 | 2017-03-22 | 纳姆实验有限责任公司 | Charge storage ferroelectric memory hybrid and erase scheme |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112397392A (en) * | 2020-11-16 | 2021-02-23 | 西交利物浦大学 | Bionic synaptic transistor and preparation method thereof |
| CN112397392B (en) * | 2020-11-16 | 2023-09-12 | 西交利物浦大学 | Bionic synaptic transistor and its preparing process |
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