CN111799262A - U-shaped ferroelectric field effect transistor memory cell string, memory and preparation method - Google Patents
U-shaped ferroelectric field effect transistor memory cell string, memory and preparation method Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6684—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a ferroelectric gate insulator
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
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Abstract
The invention discloses a U-shaped ferroelectric field effect transistor memory cell string, a memory and a preparation method. The memory cell string comprises a U-shaped body formed by connecting two first columnar structures through a second columnar structure, a separation layer (6) and a plurality of layers of gate electrodes (4) arranged at intervals; each layer of the gate electrode (4) is used for surrounding the U-shaped body; the separation layer (6) penetrates through the multilayer gate electrode (4), is positioned in the opening of the U-shaped body and is used for separating the two columnar structures of the U-shaped body, so that the number of the storage units in the U-shaped storage unit string is twice of the number of the gate electrodes (4) in the U-shaped storage unit string. Compared with the prior art, the U-shaped memory cell string has more memory cells and higher memory density under the condition that the same number of layers of gate electrodes are arranged.
Description
Technical Field
The invention relates to the field of memories, in particular to a U-shaped ferroelectric field effect transistor memory cell string, a memory and a preparation method.
Background
The ferroelectric field effect transistor (FeFET) is a ferroelectric thin film material replacing a gate dielectric layer in a field effect transistor (MOSFET), and the ferroelectric thin film material is changed in polarization direction to control the on and off of channel current, thereby realizing the storage of information. The FeFET memory has the advantages of nonvolatility, low power consumption, high read-write speed and the like, and the unit structure is simple and the theoretical storage density is high. In particular, fefets enable three-dimensional integration and are considered one of the most promising new high-density memories.
At present, the defects of the existing three-dimensional FeFET memory are researched as follows: the uniformity and the electrical property of the existing ferroelectric thin film layer and the device thereof are poor, namely the performance difference of two memories prepared by the same method is larger; secondly, in the preparation process, the interface defects between the ferroelectric thin film layer and the channel layer are more, so that the fatigue performance of the device is poorer, and the difference between the threshold voltage and the sub-threshold swing amplitude of the device is larger, so that the reliability of the memory is poor; thirdly, in the preparation process of the existing memory, the dielectric layer or the ferroelectric thin film layer needs to be etched, so that the dielectric layer and the ferroelectric thin film layer are easily damaged, the performance of the device is affected, and the reliability of the memory is affected.
Disclosure of Invention
Objects of the invention
The invention aims to provide a U-shaped ferroelectric field effect transistor storage unit string, a memory and a preparation method, wherein the storage unit string comprises a U-shaped body formed by connecting two first columnar structures through a second columnar structure, and the U-shaped body is obtained by a deposition method, so that a ferroelectric thin film layer can be prevented from being etched in the preparation process, and the reliability of the memory is improved; in addition, the first dielectric layer and the second dielectric layer are arranged, so that the ferroelectric film is not directly contacted with the gate electrode layer and the channel layer, element diffusion in the ferroelectric film and interface reaction between the element diffusion and the gate electrode and the channel layer are avoided, the quality and the performance of the ferroelectric film layer and the memory unit are further ensured, the difference between the memory units is reduced, and the reliability of the memory is improved.
(II) technical scheme
In order to solve the above problems, a first aspect of the present invention provides a U-shaped ferroelectric field effect transistor memory cell string including a U-shaped body formed by connecting two first columnar structures by a second columnar structure, a separation layer, and a plurality of layers of gate electrodes disposed at intervals; each layer of gate electrode is used for surrounding the U-shaped body; the separation layer penetrates through the multilayer gate electrodes, is positioned in the opening of the U-shaped body and is used for separating the two first columnar structures of the U-shaped body so as to enable the number of the storage units in the storage unit string to be twice of the number of the gate electrodes in the storage unit string; the columnar structure is sequentially arranged from an outer layer to an inner layer: the ferroelectric thin film layer is arranged on the first dielectric layer; the first dielectric layer and the second dielectric layer are used for isolating the ferroelectric thin film layer so as to prevent the ferroelectric thin film layer from being in direct contact with the channel layer and the gate electrode, and the first dielectric layer and the second dielectric layer are both used as seed layers or stress control layers for growth of the ferroelectric thin film layer so as to promote generation of ferroelectric phases in the ferroelectric thin film layer, so that the ferroelectric thin film layer in the U-shaped ferroelectric field effect transistor memory cell string realizes a memory function.
Further, the method also comprises the following steps: and the filling layer is arranged in the channel layer and is used for filling the center of the columnar structure.
Further, the thickness of the channel layer is not greater than the thickness of a depletion layer of the channel layer.
Further, an isolation layer is arranged between the adjacent gate electrodes.
Further, the first dielectric layer is silicon oxide (SiO)2) Silicon nitride (Si)3N4) Silicon oxynitride (SiON), aluminum oxide (Al)2O3) Hafnium oxide (HfO)2) Zirconium oxide (ZrO)2) Titanium oxide (TiO)2) Lanthanum oxide (La)2O3) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)2) One or more of; the second dielectric layer 9 is silicon oxide (SiO)2) Silicon nitride (Si)3N4) Silicon oxynitride (SiON), aluminum oxide (Al)2O3) Hafnium oxide (HfO)2) Zirconium oxide (ZrO)2) Titanium oxide (TiO)2) Lanthanum oxide (La)2O3) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)2) And the like.
Further, the ferroelectric thin film layer is hafnium oxide (HfO)2) Doped HfO2Zirconium oxide (ZrO)2) Or doped ZrO2One of (1); wherein the doped HfO2The element to be doped in (b) includes one or more of silicon (Si), aluminum (Al), zirconium (Zr), lanthanum (La), cerium (Ce), strontium (Sr), lutetium (Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge), nitrogen (N), and the like.
Further, the channel layer is polysilicon (Si), poly-germanium (Ge), poly-silicon germanium (SiGe), or doped polysilicon (Si), doped poly-germanium (Ge), doped poly-silicon germanium (SiGe), and the doping element is one or more of boron (B), phosphorus (P), and arsenic (As).
According to a second aspect of the present invention, there is provided a U-shaped ferroelectric field effect transistor memory comprising: a substrate, a conductive layer and a plurality of said strings of U-shaped ferroelectric field effect transistor memory cells as provided in the first aspect of the present invention; the conductive layer is arranged on the substrate; the second columnar structure in the U-shaped ferroelectric field effect transistor memory cell string is embedded in the conductive layer, and the two first columnar structures of the U-shaped ferroelectric field effect transistor memory cell string are positioned outside the conductive layer and are perpendicular to the conductive layer; the separation layer is arranged on the conductive layer, is positioned between the two first columnar structures and is used for separating the two first columnar structures.
Further, the gate electrodes of the plurality of layers are arranged on the surface of the conductive layer, an isolation layer is arranged between the adjacent gate electrodes, and the isolation layer is arranged between the conductive layer and the gate electrode.
Further, the isolation layer is SiO2Or from SiO, which has a dielectric constant ratio2The insulating material having a small dielectric constant of (2); the gate electrode is any one of heavily doped polysilicon, a nitride metal electrode, and tungsten (W).
According to a third aspect of the present invention, there is provided a method for manufacturing a U-shaped ferroelectric field effect transistor memory, comprising: s1: forming a conductive layer on a substrate 1; s2: forming at least one trench in the conductive layer and depositing a medium to fill the trench; s3: sequentially overlapping and depositing an isolation layer and a gate electrode on the surface of the conductive layer to obtain a stacked layer, wherein the number of layers of the gate electrode is a preset number of layers; s4: forming two through holes above each groove, wherein the through holes penetrate through the stacked layers and reach the top of the groove; s5: removing the filled medium in the groove to enable the two through holes 13 to form U-shaped through holes; s6: depositing a first dielectric layer, a ferroelectric thin film layer, a second dielectric layer and a channel layer on the inner wall of the U-shaped through hole in sequence; s7: and forming a separation layer in the middle of the U-shaped through hole, wherein the separation layer at least penetrates through the gate electrode in the laminated structure to form the U-shaped ferroelectric field effect transistor memory.
Further, after the step S6, before the step S7, the method further includes: and depositing a filling layer on the inner wall of the channel layer to fill the through hole.
(III) advantageous effects
The technical scheme of the invention has the following beneficial technical effects:
(1) the storage unit string is provided with the first dielectric layer and the second dielectric layer, so that the ferroelectric film is not directly contacted with the gate electrode layer and the channel layer, element diffusion in the ferroelectric film and interface reaction between the element diffusion and the gate electrode and the channel layer are avoided, the quality and the performance of the ferroelectric film layer and the storage unit are further ensured, the difference between the storage units is reduced, and the reliability of the memory is improved; in addition, the first dielectric layer and the second dielectric layer are used as seed layers or stress control layers for growth of the ferroelectric thin film layer, so that the performance of the ferroelectric thin film layer is improved, the leakage current can be effectively reduced, and the retention performance of the FeFET memory is improved.
(2) In the memory cell string provided by the embodiment of the invention, the filling layer is added in the channel layer, which is equivalent to reducing the volume of the polycrystalline channel layer in the device, so that the defects in the polycrystalline channel layer can be reduced, and the fatigue performance of the device and the difference between the devices are improved.
(3) According to the preparation method provided by the invention, the first dielectric layer, the ferroelectric thin film layer and the second dielectric layer are formed by adopting a deposition method, and the storage unit string is U-shaped, so that the etching of the first dielectric layer, the ferroelectric thin film layer and the second dielectric layer is avoided, and the reliability of the memory can be improved.
Drawings
Fig. 1 is a schematic structural diagram of a ferroelectric field effect transistor memory cell provided in a first embodiment of the present invention.
Fig. 2a is a schematic structural diagram of a U-shaped ferroelectric field effect transistor memory cell string provided in a second embodiment of the present invention;
fig. 2b is a top view of a U-shaped ferroelectric field effect transistor memory cell string provided in a second embodiment of the present invention;
FIG. 3 is a schematic diagram of a U-shaped FEFET memory according to a third embodiment of the present invention;
FIG. 4 is a schematic flow chart of a method for manufacturing a U-shaped ferroelectric field effect transistor memory according to a fourth embodiment of the present invention;
FIG. 4a is a schematic diagram of a fourth embodiment of the present invention for forming a conductive layer on a substrate;
fig. 4b is a schematic diagram of forming a trench in a conductive layer according to a fourth embodiment of the present invention;
FIG. 4c is a schematic view of a stack of layers formed over a conductive layer according to a fourth embodiment of the present invention;
FIG. 4d is a schematic view of a via formed in a stack of layers according to a fourth embodiment of the present invention;
FIG. 4e is a schematic illustration of the removal of the dielectric in the trench 12a provided by a fourth embodiment of the present invention;
FIG. 4f is a schematic diagram of a fourth embodiment of the present invention for depositing a filling layer in a U-shaped via;
fig. 4g is a schematic diagram of forming a separation layer according to a fourth embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings in conjunction with the following detailed description. It should be understood that the description is intended to be exemplary only, and is not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.
In the drawings a schematic view of a layer structure according to an embodiment of the invention is shown. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "first", "second", and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
In the research process, the inventor of the invention finds that in the preparation process of the existing transistor, a gate electrode and a ferroelectric thin film layer are in direct contact, an interface layer is easily generated on the contact surface, and the quality of the interface layer is difficult to control, so that the uniformity and the electrical performance of the ferroelectric thin film layer and a device thereof are poor, namely the performance difference of two memories prepared by the same method is large.
Fig. 1 is a schematic structural diagram of a ferroelectric field effect transistor memory cell provided in a first embodiment of the present invention.
As shown in fig. 1, the memory cell includes: a gate electrode layer 4; a columnar structure is embedded in the gate electrode layer 4 in the thickness direction. The first dielectric layer 7, the ferroelectric thin film layer 8, the second dielectric layer 9 and the channel layer 10 are sequentially covered from the outer layer of the columnar structure to the direction close to the axis.
The first dielectric layer 7 and the second dielectric layer 9 are both made of insulating materials and are used for preventing the ferroelectric thin film layer 8 from contacting the gate electrode layer 4 and the channel layer 10, and the first dielectric layer 7 and the second dielectric layer 9 are both used as seed layers or stress control layers for growth of the ferroelectric thin film layer 8, so that generation of ferroelectric phases in the ferroelectric thin film layer 8 is promoted, the ferroelectric thin film layer 8 has excellent ferroelectric performance, and the storage function of the storage unit is ensured.
And a ferroelectric thin film layer 8 as a storage medium.
The principle of the memory cell is that the polarization direction of the ferroelectric thin film layer 8 is changed by the direction of voltage applied to the gate electrode layer 4, thereby turning on and off the channel layer 10 to realize a memory function.
It is understood that each layer of gate electrode and the corresponding columnar structure corresponds to a ferroelectric field effect transistor memory cell.
In one embodiment, a filling layer 11 is further included and disposed in the channel layer 10 to fill the center of the pillar structure.
In this embodiment, the filling layer is added to the channel layer, which is equivalent to reducing the volume of the channel layer in the device, so that defects in the channel layer can be reduced, which is helpful for improving the fatigue performance of the device and improving the difference between the devices.
Fig. 2a is a schematic structural diagram of a U-shaped ferroelectric field effect transistor memory cell string according to a second embodiment of the present invention. Fig. 2a shows a front view of a string of U-shaped ferroelectric field effect transistor memory cells. Fig. 2b is a top view of a U-shaped ferroelectric field effect transistor memory cell string provided in a second embodiment of the present invention.
As shown in fig. 2a and 2b, the U-shaped ferroelectric field effect transistor memory cell string includes a U-shaped body formed by two first columnar structures connected by a second columnar structure, a separation layer 6, and a plurality of layers of gate electrodes 4 disposed at intervals.
Specifically, the U-shaped body may be integrally formed, for example, two ends of a column structure are bent toward one side of the column structure.
Alternatively, the U-shaped body may be formed by connecting the end portions of two first columnar structures (two columnar structures vertically arranged in fig. 2) by a second columnar structure (a columnar structure horizontally arranged in fig. 2).
Or, the U-shaped body may be formed by extending an end of one first columnar structure in a direction perpendicular to a length direction thereof to form a second columnar structure, and then connecting the second columnar structure with an end of another first columnar structure.
It will be appreciated that the U-shaped body of the present invention can be formed in a variety of ways, and the present invention is not limited thereto.
Wherein each layer of the gate electrode 4 is used for surrounding the U-shaped body.
And the separation layer 6 penetrates through the multilayer gate electrode 4, is positioned in the opening of the U-shaped body, and is used for separating the two first columnar structures of the U-shaped body, so that the number of the storage units in the storage unit string 5 is twice of the number of the gate electrodes 4 in the storage unit string 5. That is, the separating layer functions to separate the two first columnar structures of the U-shaped body, so that each first columnar structure and the gate electrode 4 in multiple layers are used as a columnar memory cell string, and in addition, because the two first columnar structures of the U-shaped body are connected, the two columnar structures of the U-shaped body are connected in series under the action of the separating layer, so that the number of memory cells in the U-shaped memory cell string 5 is twice of the number of layers of the gate electrode 4 in the memory cell string 5.
Optionally, the separation layer 6 is a hole, such as a trapezoid hole or a square hole, or the separation layer 6 is made of an insulating material.
It is understood that the columnar structure may be a cylinder or a square column, and may also be a prism, and the present invention is not limited thereto.
The first columnar structure and the second columnar structure are both multilayer structures, and specifically, each columnar structure is sequentially provided with a first dielectric layer 7, a ferroelectric thin film layer 8, a second dielectric layer 9 and a channel layer 10 from an outer layer to an inner layer; the first dielectric layer 7 and the second dielectric layer 9 are used for isolating the ferroelectric thin film layer 8 to prevent the ferroelectric thin film layer 8 from directly contacting the channel layer 10 and the gate electrode 4, and the first dielectric layer 7 and the second dielectric layer 9 are both used as seed layers or stress control layers for growth of the ferroelectric thin film layer 8 to promote generation of ferroelectric phases in the ferroelectric thin film layer 8 and ensure that the ferroelectric thin film layer 8 has excellent ferroelectric properties so as to enable the ferroelectric thin film layer 8 in the U-shaped memory cell string to realize a memory function.
In one embodiment, a filling layer 11 is further included and disposed in the channel layer 10 to fill the center of the pillar structure.
In the embodiment, the filling layer 11 is added to the channel layer 10, which is equivalent to reducing the volume of the channel layer 10 in the device, so that defects in the channel layer 10 can be reduced, which is helpful for improving the fatigue performance of the device and improving the variability between devices.
It should be noted that, in a conventional memory cell string, the source and its selection transistor are disposed at the upper end of the memory cell string, and the drain and its selection transistor are disposed at the lower end of the memory cell string. This may affect metal wiring in subsequent processes, resulting in a complicated assembly process. According to the U-shaped ferroelectric field effect transistor storage unit string provided by the invention, the source electrode and the drain electrode are respectively positioned at the top ends of the two first columnar structures of the U-shaped storage unit string, more compact wiring can be obtained, higher-density integration is realized, and the assembly process is simple and easy to use.
In one embodiment, the thickness of the channel layer 10 is not greater than the thickness of the depletion layer of the channel layer 10.
In one embodiment, an isolation layer 3 is disposed between adjacent gate electrodes 4. The isolation layer 3 is made of an insulating material and is used for isolating the adjacent gate electrodes 4.
Preferably, the material of the isolation layer 3 is SiO2Or dielectric constant ratio SiO2The dielectric constant of (2) is smaller.
In one embodiment, the first dielectric layer 7 is silicon oxide (SiO)2) Silicon nitride (Si)3N4) Silicon oxynitride (SiON), aluminum oxide (Al)2O3) Hafnium oxide (HfO)2) Zirconium oxide (ZrO)2) Titanium oxide (TiO)2) Lanthanum oxide (La)2O3) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)2) One or more of; the second dielectric layer 9 is silicon oxide (SiO)2) Silicon nitride (Si)3N4) Silicon oxynitride (SiON), aluminum oxide (Al)2O3) Hafnium oxide (HfO)2) Zirconium oxide (ZrO)2) Titanium oxide (TiO)2) Lanthanum oxide (La)2O3) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)2) And the like.
In one embodiment, the ferroelectric thin film layer 8 is hafnium oxide (HfO)2) Doped HfO2Zirconium oxide (ZrO)2) Or doped ZrO2One of (1); wherein the doped HfO2The doped element comprises one or more of silicon (Si), aluminum (Al), zirconium (Zr), lanthanum (La), cerium (Ce), strontium (Sr), lutetium (Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge) and nitrogen (N).
In one embodiment, the channel layer 10 is polysilicon (Si), poly-germanium (Ge), poly-silicon germanium (SiGe), or doped polysilicon (Si), doped poly-germanium (Ge), doped poly-silicon germanium (SiGe), with the doping elements being one or more of boron (B), phosphorous (P) and arsenic (As).
Fig. 3 is a schematic diagram of a U-shaped ferroelectric field effect transistor memory according to a third embodiment of the present invention.
As shown in fig. 3, the memory includes: a substrate 1, a conductive layer 2 and a plurality of U-shaped ferroelectric field effect transistor memory cell strings 5 provided in the second embodiment; the conductive layer 2 is arranged on the substrate 1; the second columnar structure of the U-shaped ferroelectric field effect transistor memory cell string 5 is embedded in the conducting layer 2, and the two first columnar structures of the U-shaped ferroelectric field effect transistor memory cell string 5 are positioned outside the conducting layer 2 and are perpendicular to the conducting layer 2; the separation layer 6 is disposed on the conductive layer 2, is located between the two columnar structures, and is used for separating the two structures.
Wherein, the gate electrodes 4 of multiple layers are arranged on the surface of the conducting layer 2, an isolating layer 3 is arranged between the adjacent gate electrodes 4, and the isolating layer 3 is arranged between the conducting layer 2 and the gate electrodes 4.
Preferably, the substrate 1 is a semiconductor substrate including, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), and the like.
Preferably, the conductive layer 2 includes, but is not limited to, a pn junction formed with the substrate 1, for example, if the substrate 1 is a p-type semiconductor, the conductive layer 2 is a heavily doped n-type semiconductor.
Preferably, the conductive layer 2 may also be a metal electrode, and is isolated from the substrate 1 by disposing an insulating material.
Preferably, the ferroelectric thin film layer 8 may be hafnium oxide (HfO)2) Or doped HfO2The doping element comprises one or more of silicon (Si), aluminum (Al), zirconium (Zr), lanthanum (La), cerium (Ce), strontium (Sr), lutetium (Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge), nitrogen (N) and the like, and zirconium oxide (ZrO)2) And doped ZrO2。
Preferably, the first dielectric layer 7 is silicon oxide (SiO)2) Silicon nitride (Si)3N4) Silicon oxynitride (SiON), aluminum oxide (Al)2O3) Hafnium oxide (HfO)2) Zirconium oxide (ZrO)2) Titanium oxide (TiO)2) Lanthanum oxide (La)2O3) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)2) One or more of (a).
Preferably, the second dielectric layer 9 is formed by silicon oxide (SiO) as the first dielectric layer2) Silicon nitride (Si)3N4) Silicon oxynitride (SiON), aluminum oxide (Al)2O3) Hafnium oxide (HfO)2) Zirconium oxide (ZrO)2) Titanium oxide (TiO)2) Lanthanum oxide (La)2O3) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)2) One or more of (a).
Preferably, the channel layer 10 is polysilicon (Si), poly-germanium (Ge), poly-silicon germanium (SiGe), or doped polysilicon (Si), doped poly-germanium (Ge), doped poly-silicon germanium (SiGe), and the doping element is one of boron (B), phosphorus (P), and arsenic (As).
Preferably, the thickness of the channel layer 10 is not greater than the thickness of its depletion layer.
Preferably, the filling layer 11 includes, but is not limited to, SiO2SiON and Si3N4。
Preferably, the isolation layer 3 is SiO2Or dielectric constant ratio SiO2Smaller insulating materials.
Preferably, the gate electrode 4 is any one of heavily doped polysilicon, a nitride metal electrode and tungsten (W).
Fig. 4 is a schematic flow chart of a method for manufacturing a memory according to a fourth embodiment of the invention.
As shown in FIG. 4, steps S1-S7 are included.
Therein, S1, a conductive layer 2 is formed on a substrate 1, see fig. 4 a.
In one embodiment, an ion implantation process may be used to implant ions into the surface of the substrate 1, the implanted ions being determined according to the substrate 1, so that the conductive layer 2 and the substrate 1 form a pn junction.
S2, at least one trench 12a is formed in the conductive layer 2, and a dielectric is deposited to fill the trench 12a, see fig. 4 b.
The trenches 12a may be formed in the conductive layer by a wet or dry etching process, and the number of the trenches 12a is determined according to the requirement. The profile of each trench 12a corresponds to the profile of a second columnar structure of a string of U-shaped ferroelectric field effect transistor memory cells of a U-shaped ferroelectric field effect transistor memory.
Wherein the deposited medium is SiO2SiON and Si3N4Is any one or more of thermal oxidation, Chemical Vapor Deposition (CVD), sputtering, and Atomic Layer Deposition (ALD).
S3: and sequentially overlapping and depositing an isolation layer 3 and a gate electrode 4 on the surface of the conductive layer 2 to obtain a stacked layer, wherein the number of layers of the gate electrode 4 is a preset number of layers.
Optionally, the isolating layer 3 deposited in S3 is SiO2Or dielectric constant ratio SiO2And a smaller insulating material, wherein the deposition method is any one of Chemical Vapor Deposition (CVD), sputtering, and Atomic Layer Deposition (ALD).
Optionally, the deposited control gate electrode layer 4 is any one of heavily doped polysilicon, a nitride metal electrode, and tungsten (W), and the deposition method is any one of Chemical Vapor Deposition (CVD), sputtering, Atomic Layer Deposition (ALD), and Metal Organic Chemical Vapor Deposition (MOCVD).
S4: two vias 13 are formed above each of the trenches 12a, the vias 13 extending through the stack and to the top of the trenches 12 a.
Optionally, a wet or dry etching process is used to form the via 13.
S5: the filled medium in the trench 12a is removed so that the two through holes 13 form a U-shaped through hole.
Optionally, the method for removing the filling medium is a wet etching process.
S6: and depositing a first dielectric layer 7, a ferroelectric thin film layer 8, a second dielectric layer 9 and a channel layer 10 on the inner wall of the U-shaped through hole in sequence.
Alternatively, the deposited ferroelectric thin film layer 8 may be hafnium oxide (HfO)2) Or doped HfO2The doping element comprises one or more of silicon (Si), aluminum (Al), zirconium (Zr), lanthanum (La), cerium (Ce), strontium (Sr), lutetium (Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge), nitrogen (N) and the like, and zirconium oxide (ZrO)2) And doped ZrO2The deposition method is Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD).
Optionally, depositingThe first dielectric layer 7 is silicon oxide (SiO)2) Silicon nitride (Si)3N4) Silicon oxynitride (SiON), aluminum oxide (Al)2O3)、HfO2、ZrO2Titanium oxide (TiO)2) Lanthanum oxide (La)2O3) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)2) And the like, the deposition method being a chemical vapor deposition method (CVD) or an atomic layer deposition method (ALD).
Optionally, the deposited second dielectric layer 9 is silicon oxide (SiO)2) Silicon nitride (Si)3N4) Silicon oxynitride (SiON), aluminum oxide (Al)2O3) Hafnium oxide (HfO)2) Zirconium oxide (ZrO)2) Titanium oxide (TiO)2) Lanthanum oxide (La)2O3) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)2) And the like, the deposition method being a chemical vapor deposition method (CVD) or an atomic layer deposition method (ALD).
Alternatively, the deposited channel layer 10 is polysilicon (Si), poly-germanium (Ge), poly-silicon germanium (SiGe), or doped polysilicon (Si), doped poly-germanium (Ge), doped poly-silicon germanium (SiGe), the doping element is one of boron (B), phosphorus (P), and arsenic (As), and the deposition method is Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD).
Alternatively, the deposited fill layer 11 includes, but is not limited to, SiO2SiON and Si3N4The deposition method is a chemical vapor deposition method (CVD) or an atomic layer deposition method (ALD).
S7: and forming a separation layer 6 in the middle of the U-shaped through hole, wherein the separation layer 6 at least penetrates through the gate electrode 4 in the laminated structure to form the U-shaped ferroelectric field effect transistor memory.
The separation layer 6 is, for example, a hole, or a hole is formed first and then an insulating material is deposited.
Preferably, the separation layer 6 may be formed on the middle portion of the U-shaped via hole by using a dry or wet etching process.
In one embodiment, after the step S6, before the step S7, the method further includes:
a filling layer 11 is deposited on the inner wall of the channel layer 10 to fill the via hole 13.
Wherein the deposited fill layer 11 includes, but is not limited to, SiO2SiON and Si3N4The deposition method is a chemical vapor deposition method (CVD) or an atomic layer deposition method (ALD).
The technical scheme of the invention has the following beneficial technical effects:
(1) the U-shaped memory cell string provided by the embodiment of the invention can obtain more compact wiring and realize higher density integration.
(2) The memory cell string is provided with the first dielectric layer 7 and the second dielectric layer 9, so that the ferroelectric film 8 is not directly contacted with the gate electrode layer 4 and the channel layer 10, element diffusion in the ferroelectric film 8 and interface reaction between the element diffusion and the gate electrode and the channel layer are avoided, the quality and performance of the ferroelectric film layer 8 and the memory cell are further ensured, the difference between the memory cells is reduced, and the reliability of the memory is improved.
(3) In the memory cell string provided by the embodiment of the invention, the filling layer 11 is added in the channel layer 10, which is equivalent to reducing the volume of the channel layer 10 in the device, so that defects in the channel layer 10 can be reduced, and the fatigue performance of the device and the difference between the devices can be improved.
(4) The preparation method provided by the embodiment of the invention avoids etching the first dielectric layer 7, the ferroelectric thin film layer 8 and the second dielectric layer 9, and can increase the reliability of the memory.
It is to be understood that the above-described embodiments of the present invention are merely illustrative of or explaining the principles of the invention and are not to be construed as limiting the invention. Therefore, any modification, equivalent replacement, improvement and the like made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. Further, it is intended that the appended claims cover all such variations and modifications as fall within the scope and boundaries of the appended claims or the equivalents of such scope and boundaries.
Claims (10)
1. A U-shaped ferroelectric field effect transistor memory cell string is characterized by comprising a U-shaped body formed by connecting two first columnar structures through a second columnar structure, a separation layer (6) and a plurality of layers of gate electrodes (4) arranged at intervals;
each layer of the gate electrode (4) is used for surrounding a first columnar structure of the U-shaped body;
the separation layer (6) penetrates through the multilayer gate electrode (4), is positioned in the opening of the U-shaped body, and is used for separating the two first columnar structures of the U-shaped body, so that the number of the storage units in the U-shaped storage unit string is twice of the number of the gate electrodes (4) in the U-shaped storage unit string;
each columnar structure is sequentially provided with a first dielectric layer (7), a ferroelectric thin film layer (8), a second dielectric layer (9) and a channel layer (10) from an outer layer to an inner layer;
the first dielectric layer (7) and the second dielectric layer (9) are used for isolating the ferroelectric thin film layer (8) so as to prevent the ferroelectric thin film layer (8) from being in direct contact with the channel layer (10) and the gate electrode (4), and the first dielectric layer (9) and the second dielectric layer (11) are used as seed layers or stress control layers for growth of the ferroelectric thin film layer (10) to promote generation of ferroelectric phases in the ferroelectric thin film layer (10) so as to enable the ferroelectric thin film layer (8) in the U-shaped ferroelectric field effect transistor memory cell string to realize a memory function.
2. The string of U-shaped ferroelectric field effect transistor memory cells of claim 1, further comprising:
and the filling layer (11) is arranged in the channel layer (10) and is used for filling the center of the columnar structure.
3. The string of U-shaped ferroelectric field effect transistor memory cells of claim 1 or 2,
the thickness of the channel layer (10) is not greater than the thickness of a depletion layer of the channel layer (10).
4. The string of U-shaped ferroelectric field effect transistor memory cells of claim 1 or 2,
and an isolation layer (3) is arranged between the adjacent gate electrodes (4).
5. The string of U-shaped ferroelectric field effect transistor memory cells of claim 1 or 2,
the first dielectric layer (7) is silicon oxide (SiO)2) Silicon nitride (Si)3N4) Silicon oxynitride (SiON), aluminum oxide (Al)2O3) Hafnium oxide (HfO)2) Zirconium oxide (ZrO)2) Titanium oxide (TiO)2) Lanthanum oxide (La)2O3) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)2) One or more of;
the second dielectric layer (9) is silicon oxide (SiO)2) Silicon nitride (Si)3N4) Silicon oxynitride (SiON), aluminum oxide (Al)2O3) Hafnium oxide (HfO)2) Zirconium oxide (ZrO)2) Titanium oxide (TiO)2) Lanthanum oxide (La)2O3) Hafnium silicon oxynitride (HfSiON), germanium oxide (GeO)2) And the like.
6. The string of U-shaped ferroelectric field effect transistor memory cells of claim 1 or 2,
the ferroelectric film layer (8) is hafnium oxide (HfO)2) Doped HfO2Zirconium oxide (ZrO)2) Or doped ZrO2One of (1); wherein the doped HfO2The doped element comprises one or more of silicon (Si), aluminum (Al), zirconium (Zr), lanthanum (La), cerium (Ce), strontium (Sr), lutetium (Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge) and nitrogen (N);
the channel layer (10) is made of polycrystalline silicon (Si), polycrystalline germanium (Ge), polycrystalline silicon germanium (SiGe) or doped polycrystalline silicon (Si), doped polycrystalline germanium (Ge) or doped polycrystalline silicon germanium (SiGe), and the doping elements are one or more of boron (B), phosphorus (P) and arsenic (As).
7. A U-shaped ferroelectric field effect transistor memory, comprising: -a substrate (1), -a conductive layer (2) and-a plurality of strings (5) of U-shaped ferroelectric field effect transistor memory cells according to any of claims 1-6;
the conductive layer (2) is arranged on the substrate (1);
the second columnar structures are embedded in the conducting layer (2), and the two first columnar structures are both positioned outside the conducting layer (2) and are perpendicular to the conducting layer (2);
the separation layer (6) is arranged on the conductive layer (2), is positioned between the two first columnar structures and is used for separating the two first columnar structures.
8. The U-shaped ferroelectric field effect transistor memory as claimed in claim 7,
the multi-layer gate electrodes (4) are arranged on the surface of the conducting layer (2), an isolating layer (3) is arranged between the adjacent gate electrodes (4), and the isolating layer (3) is arranged between the conducting layer (2) and the gate electrodes (4).
9. A preparation method of a U-shaped three-dimensional ferroelectric field effect transistor memory is characterized by comprising the following steps:
s1: forming a conductive layer (2) on a substrate (1);
s2: -forming at least one trench (12a) in the conductive layer (2) and depositing a medium to fill the trench (12 a);
s3: sequentially overlapping and depositing an isolation layer (3) and a gate electrode (4) on the surface of the conductive layer (2) to obtain a stacked layer, wherein the number of layers of the gate electrode (4) is a preset number of layers;
s4: forming two through holes (13) above each of said trenches (12a), said through holes (13) penetrating through said stack and up to the top of said trenches (12 a);
s5: removing the filled medium in the groove (12a) so that the two through holes (13) form a U-shaped through hole;
s6: depositing a first dielectric layer (7), a ferroelectric thin film layer (8), a second dielectric layer (9) and a channel layer (10) on the inner wall of the U-shaped through hole in sequence;
s7: and forming a separation layer (6) in the middle of the U-shaped through hole, wherein the separation layer (6) at least penetrates through the gate electrode (4) in the laminated structure to form the U-shaped ferroelectric field effect transistor memory.
10. The method according to claim 9, wherein after the step S6, before the step S7, the method further comprises:
a filler layer (11) is deposited on the inner wall of the channel layer (10) to fill the via hole (13).
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| PCT/CN2020/119410 WO2022000843A1 (en) | 2020-06-30 | 2020-12-01 | U-shaped ferroelectric field effect transistor memory cell string, memory, and preparation method |
| CN202110737900.4A CN113871395A (en) | 2020-06-30 | 2021-06-30 | Three-dimensional ferroelectric field effect transistor storage unit, memory and preparation method |
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| CN112687522A (en) * | 2020-12-24 | 2021-04-20 | 上海集成电路研发中心有限公司 | Amorphous germanium-silicon thin film structure, integrated structure and manufacturing method |
| WO2022000843A1 (en) * | 2020-06-30 | 2022-01-06 | 湘潭大学 | U-shaped ferroelectric field effect transistor memory cell string, memory, and preparation method |
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| US8692313B2 (en) * | 2011-04-29 | 2014-04-08 | SK Hynix Inc. | Non-volatile memory device and method for fabricating the same |
| EP3038141B1 (en) * | 2014-12-23 | 2019-08-28 | IMEC vzw | Method of reading a memory cell of a vertical ferroelectric memory device |
| KR20180131118A (en) * | 2017-05-31 | 2018-12-10 | 에스케이하이닉스 주식회사 | semiconductor device having ferroelectric layer and method of fabricating the same |
| CN110071116B (en) * | 2019-04-28 | 2021-07-27 | 中国科学院微电子研究所 | Three-dimensional NAND type ferroelectric memory, manufacturing method and operating method |
| CN111799262A (en) * | 2020-06-30 | 2020-10-20 | 湘潭大学 | U-shaped ferroelectric field effect transistor memory cell string, memory and preparation method |
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| WO2022000843A1 (en) * | 2020-06-30 | 2022-01-06 | 湘潭大学 | U-shaped ferroelectric field effect transistor memory cell string, memory, and preparation method |
| CN112687522A (en) * | 2020-12-24 | 2021-04-20 | 上海集成电路研发中心有限公司 | Amorphous germanium-silicon thin film structure, integrated structure and manufacturing method |
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Application publication date: 20201020 |