CN104637945B - Half floating-gate memory and its manufacturing method and half floating gate memory array - Google Patents
Half floating-gate memory and its manufacturing method and half floating gate memory array Download PDFInfo
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- 238000007667 floating Methods 0.000 title claims abstract description 106
- 230000015654 memory Effects 0.000 title claims abstract description 86
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000009933 burial Methods 0.000 claims abstract description 16
- 239000002019 doping agent Substances 0.000 claims description 87
- 238000009413 insulation Methods 0.000 claims description 54
- 238000005530 etching Methods 0.000 claims description 25
- 238000002955 isolation Methods 0.000 claims description 23
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 238000003860 storage Methods 0.000 abstract description 8
- 238000005516 engineering process Methods 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 87
- 238000009792 diffusion process Methods 0.000 description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 239000000463 material Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000010485 coping Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
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Abstract
Present invention is disclosed a kind of half floating-gate memories, including at least one U-shaped groove formed in semiconductor substrate, one burial source region formed in the semiconductor substrate of the U-shaped bottom portion of groove, two drain regions being respectively formed in the semiconductor substrate of U-shaped groove both sides, the control gate formed in the U-shaped groove and two floating booms for storing charge, a floating boom is chosen in the control gate and the combination in any one of drain region, two grid-control pn-junction diodes being respectively formed in the semiconductor substrate of U-shaped groove both sides being connected with the drain region and the floating boom.A kind of half floating gate memory array, the angle between neutrality line and corresponding active area are less than 80 degree, more half floating-gate memories can be produced in identical semiconductor substrate size, realize high density storage.The present invention manufactures half floating-gate memory and half floating gate memory array using self-registered technology, and technical process is simple, easily controllable.
Description
Technical field
The present invention relates to a kind of semiconductor memory, semicondctor storage array and its manufacturing methods, more particularly to a kind of
Half floating-gate memory and its manufacturing method and half floating gate memory array, belong to semiconductor memory technologies field.
Background technology
Semiconductor memory is widely used among various electronic products.Different application field is to semiconductor memory
Construction, performance and density have different requirements.For example, Static RAM（SRAM）Possess very high arbitrary access speed
With lower integration density, and the dynamic RAM of standard（DRAM）Then there is very high density and medium arbitrary access
Speed.
A kind of half floating-gate memory of vertical-channel is proposed in Chinese patent 201310158971.4, as shown in Figure 1, it is wrapped
The vertical channel region 401 formed in the semiconductor substrate 200 with the first doping type is included, vertical channel region 401 is this
The inversion layer that half floating-gate memory of vertical-channel is formed when being worked in semiconductor substrate 200.In semiconductor substrate
Source region 201 with second of doping type that bottom in 200, positioned at vertical channel region 401 is formed and positioned at vertical furrow
The drain region 202 with second of doping type that the top in road area 401 is formed.Cover source region 201, drain region 202 and vertical-channel
Area 401 is formed with first layer insulation film 203, and the first layer insulation film in drain region 202 is covered at the top of vertical channel region 401
Floating boom open area 204 there are one being formed in 203.On first layer insulation film 203 and covers vertical channel region 401 and float
There are one the floating booms 205 with the first doping type as charge-storage node for the formation of grid open area 204.Floating boom 205
With the doping type opposite with drain region 202, and the impurity in floating boom 205 can be diffused to by floating boom open area 204
In drain region 202 formed with the first doping type diffusion region 402, to by floating boom open area 204 floating boom 205 with
A p-n junction diode is formed between drain region 202.
Covering floating boom 205 and the p-n junction diode are formed with second layer insulation film 206.It insulate in the second layer thin
On film 206 and covering floating boom 205 and the p-n junction diode are formed with the control gate 207 of device.In control gate 207
Both sides are formed with grid curb wall 208.The doped region of doping type identical as drain region 202 is also respectively formed in drain region 202
210, the doping concentration of doped region 210 is apparently higher than the doping concentration in drain region 202, for reducing the Ohmic contact of device.Also wrap
It includes and is used to source region 201, control gate 207, drain region 202, semiconductor substrate 200 with external electrode being connected by what conductive material was formed
The contact 211 of the source region 201 connect, the contact 212 of control gate 207, the contact 213 in drain region 202 and semiconductor substrate 200
Contact 214.
But the floating boom 205 of half floating-gate memory of above-mentioned vertical-channel can only store a unit, and source region 201
Contact 211 be isolated with control gate 207 by grid curb wall 208, and to the Base top contact of semiconductor substrate 200, this can increase
The size of big device, reduces chip density.
Invention content
In view of the problems of the above-mentioned prior art, it is an object of the invention to propose half floating-gate memory of one kind and its system
Method and half floating gate memory array are made, so as to reduce the cellar area of half floating-gate memory, improves chip density.
To reach the above-mentioned purpose of the present invention, the present invention proposes a kind of half floating-gate memory, including at least one half
The U-shaped groove formed in conductor substrate, a burial source region formed in the semiconductor substrate of the U-shaped bottom portion of groove, two
A drain region being respectively formed in the semiconductor substrate of U-shaped groove both sides, the control formed in the U-shaped groove
The combination in the floating booms of grid and two for storing charge, the control gate and any one of drain region choose one it is described floating
Grid, two being respectively formed in the semiconductor substrate of U-shaped groove both sides is connected with the drain region and the floating boom
Grid-control pn-junction diode.
Preferably, half above-mentioned floating-gate memory, wherein including：
One semiconductor substrate with the first doping type；
One burial source region with second of doping type formed in the semiconductor substrate；
The bottom of one U-shaped groove formed in the semiconductor substrate, the U-shaped groove is less than the burial source region
Upper surface and higher than it is described bury source region lower surface；
Be respectively formed at the top of the semiconductor substrate of U-shaped groove both sides with second doping type
First dopant well and the second dopant well, first dopant well and the semiconductor substrate section shape buried between source region
At the first vertical channel region, second dopant well and the semiconductor substrate section buried between source region form second
Vertical channel region；
What is be respectively formed in first dopant well and the second dopant well close to U-shaped recess sidewall edge has
The first diffusion region and the second diffusion region of the first doping type；
The first drain region with second of doping type being respectively formed in first dopant well and the second dopant well
With the second drain region；
The formed in the inner surface of the U-shaped groove, covering first vertical channel region and the second vertical channel region
One layer of insulation film；
On the first layer insulation film, cover first vertical channel region and the second vertical channel region difference shape
At the first floating boom and the second floating boom with the first doping type as charge-storage node, first floating boom and institute
The connection of the first diffusion region is stated, second floating boom is connect with second diffusion region；
First floating boom in the U-shaped groove and the control gate formed between the second floating boom, the control gate point
It is not isolated by second layer insulation film between first floating boom and the second floating boom；
The control gate, second layer insulation film, the first diffusion region and first dopant well form one with the control
Grid processed are the first grid-control pn-junction diode of grid, the control gate, second layer insulation film, the second diffusion region and described second
Dopant well forms one using the control gate as the second grid-control pn-junction diode of grid.
Preferably, half above-mentioned floating-gate memory, wherein：First floating boom and first diffusion region and described the
Silicon nitride film of two floating booms with second diffusion region respectively by a layer thickness less than 1 nanometer is connect.
Preferably, half above-mentioned floating-gate memory, wherein：The first grid-control pn-junction diode and the second grid-control pn
Junction diode is grid-control pn-junction diode or the first grid-control pn-junction diode and second grid-control of planar structure
Pn-junction diode is the grid-control pn-junction diode of vertical structure.
Preferably, half above-mentioned floating-gate memory, wherein：The first described doping type is N-shaped, second of doping
Type is p-type；Alternatively, the first described doping type is p-type, second of doping type is N-shaped.
Preferably, half above-mentioned floating-gate memory, wherein：The semiconductor substrate is the silicon on silicon or insulator；Institute
State first layer insulation film and second layer insulation film be respectively silica, silicon nitride, silicon oxynitride, high-k it is exhausted
Any one in edge material or lamination between them；The floating boom is in the polysilicon, tungsten or titanium nitride of doping
Any one；The control gate is any one in polysilicon gate or metal gate.
A kind of half floating gate memory array being made of half above-mentioned floating-gate memory, wherein：Including multiple shallow by first
The active area of groove isolation construction isolation being mutually parallel, the multiple half floating boom storages formed in each active area
Device, the source line that a plurality of burial source region with half floating-gate memory is connected, a plurality of control with half floating-gate memory
The wordline that grid are connected, the bit line that a plurality of drain region with half floating-gate memory is connected, wherein each half floating boom is deposited
First drain region of reservoir connects different bit lines, the folder between every bit line and the corresponding active area with the second drain region
Angle is less than 80 degree.
Preferably, half above-mentioned floating gate memory array, wherein：Multiple described half formed in each active area
In floating-gate memory, it is isolated by the second fleet plough groove isolation structure between half adjacent floating-gate memory.
A kind of manufacturing method of half above-mentioned floating-gate memory, wherein including：
Fleet plough groove isolation structure is formed in the semiconductor substrate with the first doping type；
Burial source region and dopant well with second of doping type are formed in the semiconductor substrate；
Hard mask layer is formed on the surface of the semiconductor substrate；
The position of U-shaped groove is defined by photoetching process；
Fall the hard mask layer exposed as mask etching using photoresist, and is to cover with the hard mask layer after etching
Film etches the semiconductor substrate, U-shaped groove is formed in the semiconductor substrate, the bottom of the U-shaped groove is less than described
It buries the top of source region and is higher than the bottom for burying source region, and it is first that the U-shaped groove, which separates the dopant well,
Dopant well and the second dopant well；
First layer insulation film is formed in the inner surface of the U-shaped groove；
Covering is formed by first layer conductive film of the structure deposit with the first doping type, and to the first layer
Conductive film carve, and the upper surface of the remaining first layer conductive film should be higher than that first dopant well after etching
Bottom and the top for being less than first dopant well；
The first layer insulation film exposed is etched away, first dopant well and the second dopant well are exposed
Come；
Covering is formed by second layer conductive film of the structure deposit with the first doping type, and to the second layer
Conductive film carve, and the remaining second layer conductive film and first time conductive film form floating boom after etching, described
Floating boom is connect with first dopant well and second dopant well；
On the floating boom, the both sides at the top of U-shaped groove formation insulation film side wall；
Etch away the floating boom exposed along the edge of the insulation film side wall, the remaining floating boom after etching
The first floating boom and the second floating boom are formed, first floating boom is connect with first dopant well, second floating boom and described the
Two dopant wells connect；
Covering is formed by structure and forms second layer insulation film；
Third layer conductive film is formed on the second layer insulation film, and the third layer conductive film is carried out
Etching is to form control gate；
Etch away the second layer insulation film exposed；
Be respectively formed in first dopant well and the second dopant well the first drain region with second of doping type and
Second drain region.
Preferably, the manufacturing method of half above-mentioned floating-gate memory, wherein：In the semiconductor substrate, it is initially formed tool
The burial source region and dopant well for having second doping type re-form fleet plough groove isolation structure, alternatively, forming the control gate
Fleet plough groove isolation structure is re-formed later；
Preferably, the manufacturing method of half above-mentioned floating-gate memory, wherein：Formed the second layer conductive film it
Before, first one layer is grown respectively on the surface at the top of the U-shaped groove, first dopant well and the second dopant well that expose
Thickness is less than 1 nanometer of silicon nitride film.
Preferably, the manufacturing method of half above-mentioned floating-gate memory, wherein：The control gate is located in U-shaped groove and surpasses
Go out that U-shaped groove extends on first dopant well and the second dopant well or the control gate is only located at the U-shaped groove
It is interior.
Preferably, the manufacturing method of half above-mentioned floating-gate memory, wherein：Insulation film side coping be higher than or
Person is less than the top of first dopant well and the second dopant well.
Half floating-gate memory of the present invention and preparation method thereof and half floating gate memory array have effect following prominent：
1）Half floating-gate memory of the present invention is the embedded grid-control pn-junction diode in MOS transistor, includes at least two
Drain region and the control gate formed in U-shaped groove and two floating booms for storing charge, two in U-shaped groove two
The grid-control pn-junction diode being connected with drain region and floating boom being respectively formed in the semiconductor substrate of side, control gate with it is wherein arbitrary
The combination in one drain region can choose one of floating boom, so as to carry out the storage of dual-position unit；
2）Half floating-gate memory of the present invention uses vertical channel structure, can increase in the case where not increasing device area
Big grid length；
3）Half floating gate memory array of the present invention, the wherein angle between active area and bit line are less than 80 degree, Ke Yi
More half floating-gate memories are produced in identical semiconductor substrate size, realize high density storage；
4）The present invention manufactures half floating-gate memory and half floating gate memory array, technical process letter using self-registered technology
It is single, it is easily controllable.
Just attached drawing in conjunction with the embodiments below, the embodiment of the present invention is described in further detail, so that of the invention
Technical solution is more readily understood, grasps.
Description of the drawings
Fig. 1 is the sectional view of half floating-gate memory of the vertical-channel proposed in Chinese patent 201310158971.4；
Fig. 2 is the sectional view of one embodiment of half floating-gate memory of the present invention；
Fig. 3 is the sectional view of second embodiment of half floating-gate memory of the present invention；
Fig. 4 is the schematic top plan view of one embodiment of half floating gate memory array of the present invention；
Fig. 5 is the schematic top plan view of second embodiment of half floating gate memory array of the present invention；
Fig. 6 to Figure 15 is the work of one embodiment of the manufacturing method of half floating-gate memory as shown in Figure 2 of the present invention
Skill flow chart；
Figure 16 to Figure 18 is the work of one embodiment of the manufacturing method of half floating-gate memory as shown in Figure 3 of the present invention
Skill flow chart.
Specific implementation mode
The present invention is described in further detail with specific implementation mode below in conjunction with the accompanying drawings.In the figure for convenience
Illustrate, be exaggerated the thickness of layer and region, shown size does not represent actual size.Reference chart is that the idealization of the present invention is implemented
The schematic diagram of example, embodiment shown in the present invention should not be considered limited to the specific shape in region as shown in the figure, but wrap
Include deviation caused by obtained shape, such as manufacture.Such as the curve etched usually has the characteristics that bending or mellow and full,
But it in an embodiment of the present invention, is indicated with rectangle, the expression in figure is schematical, but this should not be construed as limiting
The scope of the present invention.Simultaneously in the following description, used term substrate can be understood as including just in technique processing
Semiconductor wafer, may be included in thereon prepared other film layers.
Fig. 2 is the sectional view of one embodiment of half floating-gate memory of the present invention, and Fig. 3 is half floating boom of the present invention
The sectional view of second embodiment of memory, as shown in Figures 2 and 3, half floating-gate memory of the invention includes：One has
The semiconductor substrate 300 of the first doping type, semiconductor substrate 300 can be silicon or be silicon on insulator.One
The burial source region 301 with second of doping type formed in semiconductor substrate 300.One shape in semiconductor substrate 300
At U-shaped groove（May be multiple U-shaped grooves, herein only by taking a U-shaped groove as an example）, the bottom of U-shaped groove, which is less than, to be covered
Bury the upper surface of source region 301 and higher than the lower surface for burying source region 301.On the top of the semiconductor substrate 300 of the both sides of U-shaped groove
The the first dopant well 302a and the second dopant well 302b, the first dopant well 302a with second of doping type that portion is respectively formed
The first vertical channel region, the second dopant well 302b and burial source region are formed with the semiconductor substrate section buried between source region 301
Semiconductor substrate section between 301 forms the second vertical channel region.In the first dopant well close to U-shaped recess sidewall edge
The diffusions of the first diffusion region 503a and second with the first doping type being respectively formed in 302a and the second dopant well 302b
Area 503b.The first leakage with second of doping type being respectively formed in the first dopant well 302a and the second dopant well 302b
Area 310a and the second drain region 310b.The first doping type is N-shaped, and second of doping type is p-type, alternatively, correspondingly, first
Kind doping type is p-type, and second of doping type is N-shaped.
In the first layer insulation that the inner surface of U-shaped groove, the first vertical channel region of covering and the second vertical channel region are formed
Film 304, first layer insulation film 304 be silica, silicon nitride, silicon oxynitride, high-k insulating materials or
Any one in lamination between them, high dielectric constant insulating material are including but not limited to hafnium oxide.In first layer
On insulation film 304, cover the conduct charge-storage node that the first vertical channel region and the second vertical channel region are respectively formed
The the first floating boom 306a and the second floating boom 306b, the first floating boom 306a and the first diffusion region 503a with the first doping type
Connection, the second floating boom 306b are connect with the second diffusion region 503b, the first floating boom 306a in U-shaped groove and the second floating boom 306b
Between the control gate 308 that is formed, control gate 308 and the first floating boom 306a and the second floating boom 306b are by second layer insulation film 311
Isolation.
Control gate 308 is any one in polysilicon gate or metal gate, and second layer insulation film 311 is titanium dioxide
Any one in silicon, silicon nitride, silicon oxynitride, the insulating materials of high-k or lamination between them, high dielectric
Constant insulator material is including but not limited to hafnium oxide.First floating boom 306a and the second floating boom 306b is the polycrystalline of doping
Any one in silicon, tungsten or titanium nitride.First floating boom 306a and the first diffusion region 503a and the second floating boom 306b and
Two diffusion region 503b the silicon nitride film by a layer thickness less than 1 nanometer can also be connected respectively, and silicon nitride film is conducive to
Holding of the charge in the first floating boom 306a and the second floating boom 306b.
One is formed in control gate 308, second layer insulation film 311, the first diffusion region 503a and the first dopant well 302a
It is the first grid-control pn-junction diode of grid with control gate 308；Control gate 308, second layer insulation film 311, the second diffusion region
503b and the second dopant well 302b form the second grid-control pn-junction diode that a control gate 308 is grid.
As shown in Fig. 2, the first grid-control pn-junction diode and the grid-control pn-junction that the second grid-control pn-junction diode is planar structure
Diode structure.As shown in figure 3, the first grid-control pn-junction diode and the second grid-control pn-junction diode may be vertical structure
Grid-control pn-junction diode structure.The structure of first grid-control pn-junction diode and the second grid-control pn-junction diode is by insulation film side wall
307 controls, insulation film side wall 307 can be any one in silicon oxide or silicon nitride.
The one embodiment for half floating gate memory array that Fig. 4 is made of half floating-gate memory of the present invention, such as Fig. 4
Shown, half floating gate memory array being made of half floating-gate memory of the present invention includes：It is multiple by the first shallow trench isolation knot
The active area of structure isolation being mutually parallel（7021-7024）, multiple half floating-gate memories formed in each active area are a plurality of
The source line being connected with the burial source region of half floating-gate memory（It is not shown）, a plurality of control gate with half floating-gate memory is connected
Wordline（7041-7043）, bit line that a plurality of drain region with half floating-gate memory is connected（7051-7058）, wherein Mei Geban
First drain region of floating-gate memory connects different bit lines with the second drain region, such as：The wordline of one of them half floating-gate memory
First drain region 310a of 7042 both sides connects bit line 7051, the second drain region 310b connects bit line 7052.Every bit line（7051-7058）With
Corresponding active area（7021-7024）Between angle should be less than 80 degree.
Second embodiment of half floating gate memory array that Fig. 5 is made of half floating-gate memory of the present invention, including：
Multiple active areas being mutually parallel being isolated by fleet plough groove isolation structure（7021-7024）, what is formed in each active area is more
A half floating-gate memory, a plurality of source line being connected with the burial source region of half floating-gate memory（It is not shown）, a plurality of and half floating boom
The wordline that the control gate of memory is connected（Illustrate wordline 7042）, a plurality of drain region with half floating-gate memory is connected
Bit line（7051-7058）, wherein the first drain region of each half floating-gate memory connects different bit lines, example with the second drain region
Such as：First drain region 310a of 7042 both sides of wordline of one of them half floating-gate memory connects bit line 7051, the second drain region 310b connects
Bit line 7052.Every bit line（7051-7058）With active area（7021-7024）Between angle should be less than 80 degree.Shown in Fig. 4
The difference of half floating gate memory array is：In multiple half floating-gate memories formed in each active area, half adjacent floating boom
It is isolated by the second fleet plough groove isolation structure between memory, for example, half floating-gate memory controlled by wordline 7042 is by second
Fleet plough groove isolation structure 801 and the second fleet plough groove isolation structure 802 are isolated with half adjacent floating-gate memory, as shown in Figure 5.
Half floating-gate memory of the present invention can be manufactured by a variety of methods, and Fig. 6 to Figure 15 is the as shown in Figure 2 of the present invention
The technological process of one embodiment of the manufacturing method of half floating-gate memory.
First, it is mixed with second as shown in fig. 6, being formed in the semiconductor substrate 300 with the first doping type
The burial source region 301 and dopant well 302 of miscellany type.
Next, forming fleet plough groove isolation structure in semiconductor substrate 300 with active area, which is known to industry
, when forming half floating gate memory array, can be formed multiple active by being mutually parallel of being isolated of fleet plough groove isolation structure
Area 901, being formed by active area 901 can be there are many pattern, and Fig. 7 a, 7b, 7c, 7d illustratively show four kinds of active area knots
The top view illustration of structure.
As described above, also can first be initially formed fleet plough groove isolation structure in semiconductor substrate 300, then served as a contrast again in semiconductor
Burial source region 301 and dopant well 302 with second of doping type are formed in bottom 300.
Next, forming one layer of hard mask layer on the surface of semiconductor substrate 300, hard mask layer is by silicon oxide film 503
With the formation of silicon nitride film 303, silicon oxide film 503 is for improving answering between silicon nitride film 303 and semiconductor substrate 300
Power relationship.Then the position of U-shaped groove is defined by photoetching process, and falls the nitridation exposed by mask etching of photoresist
Silicon thin film 303 is then that mask etching falls the silicon oxide film 503 exposed, and continues etching and partly lead with silicon nitride film 303
Body substrate 300 forms U-shaped groove 501 in semiconductor substrate 300, and the bottom of U-shaped groove 501, which should be less than, buries source region 301
Top is simultaneously higher than the bottom for burying source region 301, and is formed by U-shaped groove 501 and separates dopant well 302 for the first dopant well
302a and the second dopant well 302b, as shown in Figure 8.
Next, the inner surface in U-shaped groove 501 forms first layer insulation film 304, then covering is formed by structure
The first layer conductive film 305 with the first doping type is deposited, and first layer conductive film 305 carve, etching
The upper surface of remaining first layer conductive film 305 should be higher than that the bottom of the first dopant well 302a and be less than the first dopant well afterwards
The top of 302a, as shown in Figure 9.
Then, the first layer insulation film 304 exposed is etched away, floating boom is formed in first layer insulation film 304 and opens
Mouth 502a and 502b, to which the first dopant well 302a and the second dopant well 302b to be exposed, as shown in Figure 10.Optionally,
It, can be in the top of U-shaped groove, the first dopant well 302a exposed after etching away the first layer insulation film 304 exposed
The silicon nitride film that a layer thickness is less than 1 nanometer is grown with the surface of the second dopant well 302b, as shown in figure 11.Next, covering
Lid is formed by second layer conductive film of the structure deposit with the first doping type and is returned to second layer conductive film
It carves, remaining second layer conductive film forms floating boom 306 with first layer conductive film 305 after etching, and floating boom 306 and first adulterates
Trap 302a and the second dopant well 302b connections, as shown in figure 12.
Next, on floating boom 306, the top both sides of U-shaped groove 501 formation insulation film side wall 307, then along
The edge of insulation film side wall 307 etches away the floating boom 306 exposed, and remaining floating boom 306 forms the first floating boom after etching
306a and the second floating boom 306b, the first floating boom 306a are connect with the first dopant well 302a, the second floating boom 306b and the second dopant well
302b connections, as shown in figure 13.
Next, etching away silicon nitride film 303 and silicon oxide film 503.Material based on first layer insulation film 304
Material, in etch nitride silicon thin film 303 and silicon oxide film 503, the first layer insulation film 304 exposed can be etched
Fall, can also be retained, in the present embodiment by taking the first layer insulation film 304 exposed is etched away as an example.Then it covers
It is formed by structure and forms second layer insulation film 311, then form third layer conductive thin on second layer insulation film 311
Then film performs etching third layer conductive film by photoetching process and etching technics to form control gate 308, control gate
308 exceed U-shaped groove 501 and extend on the first dopant well 302a and the second dopant well 302b, as shown in figure 14.
Next, forming grid curb wall 309 in the both sides of control gate 308, grid curb wall structure is the knot known to industry
Structure.The second layer insulation film 311 exposed is etched away along the edge of grid curb wall 309 later, then passes through ion implanting
Method be respectively formed the first drain region with second of doping type in the first dopant well 302a and the second dopant well 302b
310a and the second drain region 310b, finally carries out high-temperature annealing process, at this point, miscellaneous in the first floating boom 306a and the second floating boom 306b
Matter can diffuse in the first dopant well 302a and the second dopant well 302b and form the first diffusion region 503a and the second diffusion region respectively
503b, as shown in figure 15.Conventional metal-oxide-semiconductor postchannel process can be finally carried out, electrode isolation is carried out and forms metal interconnection.
Figure 16 to Figure 18 is the work of one embodiment of the manufacturing method of half floating-gate memory as shown in Figure 3 of the present invention
Skill flow.
Under conditions of not forming fleet plough groove isolation structure, carries out the processing step as shown in Fig. 6 to Figure 12 and formed as schemed
Then structure shown in 12 covers structure as shown in figure 12, on floating boom 306, the top both sides of U-shaped groove 501 are formed
Insulation film side wall 307 passes through the control to etching condition so that insulation film side wall 307 is by the first dopant well 302a and
Two dopant well 302b are exposed.As shown in figure 16.
Next, the floating boom 306 exposed is etched away along the edge of insulation film side wall 307, it is remaining floating after etching
Grid 306 form the first floating boom 306a and the second floating boom 306b, and the first floating boom 306a is connect with the first dopant well 302a, the second floating boom
306b is connect with the second dopant well 302b.Then silicon nitride film 303 and silicon oxide film 503 are etched away, institute's shape is then covered
At structure form second layer insulation film 311, third layer conductive film is then formed on second layer insulation film 311,
Then third layer conductive film carve to form control gate 308, control gate 308 is only located in U-shaped groove, such as Figure 17 institutes
Show.
Next, forming fleet plough groove isolation structure in semiconductor substrate 300.It is initially formed control gate 308 and re-forms shallow ridges
The advantages of recess isolating structure is, when forming control gate 308 can directly to third layer conductive film carry out back quarter without
Photoetching process is carried out, technical process is simple.
Next, etching away the second layer insulation film 311 exposed, then mixed first by the method for ion implanting
The first drain region 310a with second doping type and the second drain region are respectively formed in miscellaneous trap 302a and the second dopant well 302b
310b finally carries out high-temperature annealing process, at this point, the impurity in the first floating boom 306a and the second floating boom 306b can diffuse to respectively
The first diffusion region 503a and the second diffusion region 503b are formed in first dopant well 302a and the second dopant well 302b, such as Figure 18 institutes
Show.Conventional metal-oxide-semiconductor postchannel process can be finally carried out, electrode isolation is carried out and forms metal interconnection.
Still there are many embodiment, all technical sides formed using equivalents or equivalent transformation by the present invention
Case is within the scope of the present invention.
Claims (5)
1. a kind of manufacturing method of half floating-gate memory, which is characterized in that described method includes following steps：
Fleet plough groove isolation structure is formed in the semiconductor substrate with the first doping type；
Burial source region and dopant well with second of doping type are formed in the semiconductor substrate；
Hard mask layer is formed on the surface of the semiconductor substrate；
The position of U connected in stars is defined by photoetching process；
Fall the hard mask layer exposed as mask etching using photoresist, and is carved by mask of the hard mask layer after etching
The semiconductor substrate is lost, forms U connected in stars in the semiconductor substrate, the bottom of the U-shaped groove is less than the burial
The top of source region is simultaneously higher than the bottom for burying source region, and the U-shaped groove separates the dopant well for the first doping
Trap and the second dopant well；
First layer insulation film is formed in the inner surface of the U connected in stars；
Covering is formed by first layer conductive film of the structure deposit with the first doping type, and to first layer conduction
Film carve, and the upper surface of the remaining first layer conductive film should be higher than that the bottom of first dopant well after etching
And less than the top of first dopant well；The first layer insulation film exposed is etched away, by first dopant well
It is exposed with the second dopant well；Covering is formed by second layer conductive film of the structure deposit with the first doping type,
And the second layer conductive film carve, the remaining second layer conductive film and first time conductive film after etching
Floating boom is formed, the floating boom is connect with first dopant well and second dopant well；
On the floating boom, the both sides at the top of U connected in stars formation insulation film side wall；
The floating boom exposed is etched away along the edge of the insulation film side wall, the remaining floating boom is formed after etching
First floating boom and the second floating boom, first floating boom are connect with first dopant well, and second floating boom is mixed with described second
Miscellaneous trap connection；Covering is formed by structure and forms second layer insulation film；Third is formed on the second layer insulation film
Layer conductive film, and the third layer conductive film is performed etching to form control gate；Etch away described second exposed
Layer insulation film；
The first drain region and second with second of doping type is respectively formed in first dopant well and the second dopant well
Drain region.
2. the manufacturing method of half floating-gate memory according to claim 1, it is characterised in that：In the semiconductor substrate
It is interior, it is initially formed burial source region and dopant well with second doping type and re-forms fleet plough groove isolation structure, alternatively, being formed
Fleet plough groove isolation structure is re-formed after the control gate.
3. according to the manufacturing method of half floating-gate memory described in claim 1, it is characterised in that：Forming the second layer
Before conductive film, first on the top of the U connected in stars, the surface of first dopant well and the second dopant well that expose
Growth a layer thickness is less than 1 nanometer of silicon nitride film respectively.
4. according to the manufacturing method of half floating-gate memory described in claim 1, it is characterised in that：The control gate is located at U-shaped
It in groove and is extended on first dopant well and the second dopant well beyond U connected in stars or the control gate is only located at
In the U connected in stars.
5. the manufacturing method of half floating-gate memory according to claim 1, it is characterised in that：The insulation film side wall
Top is higher or lower than the top of first dopant well and the second dopant well.
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| CN106711148B (en) * | 2016-11-17 | 2019-05-03 | 武汉新芯集成电路制造有限公司 | A kind of vertical structure floating gate flash memory and its manufacturing method |
| CN106356373B (en) * | 2016-11-21 | 2019-01-18 | 武汉新芯集成电路制造有限公司 | Vertical channel type floating gate flash memory and its manufacturing method |
| CN108649032A (en) * | 2017-03-15 | 2018-10-12 | 上海格易电子有限公司 | A kind of storage unit and nonvolatile memory |
| CN107665894B (en) * | 2017-09-12 | 2020-04-28 | 复旦大学 | Semi-floating gate memory based on two-dimensional semiconductor material and preparation method thereof |
| CN108447866B (en) * | 2018-03-06 | 2019-03-26 | 武汉新芯集成电路制造有限公司 | Floating-gate device and preparation method thereof |
| CN115692505A (en) * | 2022-11-21 | 2023-02-03 | 武汉新芯集成电路制造有限公司 | Semiconductor device, method of manufacturing the same, and method of operating the same |
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| CN1459850A (en) * | 2002-05-24 | 2003-12-03 | 南亚科技股份有限公司 | Separated grid electrode type quick flashing storage and its manufacturing method |
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