CN108649032A - A kind of storage unit and nonvolatile memory - Google Patents
A kind of storage unit and nonvolatile memory Download PDFInfo
- Publication number
- CN108649032A CN108649032A CN201710153121.3A CN201710153121A CN108649032A CN 108649032 A CN108649032 A CN 108649032A CN 201710153121 A CN201710153121 A CN 201710153121A CN 108649032 A CN108649032 A CN 108649032A
- Authority
- CN
- China
- Prior art keywords
- floating boom
- storage unit
- control gate
- region
- drain region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
Abstract
The invention discloses a kind of storage unit and nonvolatile memories, wherein storage unit includes：Semiconductor substrate, including active area；Source region is located in the semiconductor substrate of active area；Grid region, include on source region and the first floating boom of mutually insulated, the second floating boom and control gate, wherein, first floating boom and the second floating boom are at least partially disposed in semiconductor substrate and are located at the both ends in grid region, control gate has face region with the first floating boom and the second floating boom respectively, surface, second floating boom of first floating boom far from the second floating boom side are formed with integrated tunnel oxide between surface and the first floating boom and source region far from the first floating boom side between the second floating boom and source region；First drain region and the second drain region, are located in the semiconductor substrate of the active area of grid region both sides.The present invention solves the problems, such as that storage unit footprint area is big, can reduce the size of nonvolatile memory.
Description
Technical field
The present embodiments relate to technical field of semiconductor memory more particularly to a kind of storage units and non-volatile memories
Device.
Background technology
The grid region of traditional NOR flash memory storage unit is between source region and drain region, the semiconductor layer between source region and drain region
Raceway groove can be formed.When being programmed to NOR flash memory, the control gate of storage unit and drain region apply the high electric of certain time simultaneously
Pressure, raceway groove conducting, and under the action of transverse electric field and longitudinal electric field, the carrier in raceway groove can be injected by thermoelectron, jump
Into floating boom.Since thermoelectron injection requires storage unit to be operated under high-voltage state, the ditch of storage unit
Road length cannot be too short, limits storage unit further reducing in orientation.
Invention content
In view of this, the purpose of the present invention is to propose to a kind of storage unit and nonvolatile memory, it is single to reduce storage
Area shared by member reduces the size of nonvolatile memory.
To achieve the above object, the present invention adopts the following technical scheme that：
On the one hand, an embodiment of the present invention provides a kind of storage units, including：
Semiconductor substrate, including active area；
Source region is located in the semiconductor substrate of the active area；
Grid region includes on the source region and the first floating boom of mutually insulated, the second floating boom and control gate, wherein
First floating boom and second floating boom are at least partially disposed in the semiconductor substrate and are located in the grid region
Both ends, the control gate have face region, first floating boom separate with first floating boom and second floating boom respectively
The surface of second floating boom side, second floating boom surface and described first far from first floating boom side are floated
Between grid and the source region integrated tunnel oxide is formed between second floating boom and the source region；
First drain region and the second drain region are located in the semiconductor substrate of the active area of the grid region both sides.
Further, first floating boom and second floating boom upper surface and the semiconductor substrate upper surface flush.
Further, the control gate includes at least the first control gate, and first control gate is located at first floating boom
On second floating boom.
Further, the control gate further includes the second control gate being electrically connected with first control gate, and described second
Control gate extends from first control gate to the source region, and part is located in first floating boom and second floating boom
Between.
Further, the wordline same layer of first control gate and nonvolatile memory is arranged, and first control
Grid are integrally formed with the wordline.
Further, the thickness of first floating boom and second floating boom is 100~350nm.
Further, along the arragement direction in first drain region, the grid region and second drain region, the grid region
Width is 20~80nm.
Further, it is covered with insulating layer in the control gate and the semiconductor substrate；
The first bit line and the second bit line of the mutually insulated of nonvolatile memory are provided on the insulating layer；
First drain region is electrically connected to first bit line by the first bit line contact hole, and second drain region passes through
Two bit line contact holes are electrically connected to second bit line.
Further, it is provided with interlayer dielectric layer between the control gate and first floating boom and the second floating boom.
Further, the interlayer dielectric layer includes the first oxide layer stacked gradually, nitration case and the second oxide layer.
Further, first control gate both sides are formed with side wall.
On the other hand, an embodiment of the present invention provides a kind of nonvolatile memories, including：
Multiple storage units as described in above-mentioned one side being arranged in array；
It is a plurality of to extend wordline arrange along column direction along line direction, every wordline and with storage unit described in a line
Control gate is electrically connected；
A plurality of to extend the bit line arranged along line direction along column direction, storage unit has two bit lines described in each column,
The first drain region and the second drain region of each storage unit are electrically connected to different bit lines.
Further, a drain region is shared between two storage units of the column direction arbitrary neighborhood, and altogether
Drain region is electrically connected to same bit line by a bit line contact hole.
The beneficial effects of the invention are as follows：Storage unit provided by the invention and nonvolatile memory, by will be non-volatile
Property memory in the floating boom of storage unit be divided into first floating boom and the second floating boom at the independent both ends in the grid region, and first is floating
Grid and the second floating boom are at least partially arranged in semiconductor substrate, in surface of first floating boom far from the second floating boom side, second
Floating boom forms tunnelling between surface and the first floating boom and source region far from the first floating boom side between the second floating boom and source region
Oxide layer, and the first drain region and the second drain region are respectively formed in the semiconductor substrate of grid region both sides, it can be in existing storage unit
Two independent storage units are formed in shared region, and when non-volatile memory operation, between the first drain region and source region
And second can be respectively formed vertical-channel between drain region and source region, it is vertical to which the horizontal channel of existing storage unit to be converted to
Straight flute road, i.e., with vertical channel depth instead of the length of former horizontal channel, and then the face that storage unit can be made to occupy
Product is substantially reduced on the length direction of former horizontal channel.Therefore, storage unit provided in an embodiment of the present invention and non-volatile
Memory realizes a kind of nonvolatile memory of very high-density so that nonvolatile memory moves towards 45nm or 32nm very
It is become possible to smaller szie.
Description of the drawings
Exemplary embodiments of the present invention will be described in detail referring to the drawings by general below, makes those skilled in the art
The above-mentioned and other feature and advantage for becoming apparent from the present invention, in attached drawing：
Fig. 1 a are the planar structure schematic diagrams of the memory cell array of existing NOR type flash memory；
Fig. 1 b be in Fig. 1 a NOR type flash memory along the cross-sectional view of hatching A-A '；
Fig. 2 is the cross-sectional view for the storage unit that the embodiment of the present invention one provides；
Fig. 3 is the cross-sectional view of storage unit provided by Embodiment 2 of the present invention；
Fig. 4 is the cross-sectional view for the storage unit that the embodiment of the present invention three provides；
Fig. 5 a are the planar structure schematic diagrams of the memory cell array for the NOR type flash memory that the embodiment of the present invention four provides；
Fig. 5 b be in Fig. 5 a NOR type flash memory along the cross-sectional view of hatching B-B '；
Fig. 5 c be in Fig. 5 a NOR type flash memory along the cross-sectional view of hatching C-C '.
Specific implementation mode
Technical solution to further illustrate the present invention below with reference to the accompanying drawings and specific embodiments.It is appreciated that
It is that specific embodiment described herein is used only for explaining the present invention rather than limitation of the invention.It further needs exist for illustrating
, only the parts related to the present invention are shown for ease of description, in attached drawing rather than entire infrastructure.
Fig. 1 a are the planar structure schematic diagrams of the memory cell array of existing NOR type flash memory；Fig. 1 b are NOR type in Fig. 1 a
Cross-sectional view of the flash memory along hatching A-A '.In conjunction with Fig. 1 a and Fig. 1 b, which includes multiple be arranged in array
Storage unit 10 (two adjacent storage unit As 1 of such as same row and B1)；A plurality of extend along line direction is arranged along column direction
Wordline 20, every wordline 20 are electrically connected with the control gate 16 of same line storage unit 10；It is a plurality of to extend along line direction along column direction
The bit line 30 of arrangement, every bit line 30 are electrically connected by bit line contact hole 40 with the drain region D of same array storage unit 10.Wherein,
Each storage unit may include semiconductor substrate 11, including active area 12；Grid region, including stack gradually in semiconductor substrate 11 it
On tunnel oxide 13, floating boom 14, interlayer dielectric layer 15 and control gate 16；Source region S and drain region D, is located at grid region both sides
Active area 12 semiconductor substrate 11 in.When being programmed to NOR type flash memory, the control gate 16 of storage unit 10 and drain region
D applies the high voltage of certain time simultaneously, the horizontal channel conducting between source region S and drain region D, and in transverse electric field and longitudinal electricity
Under the action of, the carrier in horizontal channel can be injected by thermoelectron, in jump to floating boom 14.Due to the hair of thermoelectron injection
Life requires storage unit 10 to be operated under high-voltage state, therefore the channel length of storage unit 10 cannot be too short, limits and deposits
Storage unit further reducing in orientation limits the diminution of grid region width W (80~130nm).
To solve the above problems, the present invention proposes a kind of storage unit and nonvolatile memory, the solution of the present invention
Applicable a plurality of types of nonvolatile memories can illustratively illustrate, and be embodied by taking NOR type flash memory as an example
Under such as.
Embodiment one
Fig. 2 is the cross-sectional view for the storage unit that the embodiment of the present invention one provides.As shown in Fig. 2, the storage list
Member includes：
Semiconductor substrate 101, including active area (not shown)；
Source region 103 is located in the semiconductor substrate 101 of active area；
Grid region includes on source region 103 and the first floating boom 104 of mutually insulated, the second floating boom 105 and control gate
106, wherein the first floating boom 104 and the second floating boom 105 are at least partially disposed in semiconductor substrate 101 and are located in grid region
Both ends, control gate 106 has a face region with the first floating boom 104 and the second floating boom 105 respectively, and the first floating boom 104 is far from the
The surface of two floating booms, 105 side, the second floating boom 105 surface and the first floating boom 104 and source far from 104 side of the first floating boom
Integrated tunnel oxide 107 is formed between area 103 between the second floating boom 105 and source region 103；
First drain region 108 and the second drain region 109, are located in the semiconductor substrate 101 of the active area of grid region both sides.
Illustratively, as shown in Fig. 2, first floating boom 104 and the second floating boom 105 of the present embodiment can partly be located at semiconductor
In substrate 101, the thickness of first floating boom 104 and the second floating boom 105 can be 100~350nm；Control gate 106 includes at least
First control gate 1061, the first control gate 1061 is located on the first floating boom 104 and the second floating boom 105, and the first control gate
1061 lower surface has face region with the upper surface of the first floating boom 104 and the second floating boom 105.
The storage unit of the present embodiment can be divided into two independent sub- storage units, specifically, a sub- storage unit
Including at least the first control gate 1061, the first floating boom 104, source region 103, tunnel oxide 107 and the first drain region 108；Another
Sub- storage unit includes at least the first control gate 1061, the second floating boom 105, source region 103, tunnel oxide 107 and the second drain region
109.Two independent storage units can be formed in the region shared by existing storage unit as a result, are substantially increased non-volatile
The density of property memory.
When NOR type flash memory works, between the first drain region 108 and source region 103 and between the second drain region 109 and source region 103
It can be respectively formed vertical-channel, it is deep with vertical raceway groove to which the horizontal channel of existing storage unit is converted to vertical-channel
The length instead of former horizontal channel is spent, and then the area that storage unit occupies can be made in the length direction of former horizontal channel
On further reduce, in the present embodiment, along the arragement direction in the first drain region 108, grid region and the second drain region 109, the width in grid region
Degree can be contracted to 20~80nm, you can so that size reduction of the storage unit on the length direction of former horizontal channel.
In addition, in the present embodiment, interlayer Jie is may be provided between control gate 106 and the first floating boom 104 and the second floating boom 105
Matter layer 110, so that 105 mutually insulated of control gate 106, the first floating boom 104 and the second floating boom.The interlayer dielectric layer 110 may include
The first oxide layer, nitration case and the second oxide layer stacked gradually.
The storage unit that the embodiment of the present invention one provides, by the way that the floating boom of storage unit in nonvolatile memory to be divided into
Independent the first floating boom and the second floating boom positioned at both ends in grid region, and the first floating boom and the second floating boom are at least partially arranged at half
In conductor substrate, on surface, second floating boom surface far from first floating boom side of first floating boom far from the second floating boom side, with
And first form tunnel oxide between floating boom and source region between the second floating boom and source region, and served as a contrast in the semiconductor of grid region both sides
It is respectively formed the first drain region and the second drain region in bottom, two independent storages can be formed in the region shared by existing storage unit
Unit, and when non-volatile memory operation, shape can be distinguished between the first drain region and source region and between the second drain region and source region
It is substituted with vertical channel depth at vertical-channel to which the horizontal channel of existing storage unit is converted to vertical-channel
The length of former horizontal channel, and then can make the area that storage unit occupies on the length direction of former horizontal channel significantly
It reduces.Therefore, storage unit provided in an embodiment of the present invention and nonvolatile memory, realize a kind of very high-density it is non-easily
The property lost memory so that nonvolatile memory moves towards 45nm or 32nm even smaller szies and becomes possible to.
Embodiment two
Fig. 3 is the cross-sectional view of storage unit provided by Embodiment 2 of the present invention.The present embodiment is with embodiment one
Based on optimize, the first floating boom and the second floating boom are just all placed in semiconductor substrate, i.e. the first floating boom and second
Floating boom upper surface and semiconductor substrate upper surface flush, to increase vertical-channel depth.As shown in figure 3, the storage unit can wrap
It includes：
Semiconductor substrate 101, including active area (not shown)；
Source region 103 is located in the semiconductor substrate 101 of active area；
Grid region includes on source region 103 and the first floating boom 104 of mutually insulated, the control of the second floating boom 105 and first
Grid 1061, wherein the first floating boom 104 and 105 upper surface of the second floating boom and 101 upper surface flush of semiconductor substrate and be located at
Both ends in grid region, the lower surface of the first control gate 1061 have face with the upper surface of the first floating boom 104 and the second floating boom 105
Region, surface of first floating boom 104 far from 105 side of the second floating boom, the second table of the floating boom 105 far from 104 side of the first floating boom
Between face and the first floating boom 104 and source region 103 integrated tunnel oxide is formed between the second floating boom 105 and source region 103
Layer 107；
First drain region 108 and the second drain region 109, are located in the semiconductor substrate 101 of the active area of grid region both sides.
In the present embodiment, the wordline (not shown) of the first control gate 1061 and nonvolatile memory can same layer set
It sets, optionally, the first control gate 1061 is integrally formed with wordline, to save etching technics.
Illustratively, it is covered with insulating layer 111 in above-mentioned first control gate 1061 and semiconductor substrate 101；Insulating layer 111
On be provided with the bit line 300 of nonvolatile memory, include the first bit line 301 and the second bit line 302 of mutually insulated；First leakage
Area 108 is electrically connected to the first bit line 301 by the first bit line contact hole 401, and the second drain region 109 passes through second wire contact hole
402 are electrically connected to the second bit line 302.
In addition, 1061 both sides of the first control gate in the present embodiment can be formed with side wall 112, the first control is preferably isolated
Grid 1061 processed and the first drain region 108 and the second drain region 109 influence each other.
The detail content of not detailed description in the present embodiment can refer to above-described embodiment, and details are not described herein again.
Storage unit provided in this embodiment, setting floating boom upper surface and semiconductor substrate upper surface flush, keep floating boom complete
Portion is placed in semiconductor substrate, can increase the depth of vertical-channel, and it is long in former horizontal channel can to further reduce storage unit
Spend the size on direction.
Embodiment three
Fig. 4 is the cross-sectional view for the storage unit that the embodiment of the present invention three provides.The present embodiment is with embodiment two
Based on optimize, above-mentioned control gate further includes the second control gate being electrically connected with the first control gate, and the second control gate is from
One control gate extends to source region, and part is located among the first floating boom and the second floating boom.Specifically, as shown in figure 4, the storage list
Member may include：
Semiconductor substrate 101, including active area (not shown)；
Source region 103 is located in the semiconductor substrate 101 of active area；
Grid region includes the first floating boom 104, the second floating boom 105 and the first control gate 1061 on source region 103 and
Two control gates 1062, wherein 1061 mutually insulated of the first floating boom 104, the second floating boom 105 and the first control gate, the first control gate
1061 and second control gate 1062 be electrically connected；Second control gate 1062 extends from the first control gate 1061 to source region 103, and part
Among the first floating boom 104 and the second floating boom 105；First floating boom 104 and 105 upper surface of the second floating boom and semiconductor substrate
101 upper surface flush and the both ends in grid region are located at, the lower surface of the first control gate 1061 and the first floating boom 104 and second
The upper surface of floating boom 105 has face region, the both sides of the second floating boom 1062 opposite with the first floating boom 104 and the second floating boom 105
Side have face region；Surface of first floating boom 104 far from 105 side of the second floating boom, the second floating boom 105 are far from the first floating boom
Between the surface of 104 sides and the first floating boom 104 and source region 103 one is formed between the second floating boom 105 and source region 103
The tunnel oxide 107 of body；
First drain region 108 and the second drain region 109, are located in the semiconductor substrate 101 of the active area of grid region both sides.
The detail content of not detailed description in the present embodiment can refer to above-described embodiment, and details are not described herein again.
Storage unit provided in this embodiment, control gate further include the second control gate being electrically connected with the first control gate, the
Two control gates extend from the first control gate to source region, and part is located among the first floating boom and the second floating boom, increases control gate
With the facing area of the first floating boom and the second floating boom, and then coupling efficiency is improved, keeps storage unit normal erasable, improve
The wiping/writing performance of storage unit.
Example IV
This implementation provides a kind of nonvolatile memory, and optionally, which can be that NOR type is dodged.
Fig. 5 a are the planar structure schematic diagrams of the memory cell array for the NOR type flash memory that the embodiment of the present invention four provides；Fig. 5 b are Fig. 5 a
Cross-sectional view of the middle NOR type flash memory along hatching B-B '；Fig. 5 c are NOR type flash memory cuing open along hatching C-C ' in Fig. 5 a
Face structural schematic diagram.As illustrated in figs. 5 a-5 c, the nonvolatile memory of the present embodiment may include：
Multiple storage units 100 as described in above-described embodiment being arranged in array, each storage unit 100 may include two
A sub- storage unit (such as A2 and B2)；
It is a plurality of to extend the wordline 200 arranged along column direction, the control of every wordline and same line storage unit 100 along line direction
Grid electrical connection processed；
It is a plurality of to extend the bit line 300 arranged along line direction along column direction, there are two bit lines 300 per array storage unit 100,
Such as the first bit line 301 and the second bit line 302, the first drain region 108 and the second drain region 109 of each storage unit 100 are electrically connected to
Different bit lines, such as the first drain region 108 are electrically connected to the first bit line 301, and the second drain region 109 is electrically connected to the second bit line 301.
Optionally, a drain region is shared between two storage units of column direction arbitrary neighborhood, and shared drain region is logical
It crosses a bit line contact hole and is electrically connected to same bit line.For example, in conjunction with Fig. 5 a-5c, same row adjacent two storage units M and N
Between share the second drain region 109, the second drain region 109 is electrically connected to the second bit line 302 by second wire contact hole 402.
The nonvolatile memory that the embodiment of the present invention four is provided, including storage list that the embodiment of the present invention is provided
Member has corresponding function and advantageous effect.
Note that above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The present invention is not limited to specific embodiments described here, can carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out to the present invention by above example
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
May include other more equivalent embodiments, and the scope of the present invention is determined by scope of the appended claims.
Claims (13)
1. a kind of storage unit, which is characterized in that including：
Semiconductor substrate, including active area；
Source region is located in the semiconductor substrate of the active area；
Grid region includes on the source region and the first floating boom of mutually insulated, the second floating boom and control gate, wherein described
First floating boom and second floating boom are at least partially disposed at the both ends in the semiconductor substrate and being located in the grid region,
The control gate has a face region with first floating boom and second floating boom respectively, and first floating boom is far from described the
The surface of two floating boom sides, second floating boom surface and first floating boom and institute far from first floating boom side
It states and is formed with integrated tunnel oxide between second floating boom and the source region between source region；
First drain region and the second drain region are located in the semiconductor substrate of the active area of the grid region both sides.
2. storage unit according to claim 1, which is characterized in that first floating boom and second floating boom upper surface
With the semiconductor substrate upper surface flush.
3. storage unit according to claim 2, which is characterized in that the control gate includes at least the first control gate, institute
The first control gate is stated to be located on first floating boom and second floating boom.
4. storage unit according to claim 3, which is characterized in that the control gate further includes and first control gate
Second control gate of electrical connection, second control gate extend from first control gate to the source region, and part is located at institute
It states among the first floating boom and second floating boom.
5. storage unit according to claim 3, which is characterized in that first control gate and nonvolatile memory
Wordline same layer is arranged, and first control gate is integrally formed with the wordline.
6. storage unit according to claim 2, which is characterized in that the thickness of first floating boom and second floating boom
For 100~350nm.
7. storage unit according to claim 2, which is characterized in that along first drain region, the grid region and described
On the arragement direction in two drain regions, the width in the grid region is 20~80nm.
8. storage unit according to claim 2, which is characterized in that covered in the control gate and the semiconductor substrate
There is insulating layer；
The first bit line and the second bit line of the mutually insulated of nonvolatile memory are provided on the insulating layer；
First drain region is electrically connected to first bit line by the first bit line contact hole, and second drain region passes through second
Wire contact hole is electrically connected to second bit line.
9. storage unit according to claim 2, which is characterized in that the control gate and first floating boom and second are floating
Interlayer dielectric layer is provided between grid.
10. storage unit according to claim 9, which is characterized in that the interlayer dielectric layer includes stacked gradually
One oxide layer, nitration case and the second oxide layer.
11. storage unit according to claim 3, which is characterized in that first control gate both sides are formed with side wall.
12. a kind of nonvolatile memory, which is characterized in that including：
It is multiple be arranged in array such as claim 1-11 any one of them storage units；
It is a plurality of to extend the wordline arranged along column direction, every wordline and the control with storage unit described in a line along line direction
Grid are electrically connected；
A plurality of to extend the bit line arranged along line direction along column direction, storage unit has two bit lines described in each column, each
The first drain region and the second drain region of the storage unit are electrically connected to different bit lines.
13. nonvolatile memory according to claim 12, which is characterized in that along the two of the column direction arbitrary neighborhood
A drain region is shared between a storage unit, and shared drain region is electrically connected to same bit line by a bit line contact hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710153121.3A CN108649032A (en) | 2017-03-15 | 2017-03-15 | A kind of storage unit and nonvolatile memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710153121.3A CN108649032A (en) | 2017-03-15 | 2017-03-15 | A kind of storage unit and nonvolatile memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108649032A true CN108649032A (en) | 2018-10-12 |
Family
ID=63744006
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710153121.3A Pending CN108649032A (en) | 2017-03-15 | 2017-03-15 | A kind of storage unit and nonvolatile memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108649032A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5386132A (en) * | 1992-11-02 | 1995-01-31 | Wong; Chun C. D. | Multimedia storage system with highly compact memory device |
| US20050139910A1 (en) * | 2003-12-30 | 2005-06-30 | Koh Kwan J. | Semiconductor devices and methods for fabricating the same |
| CN104637945A (en) * | 2013-11-08 | 2015-05-20 | 苏州东微半导体有限公司 | Semi-floating gate storage device, manufacturing method thereof and semi-floating gate storage device array |
-
2017
- 2017-03-15 CN CN201710153121.3A patent/CN108649032A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5386132A (en) * | 1992-11-02 | 1995-01-31 | Wong; Chun C. D. | Multimedia storage system with highly compact memory device |
| US20050139910A1 (en) * | 2003-12-30 | 2005-06-30 | Koh Kwan J. | Semiconductor devices and methods for fabricating the same |
| CN104637945A (en) * | 2013-11-08 | 2015-05-20 | 苏州东微半导体有限公司 | Semi-floating gate storage device, manufacturing method thereof and semi-floating gate storage device array |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11515328B2 (en) | Staggered word line architecture for reduced disturb in 3-dimensional NOR memory arrays | |
| KR100702014B1 (en) | One-transistor floating-body DRAM devices having vertical channel transistor structure and methods of fabricating the same | |
| KR101034914B1 (en) | Flash memory with recessed floating gate | |
| US8530956B2 (en) | Non-volatile memory device and method for fabricating the same | |
| US10553598B2 (en) | Three-dimensional semiconductor devices including vertical structures | |
| CN105009286B (en) | Non-volatile memory cells with enhanced channel region effective width, and method of making same | |
| JP2007300098A5 (en) | ||
| KR101996745B1 (en) | High Density Isolated Gate Memory Cell | |
| JP2007300098A (en) | Nor flash memory and manufacturing method thereof | |
| CN103035650A (en) | Semiconductor device and manufacturing method of semiconductor device | |
| KR20030060139A (en) | Split-gate type non-volatile memory and method of fabricating the same | |
| CN101490837B (en) | Nonvolatile semiconductor memory and its drive method | |
| CN106575656A (en) | Split-gate flash memory cell with improved scaling using enhanced lateral control gate to floating gate coupling | |
| KR940005898B1 (en) | Nonvolatile semiconductor device | |
| KR101073640B1 (en) | High-density vertical-type semiconductor memory cell string, cell string array and fabricating method thereof | |
| CN105742287B (en) | Memory component | |
| JP2011035169A (en) | Nonvolatile semiconductor memory device and method of manufacturing the same | |
| US7053447B2 (en) | Charge-trapping semiconductor memory device | |
| CN100505235C (en) | Metal line of semiconductor device and method of fabricating the same | |
| US7554151B2 (en) | Low voltage non-volatile memory cell with electrically transparent control gate | |
| CN108630687A (en) | A kind of storage unit and nonvolatile memory | |
| CN108649032A (en) | A kind of storage unit and nonvolatile memory | |
| KR101002246B1 (en) | Nor flash memory array with vertical channel builtin fin-split layer | |
| KR100799055B1 (en) | A floating gate in flash memory device and forming method thereof | |
| US7767566B2 (en) | Flash memory device and method of forming the device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20181012 |
|
| RJ01 | Rejection of invention patent application after publication |