CN110071116B - Three-dimensional NAND type ferroelectric memory, manufacturing method and operating method - Google Patents
Three-dimensional NAND type ferroelectric memory, manufacturing method and operating method Download PDFInfo
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- CN110071116B CN110071116B CN201910349696.1A CN201910349696A CN110071116B CN 110071116 B CN110071116 B CN 110071116B CN 201910349696 A CN201910349696 A CN 201910349696A CN 110071116 B CN110071116 B CN 110071116B
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
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- H10B51/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
Abstract
The invention provides a three-dimensional NAND type ferroelectric memory, a manufacturing method and an operation method, the three-dimensional NAND type ferroelectric memory is formed by inserting an auxiliary grid electrode material layer between a ferroelectric layer and a dielectric layer based on the existing ferroelectric memory structure, the grid electrode of a unit is laminated into a main grid electrode material layer, the ferroelectric layer, the auxiliary grid electrode material layer and the dielectric layer, and the ferroelectric layer is independently programmed and erased by matching with the auxiliary grid electrode material layer, so that the reliability of the ferroelectric memory is effectively improved, namely, a storage window is enlarged, the durability of a device is improved, and the retention characteristic of the device is improved.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a three-dimensional NAND type ferroelectric memory, a manufacturing method and an operating method.
Background
At present, as the research on ferroelectricity on doped hafnium-based materials is broken through, the use of ferroelectric transistors as nonvolatile memories attracts extensive research of researchers. Among them, the hafnium-based ferroelectric memory has advantages of easy miniaturization and compatibility with a conventional CMOS process.
However, in the conventional hafnium-based ferroelectric memory, charge trapping of the ferroelectric layer during erasing and writing can neutralize polarization inversion of the ferroelectric layer, so that the memory window is reduced; the release process of the trapped charges of the ferroelectric layer also affects the read operation after erasing, thereby limiting the read speed; moreover, the unreasonable distribution of the electric field in the ferroelectric layer and the dielectric layer reduces the electric field between the two sides of the ferroelectric layer, so that the device works in a ferroelectric unsaturated region, thereby reducing a storage window, and increases the electric leakage and further reduces the durability due to overlarge electric field between the two sides of the dielectric layer.
Disclosure of Invention
In view of the above, in order to solve the above problems, the present invention provides a three-dimensional NAND-type ferroelectric memory, a manufacturing method and an operating method thereof, and the technical solution is as follows:
a three-dimensional NAND-type ferroelectric memory, comprising:
a substrate;
the laminated structure comprises a main grid electrode material layer and an isolation layer, wherein the main grid electrode material layer and the isolation layer are arranged in an overlapped mode in the direction perpendicular to the substrate, the bottom layer adjacent to the substrate is the main grid electrode material layer, and the top layer away from the substrate is the isolation layer;
a plurality of vias through the laminated structure;
and the main grid buffer layer, the ferroelectric layer, the auxiliary grid material layer, the dielectric layer and the channel material layer are sequentially arranged on the side wall of each through hole so as to form a plurality of operation units.
Preferably, the through hole is cylindrical in shape;
wherein the diameter of the through hole is 90nm-110nm, inclusive.
Preferably, the material of the main gate material layer and the auxiliary gate material layer is polysilicon or polysilicon silicide or W metal or TaN metal or metal nitride.
Preferably, the material of the dielectric layer is an oxide material or an oxynitride material of silicon.
Preferably, the main gate buffer layer is made of TiN or TaN or RuO2。
Preferably, the material of the ferroelectric layer is HZO.
An operation method applied to the three-dimensional NAND type ferroelectric memory of any one of the above, the operation method comprising:
determining a non-selection unit and a selection unit in each operation unit;
applying a first voltage to a main gate material layer of the non-selection unit, wherein the auxiliary gate material layer is floating, applying a read voltage to the main gate material layer of the selection unit, applying a bit line voltage to a bit line end of the operation unit, and grounding a source end of the operation unit;
judging the magnitude of current passing through the operation unit;
if the current is larger than a preset current value, the operation unit is in an erasing state; if the current is smaller than the preset current value, the operation unit is in a programming state;
when the operation units perform erasing operation, erasing voltage is applied to the auxiliary grid electrode material layer, the bit line ends and the source ends of the operation units are floating, and the main grid electrode material layer of each operation unit is grounded;
when the operation unit carries out programming operation, the auxiliary grid electrode material layer is grounded, programming voltage is applied to the main grid electrode material layer of the selection unit, and the bit line end and the source end of the operation unit and the main grid electrode material layer of the non-selection unit are all floating;
when the operation unit performs programming inhibition operation, the auxiliary grid electrode material layer applies programming inhibition voltage, the main grid electrode material layer of the selection unit applies programming voltage, and the bit line end and the source end of the operation unit and the main grid electrode material layer of the non-selection unit are all floating.
A method of fabricating a three-dimensional NAND-type ferroelectric memory, the method comprising:
providing a substrate;
arranging a laminated structure on the substrate, wherein the laminated structure comprises a sacrificial layer and an isolation layer, the sacrificial layer and the isolation layer are arranged in an overlapping mode in the direction perpendicular to the substrate, the bottom layer adjacent to the substrate is the sacrificial layer, and the top layer away from the substrate is the isolation layer;
etching the laminated structure to expose the substrate and form a plurality of through holes;
depositing a main grid buffer layer, a ferroelectric layer, an auxiliary grid material layer, a dielectric layer and a channel material layer on the side wall of each through hole in sequence;
horizontally etching the sacrificial layer to remove the sacrificial layer;
and filling the main gate material to form a main gate material layer.
Compared with the prior art, the invention has the following beneficial effects:
the three-dimensional NAND type ferroelectric memory is based on the existing ferroelectric memory structure, a layer of auxiliary grid electrode material layer is inserted between a ferroelectric layer and a dielectric layer to form the three-dimensional NAND type ferroelectric memory, the grid electrode of a unit is laminated into a main grid electrode material layer, the ferroelectric layer, the auxiliary grid electrode material layer and the dielectric layer, and the ferroelectric layer is independently programmed and erased by matching with the auxiliary grid electrode material layer, so that the reliability of the ferroelectric memory is effectively improved, namely, a storage window is increased, the durability of a device is improved, and the retention characteristic of the device is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a three-dimensional NAND-type ferroelectric memory according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart of a method of operation according to an embodiment of the present invention;
FIG. 3 is an equivalent diagram of an operation unit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a read operation according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an erase operation according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating a program operation according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating a program inhibit operation according to an embodiment of the present invention;
fig. 8 is a schematic flow chart illustrating a method for manufacturing a three-dimensional NAND-type ferroelectric memory according to an embodiment of the present invention;
fig. 9-13 are schematic process structures of the manufacturing method shown in fig. 8.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a three-dimensional NAND-type ferroelectric memory according to an embodiment of the present invention, where the three-dimensional NAND-type ferroelectric memory includes:
a substrate 11;
the stacked structure comprises a main gate electrode material layer 12 and an isolation layer 13, the main gate electrode material layer 12 and the isolation layer 13 are arranged in an overlapping mode in a direction perpendicular to the substrate 11, the bottom layer adjacent to the substrate 11 is the main gate electrode material layer 12, and the top layer away from the substrate 11 is the isolation layer 13;
a plurality of vias through the laminated structure;
and a main gate buffer layer 14, a ferroelectric layer 15, an auxiliary gate material layer 16, a dielectric layer 17 and a channel material layer 18 are sequentially arranged on the side wall of each through hole to form a plurality of operation units.
In this embodiment, the three-dimensional NAND-type ferroelectric memory is formed by inserting an auxiliary gate material layer between a ferroelectric layer and a dielectric layer based on the existing ferroelectric memory structure, the gate stack of the cell is composed of the main gate material layer, the ferroelectric layer, the auxiliary gate material layer and the dielectric layer, and the ferroelectric layer is independently programmed and erased in cooperation with the auxiliary gate material layer, so that the reliability of the ferroelectric memory is effectively improved, that is, the memory window is increased, the device durability is improved, and the device retention characteristic is improved.
The number of layers and the thickness of each layer of the stacked structure, that is, the number of layers and the thickness of the main gate material layer and the number of layers and the thickness of the isolation layer, are not limited in the embodiment of the present invention, and may be determined according to specific situations.
Further, the through hole is cylindrical in shape;
wherein the diameter of the through hole is 90nm-110nm, inclusive.
In this embodiment, the diameter of the via is, for example, 95nm or 100nm or 105 nm.
It should be noted that, in the embodiment of the present invention, the through hole is merely illustrated as a cylindrical through hole, and the embodiment of the present invention is not limited thereto.
Further, the material of the main gate material layer 12 and the auxiliary gate material layer 16 includes, but is not limited to, polysilicon or polysilicon silicide, or W metal or TaN metal or metal nitride.
Further, the material of the dielectric layer 17 is an oxide material or an oxynitride material of silicon.
Further, the material of the main gate buffer layer 14 is TiN or TaN or RuO2。
Further, the material of the ferroelectric layer 15 is HZO or different doped HfO2, doped with impurities such as Si, Al, Zr, Y, Sr, La, Gd, etc.
It should be noted that the thicknesses of the main gate material layer 12, the main gate buffer layer 14, the ferroelectric layer 15, the auxiliary gate material layer 16, the dielectric layer 17 and the channel material layer 18 are not limited in the embodiment of the present invention, and may be determined according to specific situations.
Based on the foregoing embodiment of the present invention, in another embodiment of the present invention, an operation method is further provided, which is applied to the three-dimensional NAND-type ferroelectric memory, and referring to fig. 2, fig. 2 is a schematic flow chart of the operation method according to the embodiment of the present invention, where the operation method includes:
s201: and determining a non-selection unit and a selection unit in each operation unit.
In this step, referring to fig. 3, fig. 3 is an equivalent schematic diagram of an operation unit provided by an embodiment of the present invention, where the operation unit includes a Sub Gate material layer Sub Gate, a Bit line terminal Bit-line, and a plurality of unit structures are exemplified by WL1-WL6, and ports thereof are a Main Gate material layer Main Gate and a source terminal S, where a unit to be operated is defined as a selected unit, and a unit not requiring operation is defined as a non-selected unit.
S202: applying a first voltage to the main gate material layer of the non-selection unit, floating the auxiliary gate material layer, applying a read voltage to the main gate material layer of the selection unit, applying a bit line voltage to the bit line terminal of the operation unit, and grounding the source terminal of the operation unit.
S203: and judging the magnitude of the current passing through the operation unit.
S204: if the current is larger than a preset current value, the operation unit is in an erasing state; and if the current is smaller than the preset current value, the operation unit is in a programming state.
In steps S202 to S204, referring to fig. 4, fig. 4 is a schematic diagram of a read operation provided by an embodiment of the present invention, for example, a source terminal of the operation unit is grounded to 0V by applying a turn-on voltage Vpass to a main gate material layer of the unselected unit, the auxiliary gate material layer floats Float, a read voltage Vread is applied to the main gate material layer of the selected unit, and a Bit line voltage Vd is applied to a Bit line terminal of the operation unit, and then a current passing through the operation unit, that is, a current passing through between the Bit line terminal Bit-line and the source terminal S is determined, and if the current is greater than a preset current value, the operation unit is in an erase state; and if the current is smaller than the preset current value, the operation unit is in a programming state.
S205: when the operation units perform erasing operation, the auxiliary grid electrode material layer applies erasing voltage, the bit line ends and the source ends of the operation units are floating, and the main grid electrode material layer of each operation unit is grounded.
Referring to fig. 5, fig. 5 is a schematic diagram of an erase operation provided by an embodiment of the present invention, for example, by applying an erase voltage Vers to the auxiliary gate material layer, the main gate material layer of each of the operation units is grounded at 0V, and bit line ends and source end floating floats of the operation units are provided.
S206: when the operation unit carries out programming operation, the auxiliary grid electrode material layer is grounded, programming voltage is applied to the main grid electrode material layer of the selection unit, and the bit line end and the source end of the operation unit and the main grid electrode material layer of the non-selection unit are all floating.
In this step, referring to fig. 6, fig. 6 is a schematic diagram of a programming operation provided by the embodiment of the present invention, for example, by grounding the auxiliary gate material layer to 0V, the programming voltage Vpgm is applied to the main gate material layer of the selected cell, and both the bit line terminal and the source terminal of the operating cell and the main gate material layer of the unselected cell Float.
S207: when the operation unit performs programming inhibition operation, the auxiliary grid electrode material layer applies programming inhibition voltage, the main grid electrode material layer of the selection unit applies programming voltage, and the bit line end and the source end of the operation unit and the main grid electrode material layer of the non-selection unit are all floating.
In this step, referring to fig. 7, fig. 7 is a schematic diagram illustrating a program inhibit operation according to an embodiment of the present invention, for example, by applying a program inhibit voltage Vinhibit to the auxiliary gate material layer, applying a program voltage Vpgm to the main gate material layer of the selected cell, and floating Float both at the bit line terminal and the source terminal of the operating cell and the main gate material layer of the unselected cell.
Based on the above embodiments of the present invention, in another embodiment of the present invention, a method for manufacturing a three-dimensional NAND-type ferroelectric memory is further provided, and referring to fig. 8, fig. 8 is a schematic flow chart of the method for manufacturing the three-dimensional NAND-type ferroelectric memory according to the embodiment of the present invention, where the method includes:
s801: as shown in fig. 9, a substrate 11 is provided.
In this step, the material and thickness of the substrate 11 are not limited in the embodiment of the present invention, and may be determined according to the specific situation.
S802: as shown in fig. 10, a stacked structure is disposed on the substrate 11, the stacked structure includes a sacrificial layer 19 and an isolation layer 13, in a direction perpendicular to the substrate 11, the sacrificial layer 19 and the isolation layer 13 are arranged in an overlapping manner, a bottom layer adjacent to the substrate 11 is the sacrificial layer 19, and a top layer away from the substrate 11 is the isolation layer 13.
In this step, the number of layers and the thickness of each layer of the stacked structure, that is, the number of layers and the thickness of the sacrificial layer 19 and the number of layers and the thickness of the spacer layer 13 are not limited in the embodiment of the present invention, and may be determined as the case may be.
S803: as shown in fig. 11, the stacked structure is etched to expose the substrate 11, and a plurality of through holes 111 are formed.
In this step, the through-hole 111 is cylindrical in shape; wherein the diameter of the via 111 is 90nm-110nm, inclusive. For example, the diameter of the via 111 is 95nm or 100nm or 105 nm.
It should be noted that, in the embodiment of the present invention, the through hole is merely illustrated as a cylindrical through hole, and the embodiment of the present invention is not limited thereto.
S804: as shown in fig. 12, a main gate buffer layer 14, a ferroelectric layer 15, an auxiliary gate material layer 16, a dielectric layer 17 and a channel material layer 18 are sequentially deposited on the sidewall of each of the vias 111.
In this step, the thicknesses of the main gate material layer, the main gate buffer layer 14, the ferroelectric layer 15, the auxiliary gate material layer 16, the dielectric layer 17 and the channel material layer 18 are not limited in the embodiment of the present invention, and may be determined according to specific situations.
S805: as shown in fig. 13, the sacrificial layer 19 is etched horizontally to remove the sacrificial layer 19.
S806: as shown in fig. 1, the main gate material is filled to form a main gate material layer 12.
In this embodiment, the three-dimensional NAND-type ferroelectric memory manufactured by the above manufacturing method is configured such that an auxiliary gate material layer is inserted between a ferroelectric layer and a dielectric layer based on an existing ferroelectric memory structure, and the gate stack of the cell is composed of the main gate material layer, the ferroelectric layer, the auxiliary gate material layer, and the dielectric layer, and the ferroelectric layer is independently programmed and erased in cooperation with the auxiliary gate material layer, so that the reliability of the ferroelectric memory is effectively improved, that is, the memory window is increased, the device durability is improved, and the device retention characteristic is improved. In addition, the manufacturing method is simple and the cost is low.
The three-dimensional NAND-type ferroelectric memory, the manufacturing method and the operating method provided by the present invention are described in detail above, and the principle and the implementation of the present invention are explained in the present document by applying specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include or include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (6)
1. An operating method applied to a three-dimensional NAND type ferroelectric memory, the three-dimensional NAND type ferroelectric memory comprising:
a substrate;
the laminated structure comprises a main grid electrode material layer and an isolation layer, wherein the main grid electrode material layer and the isolation layer are arranged in an overlapped mode in the direction perpendicular to the substrate, the bottom layer adjacent to the substrate is the main grid electrode material layer, and the top layer away from the substrate is the isolation layer;
a plurality of vias through the laminated structure;
the main grid electrode buffer layer, the ferroelectric layer, the auxiliary grid electrode material layer, the dielectric layer and the channel material layer are sequentially arranged on the side wall of each through hole so as to form a plurality of operation units;
the operation method comprises the following steps:
determining a non-selection unit and a selection unit in each operation unit;
applying a first voltage to a main gate material layer of the non-selection unit, wherein the auxiliary gate material layer is floating, applying a read voltage to the main gate material layer of the selection unit, applying a bit line voltage to a bit line end of the operation unit, and grounding a source end of the operation unit;
judging the magnitude of current passing through the operation unit;
if the current is larger than a preset current value, the operation unit is in an erasing state; if the current is smaller than the preset current value, the operation unit is in a programming state;
when the operation units perform erasing operation, the auxiliary grid electrode material layer applies erasing voltage, the bit line end and the source end of the operation units are floating, and the main grid electrode material layer of each operation unit is grounded;
when the operation unit carries out programming operation, the auxiliary grid electrode material layer is grounded, programming voltage is applied to the main grid electrode material layer of the selection unit, and the bit line end and the source end of the operation unit and the main grid electrode material layer of the non-selection unit are all floating;
when the operation unit performs programming inhibition operation, the auxiliary grid electrode material layer applies programming inhibition voltage, the main grid electrode material layer of the selection unit applies programming voltage, and the bit line end and the source end of the operation unit and the main grid electrode material layer of the non-selection unit are all floating.
2. The operating method according to claim 1, characterized in that said through hole is cylindrical in shape;
wherein the diameter of the through hole is 90nm-110nm, inclusive.
3. The method of claim 1, wherein the material of the main gate material layer and the auxiliary gate material layer is polysilicon or W metal or metal nitride.
4. The method of claim 1, wherein the dielectric layer is made of an oxide material or an oxynitride material of silicon.
5. The operating method according to claim 1, wherein the material of the main gate buffer layer is TiN or TaN or RuO2。
6. The operating method according to claim 1, characterized in that the material of the ferroelectric layer is HZO.
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| DE102021106058A1 (en) * | 2020-05-29 | 2021-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | STORAGE CELL AND METHOD OF OPERATING THE SAME |
| CN111799263A (en) * | 2020-06-30 | 2020-10-20 | 湘潭大学 | Three-dimensional NAND ferroelectric memory and preparation method thereof |
| CN111799262A (en) * | 2020-06-30 | 2020-10-20 | 湘潭大学 | U-shaped ferroelectric field effect transistor memory cell string, memory and preparation method |
| CN112164699B (en) * | 2020-09-25 | 2022-02-08 | 湘潭大学 | NAND ferroelectric memory unit with three-dimensional structure and preparation method thereof |
| CN112437959B (en) * | 2020-10-23 | 2022-08-19 | 长江先进存储产业创新中心有限责任公司 | Architecture, structure, method and memory array of 3D fefets for 3D ferroelectric non-volatile data storage |
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| EP3038141B1 (en) * | 2014-12-23 | 2019-08-28 | IMEC vzw | Method of reading a memory cell of a vertical ferroelectric memory device |
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| CN1312588A (en) * | 2000-02-15 | 2001-09-12 | 松下电子工业株式会社 | Semiconductor storage device, its driving method and producing method |
| CN108428701A (en) * | 2018-03-05 | 2018-08-21 | 湘潭大学 | A kind of three dimensional NAND ferroelectric memory and preparation method thereof |
| CN109461736A (en) * | 2018-10-26 | 2019-03-12 | 长江存储科技有限责任公司 | Floating gate memory device and its control method, 3D memory device and 2D memory device |
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