CN108428701A - A kind of three dimensional NAND ferroelectric memory and preparation method thereof - Google Patents
A kind of three dimensional NAND ferroelectric memory and preparation method thereof Download PDFInfo
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- 230000015654 memory Effects 0.000 title claims abstract description 29
- 238000002360 preparation method Methods 0.000 title claims abstract description 24
- 239000010410 layer Substances 0.000 claims abstract description 254
- 239000004065 semiconductor Substances 0.000 claims abstract description 81
- 239000000758 substrate Substances 0.000 claims abstract description 73
- 239000010409 thin film Substances 0.000 claims abstract description 48
- 239000011241 protective layer Substances 0.000 claims abstract description 27
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 24
- 239000001301 oxygen Substances 0.000 claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 66
- 238000000034 method Methods 0.000 claims description 62
- 238000005530 etching Methods 0.000 claims description 54
- 238000000151 deposition Methods 0.000 claims description 47
- 239000000463 material Substances 0.000 claims description 45
- 229920005591 polysilicon Polymers 0.000 claims description 40
- 230000008021 deposition Effects 0.000 claims description 28
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 23
- 239000000203 mixture Substances 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 8
- 229910052593 corundum Inorganic materials 0.000 claims description 8
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 8
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 239000002210 silicon-based material Substances 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 239000007792 gaseous phase Substances 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 229910002902 BiFeO3 Inorganic materials 0.000 claims description 2
- 229910052779 Neodymium Inorganic materials 0.000 claims description 2
- 229910003781 PbTiO3 Inorganic materials 0.000 claims description 2
- 229910002370 SrTiO3 Inorganic materials 0.000 claims description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- 229910009567 YMnO3 Inorganic materials 0.000 claims description 2
- 229910002113 barium titanate Inorganic materials 0.000 claims description 2
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 claims description 2
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 claims description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 claims description 2
- 229910052726 zirconium Inorganic materials 0.000 claims description 2
- 229910052797 bismuth Inorganic materials 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 66
- 230000008569 process Effects 0.000 description 33
- 238000001259 photo etching Methods 0.000 description 20
- 238000003860 storage Methods 0.000 description 18
- 238000005229 chemical vapour deposition Methods 0.000 description 17
- 238000005516 engineering process Methods 0.000 description 17
- 238000005137 deposition process Methods 0.000 description 12
- 238000012545 processing Methods 0.000 description 9
- 238000001755 magnetron sputter deposition Methods 0.000 description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000004590 computer program Methods 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 5
- FIWXUAGPOBLSIJ-UHFFFAOYSA-N [Hf].[Zr].[O] Chemical group [Hf].[Zr].[O] FIWXUAGPOBLSIJ-UHFFFAOYSA-N 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 4
- 238000002425 crystallisation Methods 0.000 description 4
- 230000008025 crystallization Effects 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 230000005621 ferroelectricity Effects 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- CMIAIUZBKPLIOP-YZLZLFLDSA-N methyl (1r,4ar,4br,10ar)-7-(2-hydroperoxypropan-2-yl)-4a-methyl-2,3,4,4b,5,6,10,10a-octahydro-1h-phenanthrene-1-carboxylate Chemical group C1=C(C(C)(C)OO)CC[C@@H]2[C@]3(C)CCC[C@@H](C(=O)OC)[C@H]3CC=C21 CMIAIUZBKPLIOP-YZLZLFLDSA-N 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- 230000000007 visual effect Effects 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 210000004027 cell Anatomy 0.000 description 2
- 235000013399 edible fruits Nutrition 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- -1 HfO2 Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 210000003205 muscle Anatomy 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 210000000352 storage cell Anatomy 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40111—Multistep manufacturing processes for data storage electrodes the electrodes comprising a layer which is used for its ferroelectric properties
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
Abstract
The invention discloses a kind of three dimensional NAND ferroelectric memorys and preparation method thereof, it is related to technical field of semiconductors, the ferroelectric memory includes horizontal substrate, public source in the horizontal substrate is set, two array strings are at least arranged in the horizontal substrate upper surface, are separated by first medium layer between two array strings；The array strings include the column type semiconductor regions perpendicular to the horizontal substrate; oxygen protective layer on the column type semiconductor regions and trace layer; the ferroelectric thin film layer of the column type semiconductor regions, buffer layer and the control grid electrode mutually stacked with second dielectric layer are wrapped up according to this；Wherein, the trace layer penetrates the oxygen protective layer and is contacted with the upper surface of the column type semiconductor regions.
Description
Technical field
The present invention relates to technical field of semiconductors, a kind of ferroelectric memory and preparation method thereof is more particularly related to.
Background technology
With the update iteration of semiconductor fabrication process technology, the size of semiconductor memory cell constantly reduces, integrated level
It is continuously improved.And with the continuous diminution of memory cell dimensions, the requirement of technique also accordingly improves, while but also cost not
It is disconnected to improve.Production cost to solve difficulty and the lower unit storage unit of pursuit that planar flash memory encounters proposes three-dimensional sudden strain of a muscle
Memory is deposited, such as：Three dimensional NAND Ferroelectric reservoir；
The storage unit of three dimensional NAND Ferroelectric reservoir is that (English is ferroelectricity field effect electric crystal： ferroelectric
Field-effect transistor, Chinese are：FeFET), operation principle is the polarization based on ferroelectric thin film.With N-shaped
For FeFET, when applying a positive write-in voltage on the grid in FeFET, ferroelectric thin film polarizes, and channel surface is formed
Inversion layer forms the channel of electric current between source, drain electrode in this way, can read a larger electric current in drain electrode at this time, right
Answer logical value storage " 1 "；When applying a negative voltage on grid, channel surface then forms accumulation layer, and source drains it
Between current channel be truncated, logical value storage " 0 " is corresponded to regard to very little in the electric current read of drain electrode at this time.
FeFET is considered as the novel memory devices of next-generation emphasis research and development, because it has, storage organization is simple, storage is close
The advantages that spending high and low power consumption, high access speed, radioresistance and non-Destructive readout, compared to conventional floating gate type and electric charge capture
The memory of type structure is advantageously.For existing floating gate type and charge trap-type nand flash memory, deposited to further decrease
The operating voltage of reservoir improves the speed of service, stability and reliability of device, novel based on new material and new operation principle
Nonvolatile semiconductor memory member has received widespread attention.
In conclusion that there are operating voltages is higher for existing three-dimensional flash memory memory, and erasable ability is lower repeatedly asks
Topic.
Invention content
A kind of ferroelectric memory of offer of the embodiment of the present invention and preparation method thereof, to solve existing three-dimensional flash memory storage
That there are operating voltages is higher for device, and the relatively low problem of erasable ability repeatedly.
The embodiment of the present invention provides a kind of preparation method of ferroelectric memory, including：
Public source is formed by etching and ion implanting on horizontal substrate layer；
Second dielectric layer and sacrificial layer are stacked according to this on the horizontal substrate layer by chemical gaseous phase deposition method, are formed
Original array string；
By etching at least two first through hole, and the following table of two first through hole are formed in the original array string
Face is in contact with the horizontal substrate layer；
It deposits ferroelectric thin film layer and buffer layer according to this in two first through hole, etches two first through hole bottoms
The ferroelectric thin film layer on face and the buffer layer；
In two first through hole and original array string list face deposit polycrystalline silicon forms two column type semiconductors
Region, the etching region adjacent with two column type semiconductor regions form the second through-hole, and the following table of second through-hole
Face is in contact with the public source；
The sacrificial layer is etched, and in the position depositional control grid of the sacrificial layer, etching is located at second through-hole
The control grid on side wall deposits first medium layer to second through-hole and with described second by adjacent surface；
Etch the first medium layer and form lead hole on two column type semiconductor regions, and by deposition and
Etching forms lead block in two lead hole.
Preferably, the etching region adjacent with two column type semiconductor regions is formed before the second through-hole, tool
Body includes：
With original array string list face deposit polycrystalline silicon in two first through hole, the original array string is etched
Surface deposit polycrystalline silicon forms the column type by the polysilicon of the deposition on surface and partly leads in the first through hole with described first
Body region；
In two column type semiconductor regions and the surface deposited oxide adjacent with two column type semiconductor regions
Protective layer.
Preferably, the public source is located in the horizontal substrate, and the two side of the first through hole respectively with institute
The upper surface for stating public source does not contact.
Preferably, the column type semiconductor regions are made of polycrystalline silicon material, and the cylinder of the column type semiconductor regions is straight
Diameter is 60nm~200nm.
Preferably, the material of the ferroelectric thin film is that Zr adulterates HfO2, Si doping HfO2, Al doping HfO2, Y doping HfO2
And at least one of hafnium oxide base ferroelectric material or SrBi2Ta2O9, PbTiO3, BaTiO3, Pb (Zr, Ti) O3, (Bi,
Nd)4Ti3O12, BiFeO3, YMnO3At least one of；
The thickness of the ferroelectric thin film is between 2nm~100nm；
The material of the buffer layer is Y2O3, CeO2, Al2O3, HfO2, SrTiO3, (HfO2)0.75(Al2O3) 0.25In one
Kind or combination；The thickness of the buffer layer is between 3~25nm.
Preferably, the first medium layer and the second dielectric layer are made of silica material, the sacrificial dielectric layer
It is made of silicon nitride material；
The first medium layer thickness between 50~200nm, the second medium layer thickness between for 50~
Between 150nm.
Preferably, the control grid electrode is by titanium nitride, tungsten, aluminium, one or more of polysilicon combined material group
At；The control gate is between 30~100nm.
The embodiment of the present invention additionally provides a kind of ferroelectric memory, including horizontal substrate, is arranged in the horizontal substrate
Public source, the horizontal substrate upper surface is at least arranged two array strings, passes through first between two array strings and be situated between
Matter layer separates；
The array strings include the column type semiconductor regions perpendicular to the horizontal substrate, are located at the column type semiconductor region
Oxygen protective layer on domain and trace layer, wrap up the ferroelectric thin film layer of the column type semiconductor regions according to this, buffer layer and with second
The control grid electrode that dielectric layer mutually stacks；
Wherein, the trace layer penetrates the oxygen protective layer and is contacted with the upper surface of the column type semiconductor regions.
An embodiment of the present invention provides a kind of three dimensional NAND ferroelectric memorys and preparation method thereof, which mainly wraps
It includes：Public source is formed by etching and ion implanting on horizontal substrate layer；By chemical gaseous phase deposition method in the water
Second dielectric layer and sacrificial layer are stacked on fFlat substrate layer according to this, forms original array string；By etching in the original array string
At least two first through hole are formed, and the lower surface of two first through hole is in contact with the horizontal substrate layer；At two
Ferroelectric thin film layer and buffer layer are deposited in the first through hole according to this, etches the ferroelectricity on two first through hole bottom surfaces
Film layer and the buffer layer；In two first through hole and original array string list face deposit polycrystalline silicon forms two
Column type semiconductor regions, the etching region adjacent with two column type semiconductor regions form the second through-hole, and described second
The lower surface of through-hole is in contact with the public source；The sacrificial layer is etched, and in the position depositional control of the sacrificial layer
Grid, etching are located at the control grid on second through-hole side wall, pass through to second through-hole and with described second
Adjacent surface deposits first medium layer；It etches the first medium layer and forms lead on two column type semiconductor regions
Through-hole, and by depositing and etching lead block is formed in two lead hole.The ferroelectricity storage prepared by this method
Device uses ferroelectric thin film storage medium and substitutes floating gate charge storage medium formation metal-ferroelectricity-insulation-semiconductor (MFIS)
Structure, it is contemplated that lower operating voltage can be obtained, obtain higher repeatedly erasable ability and good capability of resistance to radiation.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
Obtain other attached drawings according to these attached drawings.
Fig. 1 is a kind of three dimensional NAND ferroelectric storage unit section structure chart provided in an embodiment of the present invention；
Fig. 2 a~Fig. 2 p are that a kind of ferroelectric storage cell provided in an embodiment of the present invention makes schematic diagram.
Wherein, 1 is horizontal substrate；2 be second dielectric layer；3 gate electrodes in order to control；4 be ferroelectric thin film；5 be buffer layer；6
For column type semiconductor regions；7 be oxide protective layer；8 be public source level region；9 be first medium layer；10 be trace layer；11 are
Sacrificial dielectric layer.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a kind of ferroelectric memorys, specifically as shown in Figure 1, the ferroelectric memory includes mainly：
Horizontal substrate 1, public source layer 8 and array strings.
Specifically, public source layer 8 is arranged in horizontal substrate 1, and array strings are arranged in 1 upper surface of horizontal substrate, each
There are an intersection in the two edges of array strings with the both sides of public source layer 8, and between two array strings by first medium layer 9 every
It opens.
It should be noted that in practical applications, although public source layer 8 is arranged in horizontal substrate 1, common source
The upper surface level height having the same of the upper surface and horizontal substrate 1 of pole layer 8.
As shown in Figure 1, array strings include column type semiconductor regions 6, oxygen protective layer 7, trace layer 10,4 layers of ferroelectric thin film delays
Rush layer 5, second dielectric layer 2 and control grid electrode 3；Specifically, column type semiconductor regions 6 are vertically set on 1 upper table of horizontal substrate
Face, 6 upper surface of column type semiconductor regions are arranged aerobic protective layer 7 and trace layer 10, and the trace layer 10 penetrate oxygen protective layer 7 with
The upper surface of column type semiconductor regions 6 contacts.Furthermore the outside of column type semiconductor regions 6 is enclosed with 4 layers of ferroelectric thin film according to this,
Buffer layer 5 and the control grid electrode 3 stacked with 2 phase of second dielectric layer.
Below in conjunction with Fig. 1, Fig. 2 a to Fig. 2 p, provided by embodiment 1 to embodiment 4 to introduce the embodiment of the present invention
A kind of array strings be metal-ferroelectricity-insulation-semiconductor (MFIS) structure ferroelectric memory preparation method.
Embodiment 1
A kind of preparation method of ferroelectric memory provided in an embodiment of the present invention, mainly includes the following steps that：
Step 1：Cleaning provides horizontal substrate 1, using photoetching process, forms public source layer 8, it should be noted that light
Carving technology is using 365nm I Wiring technologies.Further, it should be noted that horizontal substrate 1 by high doped p-type silicon
(Si) material forms.
Step 2：Horizontal substrate 1 is etched, groove is formed in 1 upper surface of horizontal substrate；Polysilicon is formed in the trench, it should
The thickness value of polysilicon is equal to the depth value of groove；Further, N is carried out to polysilicon using ion implantation+Doping, to
Form pn-junction.It should be noted that forming N+It is 30KeV that type source area, which needs Implantation Energy, dosage is 1 × 1016cm-2P (31)+
Ion.Epitaxial crystallization is carried out to the polysilicon of doping using rapid thermal anneal methods, the CSL is drawn based on pn-junction, such as Fig. 2 a institutes
Show.
Step 3：Using chemical vapour deposition technique, multiple stackings are sequentially formed in the horizontal substrate 1 handled through step 2
Second dielectric layer 2 and sacrificial dielectric layer 11, form original array strings, Fig. 2 b are the result signal after depositing stacked structure
Figure.
It needs, second dielectric layer 2 is by silica (SiO2) material composition, the thickness of second dielectric layer 2 is
100nm；And sacrificial dielectric layer 11 is made of silicon nitride material, the thickness of sacrificial dielectric layer 11 is 50nm.
Step 4：Form window using photoetching process, then by dry etch process, etched on original array string to
Few two first through hole, and the lower surface of two first through hole is in contact with horizontal substrate 1 pass through two of etching formation the
One through-hole exposes the upper surface of horizontal substrate 1.Fig. 2 c are the result schematic diagram etched after two first through hole.
It should be noted that as shown in Figure 2 c, although public source layer 8 is located in horizontal substrate 1, due to public source
Layer 8 and 1 upper surface having the same of horizontal substrate, and the two side of first through hole respectively with the upper surface of public source layer 8 not
Contact, i.e., first through hole does not expose the upper surface of public source layer 8.
Step 5：It it is 280 DEG C in temperature, in the environment of pressure is 15hPa, by walking using atom layer deposition process
Deposition of hafnium zirconium oxygen (HZO) ferroelectric thin film 4 in two first through hole that rapid four etching processing obtains, Fig. 2 d are deposition of hafnium zirconium oxygen
(HZO) result schematic diagram after ferroelectric thin film.
Step 6：Using chemical vapor deposition method, setting temperature is 280 DEG C, in the ditch handled by step 5
Deposit hafnium oxides (HfO in slot2) high-k buffer layer 5, Fig. 2 e are deposit hafnium oxides (HfO2) high-k buffer layer 5
Result schematic diagram afterwards.
It should be noted that ferroelectric thin film 4 is made of hafnium zirconium oxygen (HZO) material, the thickness of the ferroelectric thin film 4 is 18nm；
High-k buffer layer 5 is by hafnium oxide (HfO2) material composition, the thickness of high-k buffer layer 5 is 7nm.
Step 7：Using dry etch process, hafnium zirconium oxygen (HZO) ferroelectric thin film 4, the oxidation of first through hole bottom are etched away
Hafnium (HfO2) high-k buffer layer 5, Fig. 2 f are the result schematic diagram after etching.
Step 8：It is in two first through hole and adjacent with two first through hole using chemical vapor deposition method
Original array string list face deposit polycrystalline silicon, Fig. 2 g are the result schematic diagram of deposit polycrystalline silicon.
Step 9：Using being lithographically formed window, then using dry etch process etching to be deposited on original array string list face heavy
Long-pending polysilicon, and the polysilicon of in first through hole and first through hole surface deposition forms column type semiconductor regions 6, i.e., in water
1 upper surface of fFlat substrate forms two column type semiconductor regions 6, and Fig. 2 h are the result schematic diagram after etches polycrystalline silicon.
It should be noted that column type semiconductor regions 6 are made of polycrystalline silicon material, the thickness of column type semiconductor regions 6 is
60nm。
Step 10：After falling the etching polysilicon being deposited on original array string list face, chemical vapor deposition work is utilized
Skill, in two column type semiconductor regions 6 and the surface adjacent with two column type semiconductor regions 6 deposition oxygen protective layer 7.Fig. 2 i are
Deposit the result schematic diagram of oxygen protective layer.
It should be noted that oxygen protective layer 7 is by silica (SiO2) material composition, the thickness of oxygen protective layer 7 is 100nm.
Step 11：Using window is lithographically formed, dry etch process, etching and two column type semiconductor regions are recycled
6 adjacent regions form the second through-hole, and the lower surface of the second through-hole is in contact with the upper surface of public source layer 8, that is, passes through
Second through-hole can expose the upper surface of public source layer 8.Fig. 2 j are the result schematic diagram etched after horizontal channel.
Step 12：Multilayer sacrificial dielectric layer 11 is removed using wet etching, Fig. 2 k are etching multilayer sacrificial dielectric layer
Result schematic diagram after 11；The position of exposure uses atom layer deposition process, low pressure chemical after etches sacrificial dielectric layer 11
Be vapor-deposited (LPCVD) depositing TiN, wherein magnetron sputtering is that setting temperature is 300 DEG C, and Fig. 2 l are that the result after depositing TiN is shown
It is intended to.
Step 13：TiN on second through-hole side wall is got rid of using dry etching, Fig. 2 m are the second through-hole side wall of etching
Result schematic diagram afterwards；Recycle chemical vapor deposition method, deposited in processed second through-hole first medium layer 9 with every
From two array strings, Fig. 2 n are the result schematic diagram deposited after first medium layer.
It should be noted that first medium layer 9 is by silica (SiO2) material composition.
Step 14：Using photoetching two lead hole, and the bottom of two lead hole are etched in first medium layer 9
It is contacted with the upper surface of column type semiconductor regions 6, Fig. 2 o are the result schematic diagram after photoetching lead hole.
Step 15：By magnetron sputtering or chemical vapor deposition method, two lead hole and with two leads
Trace layer 10 is formed on the adjacent first medium layer 9 of through-hole, Fig. 2 p are the result schematic diagram after trace layer is formed.
It should be noted that trace layer 10 is made of aluminium (Al) material, the thickness of trace layer 10 is 300nm.
Step 10 six：Using photoetching process, the part trace layer 10 of first medium upper surface is etched away, retains position simultaneously
Trace layer 10 in two lead hole and first medium protects the lead visuals of reservation with photoresist, then
By carving lead block, to complete the preparation of three dimensional NAND Ferroelectric reservoir, Fig. 1 is that the preparation of ferroelectric storage device finishes
Result schematic diagram.
It should be noted that atomic layer deposition, chemistry can be used in ferroelectric thin film 4, high-k buffer layer 5, polysilicon
Vapor deposition etc. process deposits.In the embodiment of the present invention, to ferroelectric thin film 4, dielectric constant buffer layer 5 and polysilicon deposition
Concrete technology does not do specific restriction.
Embodiment 2
A kind of preparation method of ferroelectric memory provided in an embodiment of the present invention, mainly includes the following steps that：
Step 1：Cleaning provides horizontal substrate 1, using photoetching process, forms public source layer 8, it should be noted that light
Carving technology is using 365nm I Wiring technologies.Further, it should be noted that horizontal substrate 1 by high doped p-type silicon
(Si) material forms.
Step 2：Horizontal substrate 1 is etched, groove is formed in 1 upper surface of horizontal substrate；Polysilicon is formed in the trench, it should
The thickness value of polysilicon is equal to the depth value of groove；Further, N is carried out to polysilicon using ion implantation+Doping, to
Form pn-junction.It should be noted that forming N+It is 30KeV that type source area, which needs Implantation Energy, dosage is 1 × 1016cm-2P (31)+
Ion.Epitaxial crystallization is carried out to the polysilicon of doping using rapid thermal anneal methods, the CSL is drawn based on pn-junction, such as Fig. 2 a institutes
Show.
Step 3：Using physical vaporous deposition, multiple stackings are sequentially formed in the horizontal substrate 1 handled through step 2
Second dielectric layer 2 and sacrificial dielectric layer 11, form original array strings, Fig. 2 b are the result signal after depositing stacked structure
Figure.
It needs, second dielectric layer 2 is by silica (SiO2) material composition, the thickness of second dielectric layer 2 is
100nm；And sacrificial dielectric layer 11 is made of silicon nitride material, the thickness of sacrificial dielectric layer 11 is 100nm.
Step 4：Form window using photoetching process, then by dry etch process, etched on original array string to
Few two first through hole, and the lower surface of two first through hole is in contact with horizontal substrate 1 pass through two of etching formation the
One through-hole exposes the upper surface of horizontal substrate 1.Fig. 2 c are the result schematic diagram etched after two first through hole.
It should be noted that as shown in Figure 2 c, although public source layer 8 is located in horizontal substrate 1, due to public source
Layer 8 and 1 upper surface having the same of horizontal substrate, and the two side of first through hole respectively with the upper surface of public source layer 8 not
Contact, i.e., first through hole does not expose the upper surface of public source layer 8.
Step 5：It it is 280 DEG C in temperature, in the environment of pressure is 15hPa, by walking using atom layer deposition process
Deposition deposition Si in two first through hole that rapid four etching processing obtains:HfO2Ferroelectric thin film 4, Fig. 2 d are deposition Si:HfO2Ferroelectricity
Result schematic diagram after film.
Step 6：Using atom layer deposition process, setting temperature is 280 DEG C, in the groove handled by step 5
Interior deposition (HfO2)0.75(Al2O3)0.25High-k buffer layer 5, Fig. 2 e are deposition (HfO2) 0.75(Al2O3)0.25High dielectric
Result schematic diagram after constant buffer layers 5.
It should be noted that ferroelectric thin film 4 is by Si:HfO2Material forms, and the thickness of ferroelectric thin film 4 is 14nm；High dielectric
Constant buffer layers 5 are by (HfO2)0.75(Al2O3)0.25The thickness of material composition, high-k buffer layer 5 is 10nm.
Step 7：Using dry etch process, the Si of first through hole bottom is etched away:HfO2Ferroelectric thin film 4,
(HfO2)0.75(Al2O3)0.25High-k buffer layer 5, Fig. 2 f are the result schematic diagram after etching.
Step 8：It is in two first through hole and adjacent with two first through hole using chemical vapor deposition method
Original array string list face deposit polycrystalline silicon, Fig. 2 g are the result schematic diagram of deposit polycrystalline silicon.
Step 9：Using being lithographically formed window, then using dry etch process etching to be deposited on original array string list face heavy
Long-pending polysilicon, and the polysilicon of in first through hole and first through hole surface deposition forms column type semiconductor regions 6, i.e., in water
1 upper surface of fFlat substrate forms two column type semiconductor regions 6, and Fig. 2 h are the result schematic diagram after etches polycrystalline silicon.
It should be noted that column type semiconductor regions 6 are made of polycrystalline silicon material, the thickness of column type semiconductor regions 6 is
100nm。
Step 10：After falling the etching polysilicon being deposited on original array string list face, chemical vapor deposition work is utilized
Skill, in two column type semiconductor regions 6 and the surface adjacent with two column type semiconductor regions 6 deposition oxygen protective layer 7.Fig. 2 i are
Deposit the result schematic diagram of oxygen protective layer.
It should be noted that oxygen protective layer 7 is by silica (SiO2) material composition, the thickness of oxygen protective layer 7 is 100nm.
Step 11：Using window is lithographically formed, dry etch process, etching and two column type semiconductor regions are recycled
6 adjacent regions form the second through-hole, and the lower surface of the second through-hole is in contact with the upper surface of public source layer 8, that is, passes through
Second through-hole can expose the upper surface of public source layer 8.Fig. 2 j are the result schematic diagram etched after horizontal channel.
Step 12：Multilayer sacrificial dielectric layer 11 is removed using wet etching, Fig. 2 k are etching multilayer sacrificial dielectric layer
Result schematic diagram after 11；The position of exposure uses atom layer deposition process, low pressure chemical after etches sacrificial dielectric layer 11
Be vapor-deposited (LPCVD) depositing TiN, wherein magnetron sputtering is that setting sputter temperature is 300 DEG C, and Fig. 2 l are the knot after depositing TiN
Fruit schematic diagram.
Step 13：TiN on second through-hole side wall is got rid of using dry etching, Fig. 2 m are the second through-hole side wall of etching
Result schematic diagram afterwards；Recycle chemical vapor deposition method, deposited in processed second through-hole first medium layer 9 with every
From two array strings, Fig. 2 n are the result schematic diagram deposited after first medium layer.
It should be noted that first medium layer 9 is by silica (SiO2) material composition.
Step 14：Using photoetching two lead hole, and the bottom of two lead hole are etched in first medium layer 9
It is contacted with the upper surface of column type semiconductor regions 6, Fig. 2 o are the result schematic diagram after photoetching lead hole.
Step 15：By magnetron sputtering or chemical vapor deposition method, two lead hole and with two leads
Trace layer 10 is formed on the adjacent first medium layer 9 of through-hole, Fig. 2 p are the result schematic diagram after trace layer is formed.
It should be noted that trace layer 10 is made of tungsten (W) material, the thickness of trace layer 10 is 200nm.
Step 10 six：Using photoetching process, the part trace layer 10 of first medium upper surface is etched away, retains position simultaneously
Trace layer 10 in two lead hole and first medium protects the lead visuals of reservation with photoresist, then
By carving lead block, to complete the preparation of three dimensional NAND Ferroelectric reservoir, Fig. 1 is that the preparation of ferroelectric storage device finishes
Result schematic diagram.
It should be noted that atomic layer deposition, chemistry can be used in ferroelectric thin film 4, high-k buffer layer 5, polysilicon
Vapor deposition etc. process deposits.In the embodiment of the present invention, to ferroelectric thin film 4, dielectric constant buffer layer 5 and polysilicon deposition
Concrete technology does not do specific restriction.
Embodiment 3
A kind of preparation method of ferroelectric memory provided in an embodiment of the present invention, mainly includes the following steps that：
Step 1：Cleaning provides horizontal substrate 1, using photoetching process, forms public source layer 8, it should be noted that light
Carving technology is using 365nm I Wiring technologies.Further, it should be noted that horizontal substrate 1 by high doped p-type silicon
(Si) material forms.
Step 2：Horizontal substrate 1 is etched, groove is formed in 1 upper surface of horizontal substrate；Polysilicon is formed in the trench, it should
The thickness value of polysilicon is equal to the depth value of groove；Further, N is carried out to polysilicon using ion implantation+Doping, to
Form pn-junction.It should be noted that forming N+It is 30KeV that type source area, which needs Implantation Energy, dosage is 1 × 1016cm-2P (31)+
Ion.Epitaxial crystallization is carried out to the polysilicon of doping using rapid thermal anneal methods, the CSL is drawn based on pn-junction, such as Fig. 2 a institutes
Show.
Step 3：Using physical vaporous deposition, multiple stackings are sequentially formed in the horizontal substrate 1 handled through step 2
Second dielectric layer 2 and sacrificial dielectric layer 11, form original array strings, Fig. 2 b are the result signal after depositing stacked structure
Figure.
It needs, second dielectric layer 2 is by silica (SiO2) material composition, the thickness of second dielectric layer 2 is
100nm；And sacrificial dielectric layer 11 is made of silicon nitride material, the thickness of sacrificial dielectric layer 11 is 100nm.
Step 4：Form window using photoetching process, then by dry etch process, etched on original array string to
Few two first through hole, and the lower surface of two first through hole is in contact with horizontal substrate 1 pass through two of etching formation the
One through-hole exposes the upper surface of horizontal substrate 1.Fig. 2 c are the result schematic diagram etched after two first through hole.
It should be noted that as shown in Figure 2 c, although public source layer 8 is located in horizontal substrate 1, due to public source
Layer 8 and 1 upper surface having the same of horizontal substrate, and the two side of first through hole respectively with the upper surface of public source layer 8 not
Contact, i.e., first through hole does not expose the upper surface of public source layer 8.
Step 5：It it is 280 DEG C in temperature, in the environment of pressure is 15hPa, by walking using atom layer deposition process
Y is deposited in two first through hole that rapid four etching processing obtains:HfO2Ferroelectric thin film 4, Fig. 2 d are deposition Y:HfO2Ferroelectric thin film
Result schematic diagram afterwards.
Step 6：Using atom layer deposition process, setting temperature is 280 DEG C, in the groove handled by step 5
Interior deposit hafnium oxides (HfO2) high-k buffer layer 5, Fig. 2 e are deposit hafnium oxides (HfO2) after high-k buffer layer 5
Result schematic diagram.
It should be noted that ferroelectric thin film 4 is by Y:HfO2Material forms, and the thickness of the ferroelectric thin film 4 is 10nm；Gao Jie
Electric constant buffer layer 5 is by hafnium oxide (HfO2) material composition, the thickness of high-k buffer layer 5 is 7nm.
Step 7：Using dry etch process, the Y of first through hole bottom is etched away:HfO2Ferroelectric thin film 4, hafnium oxide
(HfO2) high-k buffer layer 5, Fig. 2 f are the result schematic diagram after etching.
Step 8：It is in two first through hole and adjacent with two first through hole using chemical vapor deposition method
Original array string list face deposit polycrystalline silicon, Fig. 2 g are the result schematic diagram of deposit polycrystalline silicon.
Step 9：Using being lithographically formed window, then using dry etch process etching to be deposited on original array string list face heavy
Long-pending polysilicon, and the polysilicon of in first through hole and first through hole surface deposition forms column type semiconductor regions 6, i.e., in water
1 upper surface of fFlat substrate forms two column type semiconductor regions 6, and Fig. 2 h are the result schematic diagram after etches polycrystalline silicon.
It should be noted that column type semiconductor regions 6 are made of polycrystalline silicon material, the thickness of column type semiconductor regions 6 is
100nm。
Step 10：After falling the etching polysilicon being deposited on original array string list face, chemical vapor deposition work is utilized
Skill, in two column type semiconductor regions 6 and the surface adjacent with two column type semiconductor regions 6 deposition oxygen protective layer 7.Fig. 2 i are
Deposit the result schematic diagram of oxygen protective layer.
It should be noted that oxygen protective layer 7 is by silica (SiO2) material composition, the thickness of oxygen protective layer 7 is 150nm.
Step 11：Using window is lithographically formed, dry etch process, etching and two column type semiconductor regions are recycled
6 adjacent regions form the second through-hole, and the lower surface of the second through-hole is in contact with the upper surface of public source layer 8, that is, passes through
Second through-hole can expose the upper surface of public source layer 8.Fig. 2 j are the result schematic diagram etched after horizontal channel.
Step 12：Multilayer sacrificial dielectric layer 11 is removed using wet etching, Fig. 2 k are etching multilayer sacrificial dielectric layer
Result schematic diagram after 11；The position of exposure uses atom layer deposition process, low pressure chemical after etches sacrificial dielectric layer 11
Vapour deposition process (LPCVD) depositing TiN, wherein magnetron sputtering is that setting sputter temperature is 300 DEG C, and Fig. 2 l is after depositing TiNs
Result schematic diagram.
Step 13：TiN on second through-hole side wall is got rid of using dry etching, Fig. 2 m are the second through-hole side wall of etching
Result schematic diagram afterwards；Recycle chemical vapor deposition method, deposited in processed second through-hole first medium layer 9 with every
From two array strings, Fig. 2 n are the result schematic diagram deposited after first medium layer.
It should be noted that first medium layer 9 is by silica (SiO2) material composition.
Step 14：Using photoetching two lead hole, and the bottom of two lead hole are etched in first medium layer 9
It is contacted with the upper surface of column type semiconductor regions 6, Fig. 2 o are the result schematic diagram after photoetching lead hole.
Step 15：By magnetron sputtering or chemical vapor deposition method, two lead hole and with two leads
Trace layer 10 is formed on the adjacent first medium layer 9 of through-hole, Fig. 2 p are the result schematic diagram after trace layer is formed.
It should be noted that trace layer 10 is made of aluminium (Al) material, the thickness of trace layer 10 is 500nm.
Step 10 six：Using photoetching process, the part trace layer 10 of first medium upper surface is etched away, retains position simultaneously
Trace layer 10 in two lead hole and first medium protects the lead visuals of reservation with photoresist, then
By carving lead block, to complete the preparation of three dimensional NAND Ferroelectric reservoir, Fig. 1 is that the preparation of ferroelectric storage device finishes
Result schematic diagram.
It should be noted that atomic layer deposition, chemistry can be used in ferroelectric thin film 4, high-k buffer layer 5, polysilicon
Vapor deposition etc. process deposits.In the embodiment of the present invention, to ferroelectric thin film 4, dielectric constant buffer layer 5 and polysilicon deposition
Concrete technology does not do specific restriction.
Embodiment 4
A kind of preparation method of ferroelectric memory provided in an embodiment of the present invention, mainly includes the following steps that：
Step 1：Cleaning provides horizontal substrate 1, using photoetching process, forms public source layer 8, it should be noted that light
Carving technology is using 365nm I Wiring technologies.Further, it should be noted that horizontal substrate 1 by high doped p-type silicon
(Si) material forms.
Step 2：Horizontal substrate 1 is etched, groove is formed in 1 upper surface of horizontal substrate；Polysilicon is formed in the trench, it should
The thickness value of polysilicon is equal to the depth value of groove；Further, N is carried out to polysilicon using ion implantation+Doping, to
Form pn-junction.It should be noted that forming N+It is 30KeV that type source area, which needs Implantation Energy, dosage is 1 × 1016cm-2P (31)+
Ion.Epitaxial crystallization is carried out to the polysilicon of doping using rapid thermal anneal methods, the CSL is drawn based on pn-junction, such as Fig. 2 a institutes
Show.
Step 3：Using physical vaporous deposition, multiple stackings are sequentially formed in the horizontal substrate 1 handled through step 2
Second dielectric layer 2 and sacrificial dielectric layer 11, form original array strings, Fig. 2 b are the result signal after depositing stacked structure
Figure.
It needs, second dielectric layer 2 is by silica (SiO2) material composition, the thickness of second dielectric layer 2 is
200nm；And sacrificial dielectric layer 11 is made of silicon nitride material, the thickness of sacrificial dielectric layer 11 is 100nm.
Step 4：Form window using photoetching process, then by dry etch process, etched on original array string to
Few two first through hole, and the lower surface of two first through hole is in contact with horizontal substrate 1 pass through two of etching formation the
One through-hole exposes the upper surface of horizontal substrate 1.Fig. 2 c are the result schematic diagram etched after two first through hole.
It should be noted that as shown in Figure 2 c, although public source layer 8 is located in horizontal substrate 1, due to public source
Layer 8 and 1 upper surface having the same of horizontal substrate, and the two side of first through hole respectively with the upper surface of public source layer 8 not
Contact, i.e., first through hole does not expose the upper surface of public source layer 8.
Step 5：It it is 280 DEG C in temperature, in the environment of pressure is 15hPa, by walking using atom layer deposition process
Y is deposited in two first through hole that rapid four etching processing obtains:HfO2Ferroelectric thin film 4, Fig. 2 d are deposition Y:HfO2Ferroelectric thin film
Result schematic diagram afterwards.
Step 6：Using atom layer deposition process, setting temperature is 280 DEG C, in the groove handled by step 5
Interior deposit hafnium oxides (HfO2) high-k buffer layer 5, Fig. 2 e are deposit hafnium oxides (HfO2) after high-k buffer layer 5
Result schematic diagram.
It should be noted that ferroelectric thin film 4 is by Y:HfO2Material forms, and the thickness of the ferroelectric thin film 4 is 14nm；Gao Jie
Electric constant buffer layer 5 is by hafnium oxide (HfO2) material composition, the thickness of high-k buffer layer 5 is 7nm.
Step 7：Using dry etch process, the Y of first through hole bottom is etched away:HfO2Ferroelectric thin film 4, hafnium oxide
(HfO2) high-k buffer layer 5, Fig. 2 f are the result schematic diagram after etching.
Step 8：It is in two first through hole and adjacent with two first through hole using chemical vapor deposition method
Original array string list face deposit polycrystalline silicon, Fig. 2 g are the result schematic diagram of deposit polycrystalline silicon.
Step 9：Using being lithographically formed window, then using dry etch process etching to be deposited on original array string list face heavy
Long-pending polysilicon, and the polysilicon of in first through hole and first through hole surface deposition forms column type semiconductor regions 6, i.e., in water
1 upper surface of fFlat substrate forms two column type semiconductor regions 6, and Fig. 2 h are the result schematic diagram after etches polycrystalline silicon.
It should be noted that column type semiconductor regions 6 are made of polycrystalline silicon material, the thickness of column type semiconductor regions 6 is
100nm。
Step 10：After falling the etching polysilicon being deposited on original array string list face, chemical vapor deposition work is utilized
Skill, in two column type semiconductor regions 6 and the surface adjacent with two column type semiconductor regions 6 deposition oxygen protective layer 7.Fig. 2 i are
Deposit the result schematic diagram of oxygen protective layer.
It should be noted that oxygen protective layer 7 is by silica (SiO2) material composition, the thickness of oxygen protective layer 7 is 150nm.
Step 11：Using window is lithographically formed, dry etch process, etching and two column type semiconductor regions are recycled
6 adjacent regions form the second through-hole, and the lower surface of the second through-hole is in contact with the upper surface of public source layer 8, that is, passes through
Second through-hole can expose the upper surface of public source layer 8.Fig. 2 j are the result schematic diagram etched after horizontal channel.
Step 12：Multilayer sacrificial dielectric layer 11 is removed using wet etching, Fig. 2 k are etching multilayer sacrificial dielectric layer
Result schematic diagram after 11；The position of exposure uses atom layer deposition process, low pressure chemical after etches sacrificial dielectric layer 11
Be vapor-deposited (LPCVD) depositing TiN, wherein magnetron sputtering is that setting sputter temperature is 300 DEG C, and Fig. 2 l are the knot after depositing TiN
Fruit schematic diagram.
Step 13：TiN on second through-hole side wall is got rid of using dry etching, Fig. 2 m are the second through-hole side wall of etching
Result schematic diagram afterwards；Recycle chemical vapor deposition method, deposited in processed second through-hole first medium layer 9 with every
From two array strings, Fig. 2 n are the result schematic diagram deposited after first medium layer.
It should be noted that first medium layer 9 is by silica (SiO2) material composition.
Step 14：Using photoetching two lead hole, and the bottom of two lead hole are etched in first medium layer 9
It is contacted with the upper surface of column type semiconductor regions 6, Fig. 2 o are the result schematic diagram after photoetching lead hole.
Step 15：By atomic layer deposition or magnetron sputtering technique, lead in two lead hole and with two leads
Trace layer 10 is formed on the adjacent first medium layer 9 in hole, Fig. 2 p are the result schematic diagram after trace layer is formed.
It should be noted that trace layer 10 is made of aluminium (Al) material, the thickness of trace layer 10 is 500nm.
Step 10 six：Using photoetching process, the part trace layer 10 of first medium upper surface is etched away, retains position simultaneously
Trace layer 10 in two lead hole and first medium protects the lead visuals of reservation with photoresist, then
By carving lead block, to complete the preparation of three dimensional NAND Ferroelectric reservoir, Fig. 1 is that the preparation of ferroelectric storage device finishes
Result schematic diagram.
It should be noted that atomic layer deposition, chemistry can be used in ferroelectric thin film 4, high-k buffer layer 5, polysilicon
Vapor deposition etc. process deposits.In the embodiment of the present invention, to ferroelectric thin film 4, dielectric constant buffer layer 5 and polysilicon deposition
Concrete technology does not do specific restriction.
In conclusion an embodiment of the present invention provides a kind of ferroelectric memory and preparation method thereof, the preparation method is main
Including：Public source is formed by etching and ion implanting on horizontal substrate layer；By chemical gaseous phase deposition method described
Second dielectric layer and sacrificial layer are stacked on horizontal substrate layer according to this, forms original array string；By etching in the original array
String forms at least two first through hole, and the lower surface of two first through hole is in contact with the horizontal substrate layer；Two
Ferroelectric thin film layer and buffer layer are deposited in a first through hole according to this, etches the iron on two first through hole bottom surfaces
Thin film layer and the buffer layer；In two first through hole and original array string list face deposit polycrystalline silicon forms two
A column type semiconductor regions, etching the second through-hole of adjacent with two column type semiconductor regions region formation, and described the
The lower surface of two through-holes is in contact with the public source；The sacrificial layer is etched, and deposits and controls in the position of the sacrificial layer
Grid processed, etching are located at the control grid on second through-hole side wall, lead to second through-hole and with described second
Cross adjacent surface deposition first medium layer；It etches the first medium layer and is formed on two column type semiconductor regions and drawn
Line three-way hole, and by depositing and etching lead block is formed in two lead hole.The ferroelectricity prepared by this method is deposited
Reservoir uses ferroelectric thin film storage medium and substitutes floating gate charge storage medium formation metal-ferroelectricity-insulation-semiconductor
(MFIS) structure is estimated can obtain lower operation voltage, obtain higher repeatedly erasable ability and good radioresistance energy
Power.
It should be understood by those skilled in the art that, the embodiment of the present invention can be provided as method, system or computer program
Product.Therefore, complete hardware embodiment, complete software embodiment or reality combining software and hardware aspects can be used in the present invention
Apply the form of example.Moreover, the present invention can be used in one or more wherein include computer usable program code computer
The computer program production implemented in usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.)
The form of product.
The present invention be with reference to according to the method for the embodiment of the present invention, the flow of equipment (system) and computer program product
Figure and/or block diagram describe.It should be understood that can be realized by computer program instructions each in flowchart and/or the block diagram
The combination of flow and/or box in flow and/or box and flowchart and/or the block diagram.These computers can be provided
Processor of the program instruction to all-purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices
To generate a machine so that the instruction executed by computer or the processor of other programmable data processing devices generates use
In the dress for realizing the function of being specified in one flow of flow chart or multiple flows and/or one box of block diagram or multiple boxes
It sets.
These computer program instructions, which may also be stored in, can guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works so that instruction generation stored in the computer readable memory includes referring to
Enable the manufacture of device, the command device realize in one flow of flow chart or multiple flows and/or one box of block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device so that count
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, in computer or
The instruction executed on other programmable devices is provided for realizing in one flow of flow chart or multiple flows and/or block diagram one
The step of function of being specified in a box or multiple boxes.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (8)
1. a kind of preparation method of ferroelectric memory, which is characterized in that including：
Public source is formed by etching and ion implanting on horizontal substrate layer；
Second dielectric layer and sacrificial layer are stacked according to this on the horizontal substrate layer by chemical gaseous phase deposition method, are formed original
Array strings；
By etching the original array string formed at least two first through hole, and the lower surface of two first through hole with
The horizontal substrate layer is in contact；
It deposits ferroelectric thin film layer and buffer layer according to this in two first through hole, etches on two first through hole bottom surfaces
The ferroelectric thin film layer and the buffer layer；
In two first through hole and original array string list face deposit polycrystalline silicon forms two column type semiconductor regions,
The etching region adjacent with two column type semiconductor regions forms the second through-hole, and the lower surface of second through-hole and institute
Public source is stated to be in contact；
The sacrificial layer is etched, and in the position depositional control grid of the sacrificial layer, etching is located at second through-hole side wall
On the control grid, to second through-hole and pass through adjacent surface with described second and deposit first medium layer；
It etches the first medium layer and forms lead hole on two column type semiconductor regions, and by depositing and etching
Lead block is formed in two lead hole.
2. the method as described in claim 1, which is characterized in that the etching is adjacent with two column type semiconductor regions
Region is formed before the second through-hole, is specifically included：
With original array string list face deposit polycrystalline silicon in two first through hole, original array string list face is etched
Deposit polycrystalline silicon, the first through hole is interior and described first forms the column type semiconductor region by the polysilicon of the deposition on surface
Domain；
In two column type semiconductor regions and the surface deposited oxide protection adjacent with two column type semiconductor regions
Layer.
3. the method as described in claim 1, which is characterized in that the public source is located in the horizontal substrate, and described
The two side of first through hole is not contacted with the upper surface of the public source respectively.
4. the method as described in claim 1, which is characterized in that the column type semiconductor regions are made of polycrystalline silicon material, institute
The body diameter for stating column type semiconductor regions is 60nm~200nm.
5. the method as described in claim 1, which is characterized in that the material of the ferroelectric thin film is that Zr adulterates HfO2, Si doping
HfO2, Al doping HfO2, Y doping HfO2And at least one of hafnium oxide base ferroelectric material or SrBi2Ta2O9, PbTiO3,
BaTiO3, Pb (Zr, Ti) O3, (Bi, Nd)4Ti3O12, BiFeO3, YMnO3At least one of；
The thickness of the ferroelectric thin film is between 2nm~100nm；
The material of the buffer layer is Y2O3, CeO2, Al2O3, HfO2, SrTiO3, (HfO2)0.75(Al2O3)0.25In one kind or group
It closes；The thickness of the buffer layer is between 3~25nm.
6. the method as described in claim 1, which is characterized in that the first medium layer and the second dielectric layer are by silica
Material forms, and the sacrificial dielectric layer is made of silicon nitride material；
The first medium layer thickness between 50~200nm, the second medium layer thickness between for 50~150nm it
Between.
7. the method as described in claim 1, which is characterized in that the control grid electrode is by titanium nitride, tungsten, aluminium, in polysilicon
One or more kinds of combined materials composition；The control gate is between 30~100nm.
8. a kind of ferroelectric memory, which is characterized in that including horizontal substrate, the public source in the horizontal substrate is set,
Two array strings are at least arranged in the horizontal substrate upper surface, are separated by first medium layer between two array strings；
The array strings include the column type semiconductor regions perpendicular to the horizontal substrate, are located on the column type semiconductor regions
Oxygen protective layer and trace layer, wrap up the ferroelectric thin film layer of the column type semiconductor regions, buffer layer and and second medium according to this
The control grid electrode that layer mutually stacks；
Wherein, the trace layer penetrates the oxygen protective layer and is contacted with the upper surface of the column type semiconductor regions.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN109920794A (en) * | 2019-03-25 | 2019-06-21 | 中国科学院微电子研究所 | A kind of three-dimensional ferroelectric memory and its manufacturing method |
| CN110071116A (en) * | 2019-04-28 | 2019-07-30 | 中国科学院微电子研究所 | A kind of three dimensional NAND sections electrical storage, production method and operating method |
| CN110071117A (en) * | 2019-04-28 | 2019-07-30 | 中国科学院微电子研究所 | A kind of three dimensional NAND sections electrical storage, production method and operating method |
| CN111799265A (en) * | 2020-06-30 | 2020-10-20 | 湘潭大学 | Three-dimensional NAND type ferroelectric field effect transistor memory and preparation method thereof |
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| CN109461736A (en) * | 2018-10-26 | 2019-03-12 | 长江存储科技有限责任公司 | Floating gate memory device and its control method, 3D memory device and 2D memory device |
| CN109473431A (en) * | 2018-11-13 | 2019-03-15 | 中国科学院微电子研究所 | A kind of three-dimensional ferroelectric memory and preparation method thereof |
| CN109920794A (en) * | 2019-03-25 | 2019-06-21 | 中国科学院微电子研究所 | A kind of three-dimensional ferroelectric memory and its manufacturing method |
| CN109920794B (en) * | 2019-03-25 | 2020-11-03 | 中国科学院微电子研究所 | Three-dimensional ferroelectric memory and manufacturing method thereof |
| CN110071116A (en) * | 2019-04-28 | 2019-07-30 | 中国科学院微电子研究所 | A kind of three dimensional NAND sections electrical storage, production method and operating method |
| CN110071117A (en) * | 2019-04-28 | 2019-07-30 | 中国科学院微电子研究所 | A kind of three dimensional NAND sections electrical storage, production method and operating method |
| CN110071117B (en) * | 2019-04-28 | 2021-05-11 | 中国科学院微电子研究所 | Three-dimensional NAND type ferroelectric memory, manufacturing method and operating method |
| CN110071116B (en) * | 2019-04-28 | 2021-07-27 | 中国科学院微电子研究所 | Three-dimensional NAND type ferroelectric memory, manufacturing method and operating method |
| WO2021258305A1 (en) * | 2020-06-23 | 2021-12-30 | 华为技术有限公司 | Ferroelectric memory and storage device |
| CN111799265A (en) * | 2020-06-30 | 2020-10-20 | 湘潭大学 | Three-dimensional NAND type ferroelectric field effect transistor memory and preparation method thereof |
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