CN111788674B - 高频模块 - Google Patents

高频模块 Download PDF

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CN111788674B
CN111788674B CN201980016025.1A CN201980016025A CN111788674B CN 111788674 B CN111788674 B CN 111788674B CN 201980016025 A CN201980016025 A CN 201980016025A CN 111788674 B CN111788674 B CN 111788674B
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terminal assembly
substrate
main surface
terminal
wiring board
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CN111788674A (zh
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番场真一郎
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Abstract

本发明提供一种模块,通过在基板的角部安装具有与其他的部分相比尺寸较大的连接导体的端子集合体,来使针对向外部基板搭载时的应力的强度提高,而提高连接可靠性。高频模块(1)具备:部件(3a),安装于基板(2)的上表面(2a);第二密封树脂层(4),层叠于基板(2)的上表面(2a);部件(3b),安装于基板(2)的下表面(2b);第一密封树脂层(5),层叠于基板(2)的下表面(2b);以及第一端子集合体(6)及第二端子集合体(7),安装于基板(2)的下表面(2b)。第一端子集合体(6)安装于基板(2)的四角部,具有比第二端子集合体(7)的连接导体(7a)粗的连接导体(6a)。另外,各端子集合体(6、7)是多个连接导体(6a、7a)通过树脂块(6b、7b)一体化而成的,树脂块(6b、7b)所使用的树脂是介电损耗角正切比第一密封树脂层(5)还低的液晶聚合物树脂。

Description

高频模块
技术领域
本发明涉及一种安装有端子集合体的高频模块。
背景技术
以往,如专利文献1那样,提出有通过将多个柱状的端子电极经由绝缘体连结而成的端子连接基板安装到模块基板上,来以低成本并且较短的制造时间制造具备层间连接导体的模块的方法。例如,对图9所示的模块基板100而言,在基础基板101的上表面101a的表面电极上安装有电子部件102,并且安装有端子连接基板103。端子连接基板103是多个柱状的端子电极111在绝缘体112的两侧面分别配置为一列而成的。在模块基板100中,该端子连接基板103配置为大致接触基础基板101的外周的对置的两边,并且还配置于基础基板101的大致中央部分。
这样,通过利用绝缘体112将多个端子电极111连结而形成端子集合体(端子连接基板103),能够简化在模块基板100形成外部连接端子时的繁琐的工序。因此,能够减少制造成本。
专利文献1:日本专利第5510461号公报(参照0052~0072段、图5等)
然而,在将上述的模块基板100安装于外部基板时,应力施加于位于基础基板101的四角部的端子电极111,存在端子电极111易于损伤的趋势。该情况下,也考虑将位于基础基板101的四角部的端子电极111设为尺寸较大来使连接强度提高的方法,但为了在一个端子连接基板103中排列不同直径的端子电极111来形成端子连接基板103,存在端子连接基板103的制造工时增加而成本增加这样的问题。
发明内容
本发明是鉴于上述的课题而完成的,其目的在于提供一种通过使位于容易施加应力的基板角部的外部连接端子的尺寸比其他的外部连接端子大,从而安装于外部基板时的接合可靠性提高的模块。
为了实现上述的目的,本发明的模块的特征在于,具备:布线基板;多个端子集合体,设置于上述布线基板的一个主面;以及第一密封树脂层,覆盖上述布线基板的上述一个主面和上述端子集合体,上述端子集合体是多个连接导体竖立设置于树脂块而成的,上述连接导体的一个端部从上述树脂块露出而与上述布线基板的上述一个主面连接,上述端子集合体包括第一端子集合体和第二端子集合体,上述第一端子集合体具备多个上述连接导体,上述第二端子集合体具备与上述一个主面平行的方向上的尺寸比上述第一端子集合体的多个上述连接导体还小的多个上述连接导体,上述第一端子集合体配置于上述布线基板的上述一个主面的角部。
根据该结构,通过准备具有粗细不同的外部连接端子的第一端子集合体以及第二端子集合体,并在容易对模块施加应力的部分安装具有尺寸比第二端子集合体还大的外部连接端子的第一端子集合体,能够使外部连接端子的连接可靠性提高。另外,由于为了将尺寸不同的外部连接端子设置于一个端子集合体而制造工时增加,因此通过在第一端子集合体和第二端子集合体中改变外部连接端子的粗细,能够减少制造成本。
另外,在将模块向外部基板安装时,基板的角部特别容易施加应力,存在损伤的担忧,但通过在基板的角部安装与第二端子集合体相比外部连接端子的尺寸较大的第一端子集合体,能够使连接强度提高。
另外,为了实现上述的目的,本发明的其他的模块的特征在于,具备:布线基板;多个端子集合体,设置于上述布线基板的一个主面;以及第一密封树脂层,覆盖上述布线基板的上述一个主面和上述端子集合体,上述端子集合体是多个连接导体竖立设置于树脂块而成的,上述连接导体的一个端部从上述树脂块露出而与上述布线基板的上述一个主面连接,上述端子集合体包括第三端子集合体和第四端子集合体,上述第三端子集合体具备多个上述连接导体,上述第四端子集合体具备间隔比上述第三端子集合体的上述多个连接导体还宽地排列的多个上述连接导体,上述第三端子集合体配置于上述布线基板的上述一个主面的角部。
根据该结构,通过在基板的容易施加应力的部分安装外部连接端子的排列间隔较窄地形成的第三端子集合体以使外部连接端子密集,能够分散应力。因此,能够使将模块向外部基板安装时的连接可靠性提高。
另外,在将模块向外部基板安装时,基板的角部特别容易施加应力,存在损伤的担忧,但通过在基板的角部安装第三端子集合体以使外部连接端子密集来分散应力,能够使连接强度提高。
另外,也可以上述树脂块由介电损耗角正切比构成上述第一密封树脂层的树脂还小的树脂形成。根据该结构,虽然由于密封树脂层的树脂介电特性较低(介电常数或者介电损耗角正切较大),而在高频区域容易形成外部连接端子间的杂散电容,信号损失变大,但通过使用介电损耗角正切较小的树脂形成树脂块,能够减小外部连接端子间的杂散电容,能够减少信号损失。
另外,也可以还具备:部件,安装于上述布线基板的另一个主面;以及第二密封树脂层,覆盖上述布线基板的另一个主面和上述部件。根据该结构,能够提供两面安装并且连接可靠性较高的模块。
根据本发明,通过增大位于在向外部基板安装时容易施加应力的基板的角部的外部连接端子的尺寸,能够使向外部基板安装后的接合可靠性提高。
附图说明
图1是本发明的第一实施方式所涉及的模块的剖视图。
图2是图1的模块的俯视图。
图3是示出图1中被安装的端子集合体的例子的图。
图4是图1中被安装的端子集合体的示意图。
图5是示出端子集合体的一个例子的制造方法的图。
图6是示出图1的模块的制造方法的工序的一部分的图。
图7是示出图1的模块的制造方法的工序的一部分的图。
图8是示出图1的模块的制造方法的工序的一部分的图。
图9是以往的模块的剖视图。
具体实施方式
参照图1以及图2,对本发明的一实施方式所涉及的高频模块1进行说明。此外,图1的的(a)是第一实施方式所涉及的图2的高频模块1的A-A箭头方向的剖视图,图1的(b)是图2的高频模块1的B-B箭头方向的剖视图,图2是高频模块1的俯视图。
如图1以及图2所示,本实施方式所涉及的高频模块1具备:基板2,在上表面2a(相当于本发明的“另一个主面”)安装有多个部件3a,在下表面2b(相当于本发明的“一个主面”)安装有部件3b,在上表面2a层叠有第二密封树脂层4,在下表面2b层叠有第一密封树脂层5;以及多个第一端子集合体6以及第二端子集合体7,安装于基板2的下表面2b。高频模块1例如搭载于电子设备的母基板(省略图示)。
基板2例如由低温共烧陶瓷、玻璃环氧树脂等形成。在基板2的上表面2a以及下表面2b形成有多个焊盘电极8,在基板2的表层以及内层形成有多个接地电极(省略图示)、多个布线电极(省略图示)、以及多个通孔导体(省略图示)等。此外,各接地电极例如形成为从基板2的侧面露出。
各焊盘电极8、各接地电极、以及各布线电极分别由Cu、Ag、Al等作为电极一般采用的金属形成。另外,各通孔导体由Ag、Cu等金属形成。
部件3a以及部件3b例如可举出电感器、电容器、IC、功率放大器等部件。各部件3a、3b通过连接端子(省略图示)利用焊料与形成于基板2的上表面2a或者下表面2b的焊盘电极8连接,而安装于基板2的上表面2a或者下表面2b。
第二密封树脂层4设置于基板2的上表面2a以便覆盖基板2的上表面2a和各部件3a,第一密封树脂层5设置于基板2的下表面2b以便覆盖基板2的下表面2b、部件3b、以及各端子集合体6。两密封树脂层4、5能够由含有二氧化硅填料的环氧树脂等作为密封树脂一般采用的树脂形成。另外,也可以为了高热传导而使用氧化铝填料等热传导率较高的填料。
各第一、第二端子集合体6、7是由多个连接导体6a、7a排列并通过树脂块6b、7b一体化而成的。例如,能够使用如图3的(a)所示的端子集合体60那样,交错地等间隔配置的连接导体60a通过树脂块60b一体化而成的端子集合体、如图3的(b)所示的端子集合体61那样,具有大致平行地配置的一对脚部62a和将两脚部62a的一端彼此连接的桥接部62b的连接导体61a等间隔地排列并通过树脂块61b一体化而成的端子集合体。端子集合体61在安装于基板2的下表面2b后,通过层叠第一密封树脂层5并经由研磨或者研削等工序除去桥接部62b而作为高频模块1的外部连接端子发挥功能。另外,树脂块60b、61b优选由介电损耗角正切比两密封树脂层4、5所使用的树脂还低的液晶聚合物树脂形成。此外,在本实施方式的高频模块1安装有端子集合体61的形状的端子集合体。
如图2所示,在基板2的下表面2b的四角部安装第一端子集合体6,在这以外的部分安装第二端子集合体7。对第一端子集合体6而言,由于连接导体6a的粗细形成得比第二端子集合体7的连接导体7a粗,针对将高频模块1向外部基板搭载时的应力的强度比第二端子集合体7高,因此配置于特别容易施加应力的基板2的四角部。在这以外的部分安装第二端子集合体7。如图4的(a)所示,第一端子集合体6是将U字状地弯折截面形状为0.5mm见方的金属销或者金属板而成的多个连接导体6a通过由介电损耗角正切比形成第一密封树脂层5的环氧树脂还低的液晶聚合物等形成的树脂块6b一体化而成的。如图4的(b)所示,在本实施方式中2个连接导体6a通过树脂块6b一体化。另外,如图4的(c)所示,第二端子集合体7是将U字状地弯折截面形状为0.3mm见方的金属销或者金属板而成的多个连接导体7a通过由介电损耗角正切比形成第一密封树脂层5的环氧树脂还低的液晶聚合物等形成的树脂块7b一体化而成的。如图4的(d)所示,在本实施方式中8个连接导体7a通过树脂块7b一体化。
各端子集合体6、7将连接导体6a、7a的从树脂块6b、7b露出的部分亦即端部6c、7c与基板2连接,通过在形成第一密封树脂层后在研磨第一密封树脂层的下表面5a时削去桥接部6d、7d,从而形成图1的(a)、(b)所示的形状的端子集合体6、7,作为高频模块1的外部连接端子发挥功能。为了减少外部连接端子间的杂散电容并抑制信号损失,在树脂块6b、7b使用介电损耗角正切比第一密封树脂层5的树脂还小的液晶聚合物树脂。此外,连接导体6a、7a的截面形状、个数能够适当地变更。
这里,参照图5,对端子集合体60的制造方法进行说明。首先,如图5的(a)所示,对2个金属环分别实施冲压加工,形成在支承部90a、90b设置有梳齿部91a、91b的零件9a、9b。对两梳齿部91a、91b的前端实施弯曲加工,形成成为连接导体61a的多个端子部92a、92b,并进行零件9a、9b的对位。接下来,如图5的(b)所示,将各端子部92a、92b通过液晶聚合物树脂模塑,而成为各端子部92a、92b通过树脂93一体化的构造。接下来,如图5的(c)所示,从树脂93切去零件9a、9b。最后,研磨树脂93的下表面93a而完成端子集合体60。如图5的(d)所示,端子集合体60具有多个棱柱上的连接导体60a在树脂块60b内交错地排列的构造,连接导体60a树脂块60b的上表面600以及下表面601露出。
(模块的制造方法)
接下来,参照图6至图8对高频模块1的制造方法进行说明。在本第一实施方式中,在形成多个高频模块1的集合体后,通过进行单片化来制造高频模块1。此外,安装于基板2的上表面2a的部件以及第二密封树脂层4省略图示。
首先,准备在其上表面2a以及下表面2b形成有多个焊盘电极8,并且在表层或者内层形成有多个接地电极、多个布线电极、以及多个通孔导体等的基板2。关于各焊盘电极8、各接地电极、以及各布线电极,能够通过将含有Cu、Ag、Al等金属的导电性浆料进行丝网印刷等而分别形成。另外,关于各通孔导体,能够在使用激光等形成通孔后,通过公知方法形成。而且,如图6的(a)(b)所示,使用公知的表面安装技术在基板2的上表面2a安装各部件3a,另外在下表面2b安装各部件3b以及各端子集合体6、7。例如,在形成于基板2的下表面2b的焊盘电极8中的所希望的焊盘电极8上预先形成焊料,在形成有焊料的焊盘电极8中的对应的焊盘电极8上安装各部件3以及各端子集合体6、7,之后,进行回流处理。各第一端子集合体6安装于基板2的下表面2b的四角部(参照图2)。另外,各第二端子集合体7安装于基板2的下表面2b的四角部以外的部分。在本实施方式中,如图2所示,在基板2的下表面2b的四角部安装有各第一端子集合体6,在这以外的外周部安装有各第二端子集合体7,但各端子集合体6、7并不限于基板2的下表面2b的周缘部,也可以安装于基板2的下表面2b的内部。
接下来,如图7的(a)(b)所示,形成第二密封树脂层4以及第一密封树脂层5以便覆盖安装于基板2的上表面2a以及下表面2b的各部件3以及各端子集合体6、7。两密封树脂层4、5例如能够使用传递模塑方式、压缩模塑方式、液态树脂法、片状树脂法等而形成。另外,两密封树脂层4、5能够使用一般的含有二氧化硅填料的环氧树脂。此外,为了使两密封树脂层4、5具有较高的热传导性,也能够使用含有氧化铝填料等热传导率较高的填料的环氧树脂。此外,也可以在两密封树脂层4、5形成前根据需要来进行基板2的等离子体清洗。
接下来,如图8的(a)(b)所示,研磨或者研削第一密封树脂层5的下表面5a,来除去各端子集合体6、7的桥接部6d、7d。此时,也可以对从第一密封树脂层5的下表面5b露出的连接导体6a、7a实施镀Ni/Au。之后,通过切割或者激光加工等公知方法将高频模块1单片化。之后,也可以使用溅射装置、真空蒸镀装置,形成屏蔽膜以便覆盖第二密封树脂层4的表面以及第一密封树脂层5的侧面和基板2的侧面。这样一来,高频模块1完成。
根据上述的实施方式,通过在将高频模块1搭载到外部基板时容易施加应力的基板的四角部安装具有截面积比安装于其他的部分的端子集合体7的连接导体7a还大的连接导体6a的端子集合体6,能够使针对应力的强度提高,使高频模块1的向外部基板的连接可靠性提高。通过准备具有尺寸较大的连接导体6a的端子集合体6和具有尺寸较小的连接导体7a的端子集合体7这两种端子集合体,从而与在一个端子集合体设置尺寸不同的连接导体相比,能够减少制造端子集合体时的成本,进而减少高频模块1的制造成本。
另外,通过将各连接导体6a、7a一体化的树脂块6b、7b使用介电损耗角正切比第一密封树脂层5的树脂还低的液晶聚合物树脂,能够减少高频模块1的外部连接端子亦即连接导体6a、7a间的杂散电容,能够抑制信号损失。
此外,本发明不限定于上述的各实施方式,只要不脱离其主旨,就能够进行上述以外的各种变更。
例如,对端子集合体6而言,连接导体6a的粗细形成得比端子集合体7的连接导体7a的粗细大,但也可以连接导体6a的排列间隔形成得比连接导体7a的排列间隔小。即,端子集合体6的连接导体6a形成得比端子集合体7的连接导体7a密集。该情况下,能够分散将高频模块1搭载到外部基板时的应力,使连接可靠性提高。
工业可用性
本发明能够广泛地应用于在基板安装有部件并在部件间形成有屏蔽的模块。
附图标记说明
1...模块;2...基板;2a...上表面(另一个主面);2b...下表面(一个主面);3a...部件;4...第二密封树脂层;5...第一密封树脂层;6...第一端子集合体;7...第二端子集合体;6a、7a...连接导体。

Claims (6)

1.一种高频模块,其特征在于,具备:
布线基板;
多个端子集合体,设置于上述布线基板的一个主面;以及
第一密封树脂层,覆盖上述布线基板的上述一个主面和上述端子集合体,
上述端子集合体是多个连接导体竖立设置于树脂块而成的,上述连接导体的一个端部从上述树脂块露出而与上述布线基板的上述一个主面连接,
上述端子集合体包括第一端子集合体和第二端子集合体,上述第一端子集合体具备多个上述连接导体,上述第二端子集合体具备与上述一个主面平行的方向上的尺寸比上述第一端子集合体的多个上述连接导体还小的多个上述连接导体,
上述第一端子集合体仅配置于上述布线基板的上述一个主面的角部,上述第二端子集合体配置于上述布线基板的上述一个主面的上述角部以外的部分。
2.根据权利要求1所述的高频模块,其特征在于,
上述树脂块由介电损耗角正切比构成上述第一密封树脂层的树脂还小的树脂形成。
3.根据权利要求1或2所述的高频模块,其特征在于,还具备:
部件,安装于上述布线基板的另一个主面;以及
第二密封树脂层,覆盖上述布线基板的另一个主面和上述部件。
4.一种高频模块,其特征在于,具备:
布线基板;
多个端子集合体,设置于上述布线基板的一个主面;以及
第一密封树脂层,覆盖上述布线基板的上述一个主面和上述端子集合体,
上述端子集合体是多个连接导体竖立设置于树脂块而成的,上述连接导体的一个端部从上述树脂块露出而与上述布线基板的上述一个主面连接,
上述端子集合体包括第三端子集合体和第四端子集合体,上述第三端子集合体具备多个上述连接导体,上述第四端子集合体具备间隔比上述第三端子集合体的上述多个连接导体还宽地排列的多个上述连接导体,
上述第三端子集合体仅配置于上述布线基板的上述一个主面的角部,上述第四端子集合体配置于上述布线基板的上述一个主面的上述角部以外的部分。
5.根据权利要求4所述的高频模块,其特征在于,
上述树脂块由介电损耗角正切比构成上述第一密封树脂层的树脂还小的树脂形成。
6.根据权利要求4或5所述的高频模块,其特征在于,还具备:
部件,安装于上述布线基板的另一个主面;以及
第二密封树脂层,覆盖上述布线基板的另一个主面和上述部件。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008300500A (ja) * 2007-05-30 2008-12-11 Panasonic Corp 半導体装置およびその製造方法
WO2015041050A1 (ja) * 2013-09-17 2015-03-26 株式会社村田製作所 複合モジュール
CN105976981A (zh) * 2015-03-12 2016-09-28 株式会社村田制作所 线圈模块
CN106067447A (zh) * 2015-04-23 2016-11-02 三星电机株式会社 半导体封装件及其制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE602005008008D1 (de) * 2004-09-08 2008-08-21 Murata Manufacturing Co Zusammengesetztes keramisches substrat
EP1873826B1 (en) * 2005-04-18 2016-04-20 Murata Manufacturing Co., Ltd. Electronic component module
JP2007123595A (ja) 2005-10-28 2007-05-17 Nec Corp 半導体装置及びその実装構造
JP2007317754A (ja) * 2006-05-24 2007-12-06 Matsushita Electric Ind Co Ltd 半導体装置
JP5538682B2 (ja) * 2008-03-06 2014-07-02 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
CN102792785A (zh) * 2010-04-13 2012-11-21 株式会社村田制作所 模块基板、模块基板的制造方法、以及端子连接基板
JP6071439B2 (ja) * 2011-11-30 2017-02-01 キヤノン株式会社 フタロシアニン結晶の製造方法、および電子写真感光体の製造方法
WO2014020787A1 (ja) * 2012-08-03 2014-02-06 パナソニック株式会社 電子部品モジュールとその実装体
KR101983142B1 (ko) * 2013-06-28 2019-08-28 삼성전기주식회사 반도체 패키지
KR20150035251A (ko) * 2013-09-27 2015-04-06 삼성전기주식회사 외부접속단자부와 외부접속단자부를 갖는 반도체 패키지 및 그들의 제조방법
BR112015029665A2 (pt) * 2014-12-26 2017-07-25 Intel Corp arquitetura de montagem que emprega suporte orgânico para produção de montagem compacta e aprimorada.

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008300500A (ja) * 2007-05-30 2008-12-11 Panasonic Corp 半導体装置およびその製造方法
WO2015041050A1 (ja) * 2013-09-17 2015-03-26 株式会社村田製作所 複合モジュール
CN105976981A (zh) * 2015-03-12 2016-09-28 株式会社村田制作所 线圈模块
CN106067447A (zh) * 2015-04-23 2016-11-02 三星电机株式会社 半导体封装件及其制造方法

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