CN111785773A

CN111785773A - Semiconductor structure, high electron mobility transistor and semiconductor structure manufacturing method

Info

Publication number: CN111785773A
Application number: CN201910271137.3A
Authority: CN
Inventors: 林永丰; 周政道
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp; Vanguard International Semiconductor America
Priority date: 2019-04-04
Filing date: 2019-04-04
Publication date: 2020-10-16

Abstract

The invention provides a semiconductor structure, a high electron mobility transistor and a manufacturing method of the semiconductor structure. The semiconductor structure comprises a substrate, a flowable dielectric material pad layer, a reflow protection layer and a gallium nitride series semiconductor layer. The substrate has an excavation exposed from an upper surface of the substrate. A cushion layer of flowable dielectric material is formed in the cavity, and an upper surface of the cushion layer of flowable dielectric material is below an upper surface of the substrate. A reflow protection layer is formed on the upper surfaces of the substrate and the flowable dielectric material pad layer. The gallium nitride semiconductor layer is disposed on the reflow protection layer.

Description

Semiconductor structure, high electron mobility transistor and semiconductor structure manufacturing method

Technical Field

The present invention relates to semiconductor manufacturing technology, and more particularly to a semiconductor structure having a gallium nitride based semiconductor material, a high electron mobility transistor, and a method for manufacturing the same.

Background

Gallium nitride-based (GaN-based) semiconductor materials have many excellent material characteristics, such as high heat resistance, wide band-gap (band-gap), and high electron saturation velocity. Therefore, the gallium nitride based semiconductor material is suitable for high speed and high temperature operation environment. In recent years, gallium nitride-based semiconductor materials have been widely used in Light Emitting Diode (LED) devices, high frequency devices such as High Electron Mobility Transistors (HEMTs) having a hetero interface structure, and the like.

With the development of gallium nitride-based semiconductor materials, these semiconductor structures using gallium nitride-based semiconductor materials are applied in more severe operating environments, such as higher frequency, higher temperature, or higher voltage operating environments. Therefore, the process conditions of the semiconductor structure having the gallium nitride based semiconductor material also face many new challenges.

Disclosure of Invention

Some embodiments of the present invention provide a semiconductor structure comprising a substrate, a flowable dielectric material pad layer, a reflow protection layer, and a gallium nitride-based semiconductor layer (GaN-based). The substrate has a pit (pit) exposed from an upper surface of the substrate. A cushion layer of flowable dielectric material is formed in the cavity, and an upper surface of the cushion layer of flowable dielectric material is below an upper surface of the substrate. A reflow protection layer is formed on the upper surfaces of the substrate and the flowable dielectric material pad layer. The gallium nitride semiconductor layer is disposed on the reflow protection layer.

Some embodiments of the present invention provide a High Electron Mobility Transistor (HEMT) comprising an aluminum nitride substrate, a flowable dielectric material underlayer, a reflow protection layer, a gallium nitride semiconductor layer, a gallium aluminum nitride semiconductor layer, a source electrode, a drain electrode, and a gate electrode. The aluminum nitride substrate has a pit exposed from an upper surface of the aluminum nitride substrate. A flowable dielectric material pad layer is formed in the hole, and an upper surface of the flowable dielectric material pad layer is located below an upper surface of the aluminum nitride substrate. The reflow protection layer is formed on the upper surfaces of the aluminum nitride substrate and the flowable dielectric material pad layer. The gallium nitride semiconductor layer is arranged on the backflow protection layer. The gallium nitride aluminum semiconductor layer is arranged on the gallium nitride semiconductor layer. The source electrode, the drain electrode and the gate electrode are disposed on the gallium aluminum nitride semiconductor layer.

Some embodiments of the present invention provide methods of fabricating a semiconductor structure, the method comprising providing a substrate having a cavity exposed from an upper surface of the substrate; forming a flowable dielectric material on a substrate; performing a thermal process to reflow the flowable dielectric material into the pits; removing the flowable dielectric material outside the cavity and exposing the upper surface of the substrate to form a cushion layer of the flowable dielectric material in the cavity, wherein the upper surface of the cushion layer of the flowable dielectric material is located below the upper surface of the substrate; forming a reflow protection layer on the upper surfaces of the substrate and the flowable dielectric material pad layer; and forming a gallium nitride-based semiconductor layer on the reflow protection layer.

The semiconductor structure of the present invention can be applied to various types of semiconductor devices, and in order to make the features and advantages of the present invention more comprehensible, embodiments applied to a high electron mobility transistor are specifically described below with reference to the accompanying drawings.

Drawings

In order to make the features and advantages of the present invention comprehensible, various embodiments accompanied with figures are described in detail as follows:

fig. 1A-1G are schematic cross-sectional views illustrating the formation of a substrate structure at various stages according to some embodiments of the invention.

Fig. 2 is a cross-sectional schematic view illustrating a high electron mobility transistor formed using the substrate structure of fig. 1F, in accordance with some embodiments of the present invention.

Reference numerals:

50-active area;

100. 100' -a substrate structure;

102-a substrate;

102a, 116 a-upper surface;

103-hole;

104-defect;

105-pits;

106 flowable dielectric material;

107. 108-refluxing the protective layer;

108A, 108B-projecting portion;

109 to a gallium nitride semiconductor layer;

110-a buffer layer;

112-gallium nitride semiconductor layer;

114-gallium aluminum nitride semiconductor layer;

116. 126-flowable dielectric material pad layer;

117-isolation structures;

118 source/drain electrodes;

120-gate electrode;

150-heat treatment;

160. 170-planarization process;

200-high electron mobility transistor;

d-depth;

w-width;

p-diameter;

t1, T2, T3 and T4.

Detailed Description

The following invention provides many embodiments or examples for implementing various elements of the provided semiconductor structures. Specific examples of the elements and their configurations are described below to simplify the description of the embodiments of the present invention. These are, of course, merely examples and are not intended to limit the embodiments of the invention. For example, references in the description to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. Moreover, the same or similar element numbers may be reused in different instances of embodiments of the present invention. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments discussed.

Some variations of the embodiments are described below. Like reference numerals are used to designate like elements in the various figures and described embodiments. It will be understood that additional steps may be provided before, during, or after the method, and that some of the recited steps may be substituted or deleted in other embodiments of the method.

Embodiments of the invention provide semiconductor structures and High Electron Mobility Transistors (HEMTs) and methods of fabricating the same. In general, a semiconductor device including a gallium nitride semiconductor material is generally formed over a ceramic substrate. Since the ceramic substrate formed by powder metallurgy may have pits on the surface thereof, when the ceramic substrate is used in a semiconductor process, a material layer formed on the substrate may be formed in the pits, adversely affecting a semiconductor device. Embodiments of the present invention provide a method for fabricating a semiconductor structure, the method comprising forming a flowable dielectric material on a substrate, reflowing the flowable dielectric material to the cavities by thermal processing to form a flowable dielectric material pad in the cavities, and depositing a reflow protection layer on the flowable dielectric material pad to fill the cavities, such that the substrate structure has a planar surface for a subsequent semiconductor process, and the reflow protection layer can prevent the flowable dielectric material from causing adverse effects on semiconductor materials or devices in the subsequent semiconductor process due to secondary reflow caused by the subsequent high temperature process, thereby improving the yield of semiconductor devices.

Fig. 1A-1G are schematic cross-sectional views illustrating various stages in the formation of a substrate structure 100' as shown in fig. 1G, in accordance with some embodiments of the present invention. Referring to fig. 1A, a substrate 102 is provided. The substrate 102 may be circular and the diameter P of the substrate 102 may be 4 inches or more, such as 6 inches, 8 inches, or 12 inches, to accommodate manufacturing equipment in the semiconductor industry.

The substrate 102 essentially contains a number of defects 104, the defects 104 including holes 103 in the substrate 102 and pits 105 exposed from the upper surface 102a of the substrate 102. In some embodiments, the substrate 102 is a ceramic substrate and is formed by high temperature sintering of a ceramic powder by powder metallurgy. For example, the substrate 102 is an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, a Sapphire (Sapphire) substrate, a suitable similar substrate, or any combination thereof. In some embodiments, the voids between the ceramic powders gradually shrink during sintering of the ceramic powders to fabricate the substrate 102, but do not completely disappear after sintering of the ceramic powders is completed. Thus, some defects 104 remain on the surface and interior of the substrate 102. In addition, even if the sintered substrate 102 is polished to remove the surface pits 105, the holes 103 in the substrate 102 will be exposed, and new pits 105 will be formed on the upper surface 102a of the substrate 102.

In some embodiments, the substrate 102 is used to fabricate a semiconductor device containing a gallium nitride-based (GaN-based) semiconductor layer, such as a light-emitting diode (LED), a high frequency device, or a high voltage device. The high frequency device or the high voltage device may be, for example, a High Electron Mobility Transistor (HEMT), a Schottky Bipolar Diode (SBD), a Bipolar Junction Transistor (BJT), a Junction Field Effect Transistor (JFET), or an Insulated Gate Bipolar Transistor (IGBT).

It should be noted that although the pit 105 illustrated in fig. 1A has an arc-shaped cross-sectional profile, the type of the pit 105 is not limited thereto. In some embodiments, the pit 105 may have an irregular cross-sectional profile (not shown). In the cross-sectional view shown in fig. 1A, the pothole 105 may have a width W measured in a lateral direction and a depth D measured in a longitudinal direction. In some embodiments of the present invention, when depth D of pit 105 is greater than width W, the size of pit 105 may be defined as its depth D; conversely, when the width W of pit 105 is greater than the depth D, the size of pit 105 may be defined as its width W. In general, in some embodiments, the size of the crater 105 may be in a range from about 0.5 micrometers (μm) to about 15 micrometers.

Referring to fig. 1B, a flowable dielectric material 106 is formed on the upper surface 102a of the substrate 102. In the embodiment shown in fig. 1B, flowable dielectric material 106 is conformally formed in pits 105. The flowable dielectric material 106 has a thickness T1, for example, on the upper surface 102a of the substrate 102. In some embodiments, since the size of most of voids 105 is greater than thickness T1 of flowable dielectric material 106, most of voids 105 are not filled with flowable dielectric material 106.

In embodiments of the present invention, the flowable dielectric material 106 is solid at room temperature, and when the flowable dielectric material 106 is heated by the thermal process, the heated flowable dielectric material 106 is liquid-like flowable, and reflowing occurs. In other words, the flowable dielectric material 106 is a dielectric material that is not flowable at low temperatures and is flowable at high temperatures. In some embodiments, the flowable dielectric material 106 may comprise spin-on glass (SOG), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), fluorosilicate glass (FSG), suitable similar materials, or any combination thereof. In some embodiments, the flowable dielectric material 106 may be formed by spin-on coating (spin-on coating), Chemical Vapor Deposition (CVD), a similar method as applicable, or any combination thereof.

Next, referring to fig. 1C, after forming the flowable dielectric material 106, the substrate 102 with the flowable dielectric material 106 formed thereon is subjected to a thermal process 150 to render the flowable dielectric material 106 flowable for reflow. As shown in fig. 1C, in an embodiment of the present invention, flowable dielectric material 106 is reflowed into voids 105 by thermal treatment 150. In an embodiment, the thermal treatment may result in a reduced thickness T2 of the flowable dielectric material 106 on the upper surface 102a of the substrate 102 and an increased thickness T3 of the flowable dielectric material 106 within the pit 150, although most of the pit 105 may still not be filled with the flowable dielectric material 106. For example, thickness T3 is greater than thickness T1, and thickness T1 is greater than thickness T2.

According to an embodiment of the present invention, reflowing (reflowing) flowable dielectric material 106 into pits 105 by thermal treatment 150 can reduce the extent to which semiconductor material subsequently grown on upper surface 102a of substrate 102 grows in pits 105, thereby avoiding the occurrence of critical defects (killers) in semiconductor devices formed in pits 105, and thus improving the yield of semiconductor devices. Furthermore, the flowable dielectric material 106 that can flow through the thermal process 150 is used to fill the voids 105, which can significantly reduce the deposition thickness and process time of the dielectric material used to fill the voids 105, thereby reducing the manufacturing cost.

In some embodiments of the present invention, the temperature of the heat treatment 150 is, for example, 300 ℃ to 800 ℃.

In some embodiments, the flowable dielectric material 106 is, for example, spin-on-glass (SOG), the temperature of the heat treatment 150 is, for example, in the range of about 300 ℃ to about 500 ℃, such as about 350 ℃ to about 450 ℃, and the heat treatment time may be in the range of about 20 minutes to about 60 minutes. When the heat treatment temperature is less than about 300 ℃, the spin-on glass (SOG) may not reflow, and when the heat treatment temperature is greater than about 500 ℃, the spin-on glass (SOG) may be too fluid and expand, so that cracks may occur between the spin-on glass (SOG) and the substrate 102 after the temperature is reduced, and even the substrate 102 may crack.

In some embodiments in which flowable dielectric material 106 is spin-on-glass (SOG), a ratio of thickness T1 of flowable dielectric material 106 on upper surface 102a of substrate 102 relative to a dimension of pit 105 (e.g., depth D of pit 105) may be about 0.15 to about 0.6, e.g., may be in a range of about 0.15 to about 0.3, and a ratio of thickness T3 of reflowed flowable dielectric material 106 within pit 105 relative to a dimension of pit 105 (e.g., depth D of pit 105) may be about 0.15 to about 0.8, e.g., about 0.3 to about 0.8, after thermal treatment 150.

In some embodiments, the flowable dielectric material 106 is, for example, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and/or fluorosilicate glass (FSG), the temperature of the heat treatment 150 is, for example, in a range from about 600 ℃ to about 800 ℃, such as from about 650 ℃ to about 800 ℃, and the heat treatment time may be in a range from about 20 minutes to about 60 minutes. When the heat treatment temperature is less than about 600 ℃, the borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and/or fluorosilicate glass (FSG) may not reflow, and when the heat treatment temperature is greater than about 800 ℃, the mobility of the borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and/or fluorosilicate glass (FSG) may be too high and expand, such that after cooling, cracks may occur between the flowable dielectric material 106 and the substrate 102, and even the substrate 102 may crack.

In some embodiments where flowable dielectric material 106 is borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and/or fluorosilicate glass (FSG), a ratio of thickness T1 of flowable dielectric material 106 on upper surface 102a of substrate 102 relative to a dimension of pit 105 (e.g., depth D of pit 105) may be about 0.3 to about 0.6, such as may be in a range of about 0.3 to about 0.6, and a ratio of thickness T3 of reflowed flowable dielectric material 106 within pit 105 relative to a dimension of pit 105 (e.g., depth D of pit 105) may be about 0.3 to about 0.8 after thermal treatment 150.

Next, referring to fig. 1D, the portion of the flowable dielectric material 106 outside the cavity 105 is removed and the upper surface 102a of the substrate 102 is exposed, so as to form flowable

dielectric material pads

116 and 126 in the cavity 105. In one embodiment, as shown in FIG. 1D, the upper surface 116a of the flowable dielectric material pad layer 116 is below the upper surface 102a of the substrate 102.

In some embodiments, as shown in fig. 1D, the flowable dielectric material 106 may be removed outside the cavity 105 by performing a planarization process 160 on the flowable dielectric material 106 to form the flowable

dielectric material pads

116 and 126. In some embodiments, the planarization process 160 is, for example, Chemical Mechanical Polishing (CMP).

In some embodiments, as shown in fig. 1D, the upper surface 116a of the flowable dielectric material pad 116 has a concave (concave) profile. In some embodiments, as shown in fig. 1D, the top surface of the flowable dielectric material pad 126 is substantially coplanar with the top surface 102a of the substrate 102.

In some embodiments, as shown in fig. 1D, the ratio of thickness T3 of flowable dielectric material pad 116 to depth D of pothole 105 is, for example, about 0.15 to about 0.8.

Next, referring to fig. 1E, in some embodiments, the reflow protection layer 107 may be conformally deposited on the substrate 102 and the upper surface 116a of the flowable dielectric material pad layer 116 by a deposition process. In some embodiments, the reflow protection layer 107 is also conformally deposited on the flowable dielectric material pad layer 126. In some embodiments, the reflow protection layer 107 is blanket deposited over and covers the flowable dielectric material pad layers 116 and 126.

In the embodiment of the present invention, the reflow protection layer 107 is a film with good thermal stability and high quality at high temperature compared to the flowable dielectric material 106. In some embodiments, the material of the reflow protection layer 107 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or any combination thereof. In some embodiments, the process temperature for depositing the reflow protection layer 107 is, for example, 1000 ℃ to 1200 ℃. In some embodiments, the process of forming the reflow protection layer 107 may include Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), or a combination thereof.

In some embodiments, the reflow protection layer 107 is a silicon oxide film made of Tetraethoxysilane (TEOS), for example, by Low Pressure Chemical Vapor Deposition (LPCVD). In some embodiments, the reflow protection layer 107 is a dielectric layer formed by Plasma Enhanced Chemical Vapor Deposition (PECVD), for example, which may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, suitable similar materials, or combinations thereof.

Next, referring to fig. 1F, in some embodiments, the reflow protection layer 107 may be partially removed by performing a planarization process 170 on the reflow protection layer 107 to form a reflow protection layer 108 having a flat upper surface. In some embodiments, the planarization process 170 is, for example, Chemical Mechanical Polishing (CMP). At this point, the reflow protection layer 108 is formed on the substrate 102, the flowable dielectric material pad layer 126 and the upper surface 116a of the flowable dielectric material pad layer 116.

In an embodiment, after the planarization process 170, the substrate structure 100 is formed as shown in FIG. 1F. The substrate structure 100 has a substantially planar upper surface (i.e., the planarized upper surface of the reflow protection layer 108) that may be provided for forming semiconductor devices thereon.

In some embodiments, as shown in fig. 1F, the reflow protection layer 108 is conformally deposited on the upper surface 116a of the pad layer 116 of the flowable dielectric material, such that the reflow protection layer 108 has a protruding portion 108B, and the protruding portion 108B extends into and fills the cavity 105.

In some embodiments, as shown in fig. 1F, the protruding portion 108B of the reflow protection layer 108 directly contacts the upper surface 116a of the flowable dielectric material pad layer 116. In some embodiments, as shown in fig. 1F, the lower surface of the protruding portion 108B of the reflow protection layer 108 conforms to the upper surface 116a of the flowable dielectric material pad layer 116.

According to some embodiments of the present invention, when the flowable dielectric material 106 is used to achieve the aforementioned advantages of reducing the manufacturing cost and the processing time, the flowable dielectric material 106 is thermally processed to have high fluidity, which may cause the pits 105 to be not completely filled, and the protruding portion 108B of the reflow protection layer 108 extends into and fills the pits 105 to be conformally formed on the upper surface 116a of the flowable dielectric material pad 116, so that the pits 105 that are not filled with the flowable dielectric material 106 can be further filled, thereby ensuring perfect repair of the defects of the substrate 102 and improving the manufacturing yield of the semiconductor device.

Furthermore, according to some embodiments of the present invention, the reflow protection layer 108 may be an insulating protection layer formed through a high temperature process, and when a subsequent semiconductor process uses a process temperature higher than a temperature at which the flowable dielectric material 106 undergoes a secondary reflow, the reflow protection layer 108 may prevent the flowable dielectric material 106 (i.e., the flowable dielectric material pads 116 and 126) from overflowing, expanding, or bursting due to the secondary reflow, and thus may prevent the high temperature of the subsequent semiconductor process from adversely affecting the semiconductor material formed on the flowable dielectric material 106 (i.e., the flowable dielectric material pads 116 and 126), such as, for example, preventing peeling (peeling) or cracking (crack) of the subsequent semiconductor material or device.

Next, referring to fig. 1G, a gallium nitride-based (GaN-based) semiconductor layer 109 is formed on the reflow protection layer 108. In some embodiments, the gallium nitride-based semiconductor layer 109 includes, for example, a gallium nitride semiconductor layer 112, an aluminum gallium nitride semiconductor layer 114, other suitable similar gallium nitride-based semiconductor layers, or any combination thereof, as described herein below.

In some embodiments, the gallium nitride-based semiconductor layer 109 may be formed by an epitaxial growth process, such as Metal Organic Chemical Vapor Deposition (MOCVD), Hydride Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE), the like, where applicable, or any combination thereof. In some embodiments, the process temperature for forming the gallium nitride based semiconductor layer 109 is higher than the temperature of the thermal treatment of the flowable dielectric material 106. In some embodiments, the process temperature for forming the gallium nitride based semiconductor layer 109 is, for example, higher than 800 ℃. In some embodiments, the process temperature for forming the gallium nitride-based semiconductor layer 109 is, for example, higher than 1000 ℃.

In the embodiment of the present invention, after the gallium nitride-based semiconductor layer 109 is formed, the substrate structure 100' as shown in fig. 1G is formed. According to an embodiment of the present invention, the substrate structure 100 or 100 'has a flat upper surface, and thus a device including a gallium nitride-based semiconductor material may be formed on the substrate structure 100 or 100'. For example, the semiconductor device including the gallium nitride-based semiconductor material may be, for example, a Light Emitting Diode (LED), a High Electron Mobility Transistor (HEMT), a schottky diode (SBD), a Bipolar Junction Transistor (BJT), a Junction Field Effect Transistor (JFET), an Insulated Gate Bipolar Transistor (IGBT), or the like. An embodiment of forming a semiconductor device on the substrate structure 100 of fig. 1F is described below, taking a High Electron Mobility Transistor (HEMT) as an example.

Fig. 2 is a cross-sectional schematic view illustrating a high electron mobility transistor formed using the substrate structure of fig. 1F, in accordance with some embodiments of the present invention. In this embodiment, the same or similar elements as those in the previous embodiment are labeled with the same or similar elements, and the description of the same or similar elements is referred to the foregoing description, and will not be repeated herein.

In general, the breakdown voltage (breakdown voltage) of a High Electron Mobility Transistor (HEMT) mainly depends on the thickness of a gallium nitride (GaN) semiconductor layer as a channel layer. For example, increasing the thickness of the gan semiconductor layer by 1 μm can increase the breakdown voltage (breakdown voltage) of a High Electron Mobility Transistor (HEMT) by about 100 v. During the epitaxial growth process for forming the gallium nitride semiconductor layer, it is necessary to use a substrate having high thermal conductivity and high mechanical strength to deposit the gallium nitride semiconductor material thereon, which may otherwise cause the substrate to bend or even crack. Therefore, the aluminum nitride substrate has higher thermal conductivity and higher mechanical strength relative to the silicon substrate to form a thicker gallium nitride semiconductor layer on the aluminum nitride substrate. For example, a gallium nitride semiconductor layer may be formed on a silicon substrate surface to a thickness of about 2 to 4 microns. The thickness of the gallium nitride semiconductor layer that can be formed on the surface of the aluminum nitride substrate can reach 5 to 15 micrometers.

Referring to fig. 2, a substrate structure 100 as shown in fig. 1F is provided. Fig. 2 shows a portion of the substrate structure 100 of fig. 1F, wherein the portion of the substrate structure 100 has some pits 105 therein, and the remaining elements of the hemt 200 are formed on the portion of the substrate structure 100. In the embodiment shown in fig. 2, the substrate 102 is an aluminum nitride substrate.

Although some processes for fabricating the remaining elements of the hemt 200 may have a temperature higher than 500 c or even higher than 800 c, according to embodiments of the present invention, the reflow protection layer 108 is formed on the upper surfaces of the substrate 102 and the

pads

116 and 126 of the flowable dielectric material and covers the

pads

116 and 126 of the flowable dielectric material, thereby protecting the semiconductor materials or elements formed in the subsequent semiconductor processes from the adverse effects of the second reflow of the flowable dielectric material.

In some embodiments, the hemt 200 may include a buffer layer 110 and a gallium nitride semiconductor layer 112, the buffer layer 110 being formed on an upper surface of the reflow protective layer 108, the gallium nitride semiconductor layer 112 being formed on the buffer layer 110. In some embodiments, the hemt 200 may include an aluminum gallium nitride semiconductor layer 114 formed on the gallium nitride semiconductor layer 112 and a seed layer (not shown) formed between the reflow protection layer 108 and the buffer layer 110.

In some embodiments, the material of the seed layer may be aluminum nitride (AlN), aluminum oxide (Al2O3), aluminum gallium nitride (AlGaN), silicon carbide (SiC), aluminum (Al), or any combination thereof, and the seed layer may be a single or multi-layer structure. The seed layer may be formed by an epitaxial growth process, such as Metal Organic Chemical Vapor Deposition (MOCVD), Hydride Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE), the like, or any combination thereof.

In some embodiments, the buffer layer 110 may relieve strain (strain) of the gallium nitride semiconductor layer 112 subsequently formed over the buffer layer 110 to prevent defects from forming in the overlying gallium nitride semiconductor layer 112, which may be caused by a mismatch between the gallium nitride semiconductor layer 112 and the substrate 102. In some embodiments, the material of the buffer layer 110 may be AlN, GaN, AlxGa1-xN (where 0< x <1), a similar material as applicable, or any combination thereof. In some embodiments, buffer layer 110 may be formed by an epitaxial growth process, such as Metal Organic Chemical Vapor Deposition (MOCVD), Hydride Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE), similar methods as applicable, or any combination thereof. Although the buffer layer 110 has a single-layer structure in the embodiment shown in fig. 2, the buffer layer 110 may have a multi-layer structure. In addition, in some embodiments, the material of the buffer layer 110 is determined by the material of the seed layer and the gas introduced during the epitaxial process.

In the hemt 200, a two-dimensional electron gas (2 DEG) (not shown) may be formed at the hetero-interface between the gallium nitride semiconductor layer 112 and the gallium aluminum nitride semiconductor layer 114. In some embodiments, there is no dopant in gallium nitride semiconductor layer 112 and gallium aluminum nitride semiconductor layer 114. In some other embodiments, the gallium nitride semiconductor layer 112 and the aluminum gallium nitride semiconductor layer 114 may have dopants, such as n-type dopants or p-type dopants. The gallium nitride semiconductor layer 112 and the gallium aluminum nitride semiconductor layer 114 may be formed by an epitaxial growth process, such as Metal Organic Chemical Vapor Deposition (MOCVD), Hydride Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE), the like, where applicable, or any combination thereof.

In accordance with some embodiments of the present invention, as shown in fig. 2, since substrate 102 is an aluminum nitride substrate having high thermal conductivity and high mechanical strength, gallium nitride semiconductor layer 112 may be deposited to a thickness T4 in a range from about 5 microns to about 15 microns.

In some embodiments, the hemt 200 may include an isolation structure 117, wherein the isolation structure 117 is formed in the gan semiconductor layer 112 and the gan aluminum semiconductor layer 114 to define the active region 50. The material of the isolation structure 117 may be a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, suitable similar materials, or any combination thereof. Also, the isolation structure 117 may be formed through an etching process and a deposition process.

In some embodiments, the hemt 200 may include source/drain electrodes 118 and a gate electrode 120 interposed between the source/drain electrodes 118, the source/drain electrodes 118 and the gate electrode 120 being formed on the aluminum gallium nitride semiconductor layer 114 in the active region 50. In some embodiments, the material of the source/drain electrodes 118 and the gate electrode 120 may be a conductive material, such as a metal, a metal nitride, or a semiconductor material. The metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), similar materials as applicable, or any combination thereof. The semiconductor material may be polysilicon or poly-germanium. The step of forming the source/drain electrodes 118 and the gate electrode 120 may include depositing a conductive material on the gallium aluminum nitride semiconductor layer 114 and patterning the conductive material to form the source/drain electrodes 118 and the gate electrode 120. The source/drain electrodes 118 and the gate electrode 120 may be formed in the same process, or may be formed separately in different processes.

The foregoing outlines several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, comprising:

a substrate having a hole exposed from an upper surface thereof;

a flowable dielectric material pad layer formed in the hole, an upper surface of the flowable dielectric material pad layer being below the upper surface of the substrate;

a reflow protection layer formed on the substrate and the upper surface of the flowable dielectric material pad layer; and

a GaN semiconductor layer disposed on the reflow protection layer.

2. The semiconductor structure of claim 1, wherein said upper surface of said flowable dielectric material liner has a concave profile.

3. The semiconductor structure of claim 1, wherein a ratio of a thickness of said flowable dielectric material pad layer to a depth of said pit is 0.15 to 0.8.

4. The semiconductor structure of claim 1, wherein a protruding portion of said reflow protection layer extends into and fills said pit.

5. The semiconductor structure of claim 4, wherein said protruding portion of said reflow protection layer directly contacts said upper surface of said flowable dielectric material pad layer.

6. The semiconductor structure of claim 4, wherein a lower surface of said protruding portion of said reflow protection layer conforms to said upper surface of said flowable dielectric material liner.

7. The semiconductor structure of claim 1, wherein the substrate is an aluminum nitride substrate, a silicon carbide substrate, a sapphire substrate, or any combination thereof.

8. The semiconductor structure of claim 1, wherein the flowable dielectric material pad comprises spin-on glass, borophosphosilicate glass, phosphosilicate glass, borosilicate glass, fluorosilicate glass, or any combination thereof.

9. The semiconductor structure of claim 1, wherein the reflow protection layer comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or any combination thereof.

10. A high electron mobility transistor, comprising:

an aluminum nitride substrate having a hole exposed from an upper surface thereof;

a flowable dielectric material pad layer formed in the hole, an upper surface of the flowable dielectric material pad layer being located below the upper surface of the aluminum nitride substrate;

a reflow protection layer formed on the upper surfaces of the aluminum nitride substrate and the flowable dielectric material pad layer;

a gallium nitride semiconductor layer disposed on the reflow protection layer;

a gallium aluminum nitride semiconductor layer disposed on the gallium nitride semiconductor layer; and

a source electrode, a drain electrode and a gate electrode disposed on the GaN-Al semiconductor layer.

11. The hemt of claim 10, wherein said gan semiconductor layer has a thickness of 5 to 15 microns.

12. A method of fabricating a semiconductor structure, comprising:

providing a substrate, wherein the substrate is provided with a pit exposed from the upper surface of the substrate;

forming a flowable dielectric material on the substrate;

performing a thermal process to reflow the flowable dielectric material into the cavity;

removing the portion of the flowable dielectric material outside the cavity and exposing the upper surface of the substrate to form a cushion of flowable dielectric material in the cavity, wherein an upper surface of the cushion of flowable dielectric material is below the upper surface of the substrate;

forming a reflow protection layer on the substrate and the upper surface of the flowable dielectric material pad layer; and

a GaN-based semiconductor layer is formed on the reflow protection layer.

13. The method of claim 12, wherein the substrate is an aluminum nitride substrate, a silicon carbide substrate, a sapphire substrate, or any combination thereof.

14. The method of claim 12, wherein the flowable dielectric material comprises spin-on glass, borophosphosilicate glass, phosphosilicate glass, borosilicate glass, fluorosilicate glass, or any combination thereof.

15. The method of claim 12, wherein the heat treatment is performed at a temperature of 300 ℃ to 800 ℃.

16. The method of claim 12, wherein the reflow protection layer comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or any combination thereof.

17. The method of claim 12, wherein the reflow protection layer is conformally deposited on the substrate and the upper surface of the flowable dielectric material pad layer by a deposition process.

18. The method of claim 17, wherein the process temperature for depositing the reflow protection layer is between 1000 ℃ and 1200 ℃.

19. The method of claim 12, wherein the step of forming the reflow protection layer comprises plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, or a combination thereof.

20. The method according to claim 12, wherein a process temperature for forming the gallium nitride based semiconductor layer is higher than a temperature of the heat treatment.