CN111767634B - Method for establishing IGBT switch transient model - Google Patents

Method for establishing IGBT switch transient model Download PDF

Info

Publication number
CN111767634B
CN111767634B CN202010426807.7A CN202010426807A CN111767634B CN 111767634 B CN111767634 B CN 111767634B CN 202010426807 A CN202010426807 A CN 202010426807A CN 111767634 B CN111767634 B CN 111767634B
Authority
CN
China
Prior art keywords
voltage
igbt
collector
current
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010426807.7A
Other languages
Chinese (zh)
Other versions
CN111767634A (en
Inventor
罗毅飞
朱庆祥
刘宾礼
李鑫
肖飞
黄永乐
贾英杰
唐欣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Naval University of Engineering PLA
Original Assignee
Naval University of Engineering PLA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Naval University of Engineering PLA filed Critical Naval University of Engineering PLA
Priority to CN202010426807.7A priority Critical patent/CN111767634B/en
Publication of CN111767634A publication Critical patent/CN111767634A/en
Application granted granted Critical
Publication of CN111767634B publication Critical patent/CN111767634B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Conversion In General (AREA)

Abstract

The invention relates to a method for establishing an IGBT switch transient model, which comprises the following steps: dividing the switching-on transient into 5 stages; establishing an opening relation set; dividing the turn-off transient into 5 phases; establishing a turn-off relation set; establishing an IGBT simulation model which comprises an input module, an acquisition unit, an IGBT transient characteristic calculation unit and an output module; the input module transmits the external parameters to the acquisition unit; the acquisition unit transmits the acquired IGBT external parameters to the IGBT transient characteristic calculation unit; the IGBT transient characteristic calculation unit simulates and synchronously transmits a simulation result to the output module; and outputting the simulation result by the output module. According to the invention, a modeling method based on relevant physical parameters in the IGBT is adopted, and a model which can accurately represent transient electrical characteristics of the IGBT switch and can be used for complex circuit simulation is established; the cost is reduced, and the power density of the device is improved; the reliability of the device is improved, and potential safety hazards are reduced.

Description

Method for establishing IGBT switch transient model
Technical Field
The invention relates to the field of power electronic device modeling, in particular to a method for establishing an IGBT switch transient model.
Background
Insulated Gate Bipolar Transistor (IGBT) is widely used in the field of power conversion and the like due to its advantages of high switching speed, convenience in control and the like, and research show that, in power electronic devices with a voltage level of more than 300V and a power level of more than 10kW, an IGBT power module has become the most widely used power electronic switching device. The turn-on and turn-off of the IGBT is a transient process of microsecond level, is a complex non-ideal and non-linear process influenced by external circuits and internal parameters, and can generate voltage and current spikes higher than those generated during steady-state operation. When the IGBT is switched on, overcurrent may be caused by current spikes generated by reverse recovery currents of the parallel freewheeling diodes; when the IGBT is turned off, voltage spikes due to stray inductance of the line distribution, etc., may cause overvoltage breakdown, and even eventually cause device and even device damage. Therefore, the transient characteristics of the IGBT switching process, particularly the voltage and current spikes, are a problem that must be considered when designing power electronics-related devices.
The accurate analysis of the operating characteristics of the IGBT is a precondition and a basis for application. However, since domestic manufacturers start late, most of core data such as process parameters are mastered by the domestic manufacturers, it is difficult for domestic personnel to directly obtain the operating characteristics of the IGBT through models such as finite elements, and modeling cannot be performed completely based on a data manual.
Currently, in the design task of the IGBT-related device, there are generally three approaches: the ideal model of the commercial software is adopted, the latest physical model and the traditional design method are adopted.
The disadvantages of the current ideal model of commercial software are: the transient electrical characteristics of the IGBT switch cannot be accurately reflected.
Although recent physical models and the like have achieved a lot of results, the disadvantages are: the research results up to now are difficult to use for complex circuit simulation.
Currently, the mainstream method still adopts the traditional design method, that is, a method with a large margin is adopted during design, but the traditional design method has the following disadvantages:
1. the method can not realize accurate characterization and effective simulation of the transient characteristics of the device switch in the complex circuit, and is difficult to provide effective guidance for the precise design of the device.
2. Increasing cost and reducing device power density.
3. The rugged design also brings hidden trouble to the reliability of the device.
Disclosure of Invention
Aiming at the problems, the invention provides a method for establishing an IGBT switch transient model, and establishes a model which can accurately represent the transient electrical characteristics of the IGBT switch and can be used for complex circuit simulation.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
the method for establishing the IGBT switch transient model is suitable for complex circuit simulation and comprises the following steps:
s100, dividing the IGBT switching-on transient state into 5 stages, and specifically comprising the following steps: the method comprises a switching-on delay stage, a current rising stage, a voltage steep-falling stage, a voltage tailing stage and a grid voltage rising stage.
Establishing a switching-on relation set under a switching-on transient state according to main internal parameters of the IGBT physical model; the set of turn-on relationships includes a collector-emitter voltage, a collector-emitter current, and a gate voltage, wherein: the grid voltage controls the turn-on of the IGBT; the voltage of the collector and emitter is the voltage at two ends of the collector and emitter in the turn-on process of the IGBT; the current of the collector and the emitter is the current flowing through the collector and the emitter in the turn-on process of the IGBT;
dividing the IGBT turn-off transient into 5 phases, specifically including: a turn-off delay stage, a voltage ramp-up stage, a current ramp-down stage and a current tail stage.
Establishing a turn-off relation set of collector-emitter voltage, collector-emitter current and grid voltage under a turn-off transient state according to main internal parameters of an IGBT physical model; the set of turn-off relationships includes the collector-emitter voltage, collector-emitter current, and gate voltage, wherein: the gate voltage controls the turn-off of the IGBT; the voltage of the collector and emitter is the voltage at two ends of the collector and emitter in the turn-off process of the IGBT; the current of the collector and the emitter is the current flowing through the collector and the emitter in the turn-off process of the IGBT;
s300, collecting and outputting external parameters of the IGBT; the external parameters of the IGBT comprise a driving signal, bus voltage, temperature and input current, wherein: the input current is measured by an ammeter in a branch associated with the IGBT; the temperature is IGBT junction temperature and is preset manually or coupled with a heat transfer network; the bus voltage is manually preset according to the setting parameters of the power supply;
establishing expressions of collector-emitter voltage, collector-emitter current and grid voltage under the switching relation set; establishing expressions of collector-emitter voltage, collector-emitter current and gate voltage under the switching-off relation set;
establishing an IGBT simulation model according to main internal parameters of an IGBT physical model, expressions of collector-emitter voltage, collector-emitter current and grid voltage under the switching-on relation set and expressions of collector-emitter voltage, collector-emitter current and grid voltage under the switching-off relation set; the main internal parameters of the IGBT physical model comprise a gate-drain electrode overlapping area, a gate-emitter electrode capacitance, a gate oxide layer capacitance, an IGBT base region doping concentration, an IGBT transconductance, an IGBT base region electron mobility and an IGBT base region hole mobility; the IGBT simulation model comprises an input module, an acquisition unit, an IGBT transient characteristic calculation unit and an output module; wherein:
the input module transmits external parameters of the IGBT to the acquisition unit; the input module comprises a driving module; the driving module adds the driving signal to the external parameters of the IGBT; the input module processes the driving signal and the emitter current to obtain time information and current value information when the driving signal changes; the input module comprises a driving signal input end, a bus voltage input end, a temperature signal input end and an input current signal input end; the acquisition unit transmits the acquired external parameters of the IGBT to the transient characteristic calculation unit of the IGBT; the IGBT transient characteristic calculation unit simulates the collector-emitter voltage, the collector-emitter current and the grid voltage of the IGBT in time according to the acquired external parameters of the IGBT and by combining the expressions of main internal parameters of the physical model of the IGBT, the collector-emitter voltage, the collector-emitter current and the grid voltage under the switching-on transient state and the expressions of the collector-emitter voltage, the collector-emitter current and the grid voltage under the switching-off transient state, and synchronously transmits the simulation results of the collector-emitter voltage, the collector-emitter current and the grid voltage of the IGBT to the output module; the output module outputs simulation results of the collector-emitter voltage, the collector-emitter current and the grid voltage of the IGBT.
Preferably, in the turn-on delay phase, the expression of collector-emitter current and collector-emitter voltage is:
I CE ＝0；V CE ＝V DC
wherein, I CE Is the collector-emitter current; v CE Is the collector-emitter voltage; v DC Is the bus voltage.
In the turn-on delay stage, the expression of the gate voltage is:
Figure RE-GDA0002657884650000041
wherein, V GE Is the gate voltage; v GGf The negative voltage value representing the grid voltage is provided by external parameters of the IGBT; v GGn A positive voltage value representing the gate voltage, provided by an IGBT external parameter; t represents the current time; t is t 0 The starting time of the turn-on delay stage is represented and is calculated from the moment when the IGBT switch is turned on; r g The driving resistance is represented and is manually preset during circuit design or obtained by a driver board user manual; c GE Represents the gate capacitance, obtained from the device handbook.
In the current rise phase, the expression of the collector-emitter current is:
I CE ＝I n +I P
wherein, I p For hole current, it is calculated as follows:
Figure RE-GDA0002657884650000042
wherein the content of the first and second substances,
Figure RE-GDA0002657884650000043
τ Hb 、τ Ab 、τ r five intermediate quantities related to the internal parameters of the device are obtained by deducing an IGBT physical model; the derivation of the IGBT physical model comprises the doping concentration of a base region, the width of the base region, the service life of excess carriers of the base region, the doping concentration of a buffer layer, the width of the buffer layer, the service life of excess carriers of the buffer layer, the carrier mobility, the area of a chip and the voltage of the IGBT device; b L To representAn electron to hole mobility ratio, derived from the ratio of electron to hole mobility; q T The total charge quantity in the IGBT is expressed and obtained by a semiconductor charge control equation.
I n For electron current, it is calculated as follows:
Figure RE-GDA0002657884650000051
wherein, I MOS The current flowing through the MOS channel is represented and obtained by a MOSFET current characteristic expression; c DSJ Representing the capacitance between a drain electrode and a source electrode in the MOS structure, and obtaining the capacitance from physical model parameters; v ds Representing the drain-source voltage in the MOS structure, this phase V ds ＝V CE 。
The expression for the miller plateau voltage is:
Figure RE-GDA0002657884650000052
wherein, V ml Is the Miller plateau voltage; v T Threshold voltage, obtained from the device handbook; k P Transconductance, obtained from the device handbook; i is Lm The current value is the current value at the ending moment of the current rising stage and is obtained by processing of the signal acquisition unit; beta is the channel current coefficient and is calculated according to the following formula:
β＝I mos /I CE
the semiconductor physical formula is calculated as follows:
Figure RE-GDA0002657884650000053
in the formula, A GD Is the gate-drain overlap area; epsilon si Is the dielectric constant of silicon; q is an electron charge amount constant; n is a radical of L Is the n-base region doping concentration.
Miller capacitance C GD (t) is:
Figure RE-GDA0002657884650000054
in the voltage steep drop phase and the voltage tail phase, the voltage is in the Miller plateau phase V ml And (3) if the voltage drop slope in each stage is constant, calculating according to the following formula:
Figure RE-GDA0002657884650000061
C GDa for equivalent capacitance, it is calculated as follows:
Figure RE-GDA0002657884650000062
wherein, V Cn ＝V CE2 /3；C OXD A gate oxide layer capacitor, obtained from a device handbook; wherein V GD ＝V ml -V T Is the demarcation point of the change of the Miller capacitance; v CE2 Is t 2 The gate voltage at the time is calculated by the following equation.
Figure RE-GDA0002657884650000063
The expression for the collector-emitter voltage is:
Figure RE-GDA0002657884650000064
wherein, t 2 The end time of the current rising phase and the start time of the voltage steep-falling phase are calculated according to the following formula:
Figure RE-GDA0002657884650000065
t 3 the end time of the voltage steep-drop stage is also the start time of the voltage tailing stage; t is t 4 For voltage trailingThe end time of the stage is also the start time of the grid voltage rising stage; can be calculated from the following formula:
Figure RE-GDA0002657884650000071
Figure RE-GDA0002657884650000072
Figure RE-GDA0002657884650000073
wherein, V on For on-state voltage drop, available from device handbook, k 22 、k 23 、k 34 Is t 2 ～t’ 2 、t’ 2 ～t 3 、t 3 ～t 4 The slope of the voltage over the time period.
Preferably, in the turn-off delay phase, the expression of the gate voltage is:
Figure RE-GDA0002657884650000077
wherein, t 6 The start of the turn-off delay phase is calculated from the instant the IGBT switch is turned off.
Similar to the opening phase, wherein C GDa For equivalent capacitance, it is calculated as follows:
Figure RE-GDA0002657884650000074
in the formula (I), the compound is shown in the specification,
Figure RE-GDA0002657884650000075
in the voltage ramp-up stage and the voltage ramp-up stage, the expression of the collector-emitter voltage is as follows:
Figure RE-GDA0002657884650000076
in the formula, t 7 The end time of the turn-off delay stage is also the start time of the voltage ramp-up stage; t is t 8 The end time of the voltage gradual rising stage is also the start time of the voltage steep rising stage; t is t 9 The end time of the voltage steep-rise stage and the start time of the current steep-fall stage are also provided; t' 8 For the voltage to reach V cf The time point of (a); similar to the turn-on phase, the time point of this phase can be calculated by the following formula:
Figure RE-GDA0002657884650000081
Figure RE-GDA0002657884650000082
Figure RE-GDA0002657884650000083
wherein k is 78 、k 88 、k 89 Is t 7 ～t 8 、t 8 ～t’ 8 、t 8 ～t 9 The slope of the voltage over the time period.
In the current steep drop phase, at t' 9 The moment the collector-emitter voltage reaches a maximum value; t' 9 Is t 9 And t 10 Intermediate value of (1), t' 9 ＝(t 9 +t 10 ) /2, wherein t 10 The end time of the current steep-off phase and the start time of the current tail-off phase are calculated according to the following formula:
Figure RE-GDA0002657884650000084
the maximum value of the collector-emitter voltage is calculated as follows:
Figure RE-GDA0002657884650000085
wherein, V CEm Is the maximum value of the collector-emitter voltage; l is s The line stray inductance is obtained by external circuit measurement; r is s The stray resistance of the line is measured by an external circuit; i is Lm The value of the collector-emitter current collected at this stage; i is tail For the initial value of the tail current, it is calculated as follows:
I tail ＝I p ＝I Lm -I n ＝(1-β)I Lm
k 910 for the current ramp-down slope, it is calculated as follows:
Figure RE-GDA0002657884650000086
in the current tail phase, the collector-emitter current is calculated as follows:
Figure RE-GDA0002657884650000087
wherein, I Keff And τ eff Is a diffusion coefficient with holes D P Buffer layer width W H The doping concentration N of the Buffer layer H And Buffer layer carrier lifetime τ H The two constants of the correlation can be obtained by experiment or data manual information calculation.
Preferably, the IGBT simulation model is built in a Simulink tool box in MATLAB software by adopting an S-Function mode.
Preferably, the IGBT simulation model further includes a clock unit; and the clock unit simultaneously provides synchronous clock signals for the acquisition unit and the IGBT transient characteristic calculation unit.
Preferably, the method comprises the following steps:
s400, simplifying 5 stages of the IGBT turn-off transient stateThe method comprises 2 stages: the on-state voltage rises to a voltage spike section and the voltage spike falls to a bus voltage section; the starting time of the on-state voltage rising to the voltage spike section is t 6 The ending time is t f1 (ii) a The end time when the voltage spike drops to the bus voltage section is t 10 The starting time is calculated as follows:
t f1 ＝(t 6 +t 10 )/2
wherein, t f1 The starting moment when the voltage spike drops to the bus voltage segment.
Compared with the prior art, the invention has the following advantages:
1. the modeling method based on the internal relevant physical parameters of the IGBT is creatively adopted, and different from the modeling method based on a data manual completely, a model which can accurately represent the transient electrical characteristics of the IGBT switch and can be used for the simulation of a complex circuit is established;
2. the cost is reduced, and the power density of the device is improved;
3. the influence of temperature on the IGBT switch transient state can be reflected;
4. the reliability of the device is improved, and potential safety hazards are reduced.
Drawings
FIG. 1 is a schematic flow chart of an embodiment of the present invention.
Fig. 2 is a schematic diagram of an on-transient segmentation according to an embodiment of the present invention.
Fig. 3 is a sectional view of a turn-off transient state according to an embodiment of the present invention.
FIG. 4a is a schematic diagram illustrating the effect of temperature on model parameters and electrical characteristics during the on-state of an embodiment of the present invention.
FIG. 4b is a schematic diagram illustrating the effect of temperature on model parameters and electrical characteristics during the off-transient state in accordance with an embodiment of the present invention.
FIG. 5a is a comparison graph of simulation results of a simplified model and a physical model in a stepwise manner at a transient state of startup according to an embodiment of the present invention.
FIG. 5b is a graph comparing simulation results of a simplified model and a physical model at an ON transient for temperature in accordance with an embodiment of the present invention.
FIG. 6 is a schematic diagram of the Simulink model according to an embodiment of the present invention.
FIG. 7 is a schematic diagram of a simulation of three-phase inversion according to an embodiment of the present invention
FIG. 8 shows a three-phase inverter circuit of an embodiment of the present invention at V DC The experimental waveform, the Simulink ideal model and the transient result comparison graph of the model are compared in 400V real-time simulation.
Fig. 9 is a schematic diagram of an optimized model turn-off transient segmentation according to an embodiment of the present invention.
FIG. 10a shows a three-phase inverter circuit of an embodiment of the present invention at V DC Graph of voltage simulation results for one fundamental period at 400V.
FIG. 10b shows a three-phase inverter circuit of an embodiment of the present invention at V DC Voltage experiment oscillogram of one fundamental wave period when the voltage is 400V.
Fig. 11a is a diagram illustrating a current simulation result of one fundamental wave period of the three-phase inverter circuit according to the embodiment of the present invention.
Fig. 11b is a waveform diagram of a current experiment of a fundamental wave period of a three-phase inverter circuit according to an embodiment of the invention.
Wherein the solid lines in fig. 5a and 5b both represent simplified models and the dashed lines both represent physical models; the solid line in fig. 8 represents the experimental waveform, the broken line represents the simplified model, and the dotted line represents the ideal model; the dotted line in fig. 9 represents the model curve before simplification, and the solid line represents the model curve after simplification.
Detailed Description
The present invention is further illustrated by the following examples, which are intended to be purely exemplary and are not intended to limit the scope of the invention, as various equivalent modifications of the invention will occur to those skilled in the art upon reading the present disclosure and fall within the scope of the appended claims.
It should be noted that, in this specific embodiment, the IGBT simulation model is built in the Simulink toolbox in MATLAB software by using an S-Function method. The CPU model of the computer used in the simulation is AMD 1600X, the running memory is 16G. In a fixed-step mode, under the same step length, the simulation time of the model is about 20 times of that of an ideal model, and the simulation time and the step length are in a basically direct proportional relation. Although the internal functions of the segmented model are basically linear functions with simple operation and the like, the time length is longer than that for the simulation of an ideal model due to the small step length and the large number of calculation points. This is not a problem of computational complexity of the model itself. Therefore, the model simulation efficiency can be improved in a mode of reasonably setting the step length. To ensure the integrity of sampling transient processes, the model needs to be implemented in a small step (about 10) -9 s) simulation was performed.
As shown in fig. 1, a method for establishing an IGBT switching transient model to which the present invention is applied includes the following steps:
as shown in fig. 2, S100, dividing the IGBT turn-on transient state into 5 stages, specifically including: the method comprises a switching-on delay stage, a current rising stage, a voltage steep-falling stage, a voltage tailing stage and a grid voltage rising stage.
Establishing a switching-on relation set under a switching-on transient state according to main internal parameters of the IGBT physical model; the switching-on relation set comprises collector-emitter voltage, collector-emitter current and grid voltage, wherein the grid voltage controls the switching-on of the IGBT; the voltage of the collector and emitter is the voltage at two ends of the collector and emitter in the turn-on process of the IGBT; the collector-emitter current is the current flowing through the collector-emitter in the turn-on process of the IGBT; the time domain representation of three important characteristic quantities of voltage at two ends of the on-off transient IGBT, current flowing through the IGBT and a grid voltage control signal is realized.
In the on-delay phase, the expression of collector-emitter current and collector-emitter voltage is formula (1):
I CE ＝0；V CE ＝V DC (1)
wherein, I CE Is the collector-emitter current; v CE Is the collector-emitter voltage; v DC Is the bus voltage.
In the turn-on delay stage, the expression of the gate voltage is formula (2):
Figure RE-GDA0002657884650000121
wherein, V GE Is the gate voltage; v GGf The negative voltage value representing the grid voltage is provided by external parameters of the IGBT; v GGn A positive voltage value representing the gate voltage, provided by an IGBT external parameter; t represents the current time; t is t 0 The starting time of the turn-on delay stage is represented and is calculated from the moment when the IGBT switch is turned on; r g The driving resistance is represented and is manually preset during circuit design or obtained by a driver board user manual; c GE Representing the gate capacitance, obtained from the device handbook; according to the IGBT physical model and the working mechanism, at t 0 At the moment, the IGBT grid driving voltage is driven from a negative voltage V GGf Becomes positive pressure V GGn At t 1 Time gate voltage V GE Rises to a threshold voltage V T . At this stage, the inversion layer is not formed, and the electrons have no conduction channel, so that the MOSFET is not turned on.
In the current rising phase, according to the IGBT physical model and the working mechanism, at t 1 At that time, an inversion layer is formed, an electron conduction channel is formed, and the MOSFET starts to conduct. Collector-emitter current I at this stage CE Rises rapidly at t 2 At the moment of time to reach I Lm Then, a current spike appears due to the reverse recovery action of the diode; the current change results in V due to the presence of line stray inductance CE Down to V CE2 ；V GE Since the capacitor continues to charge, at t 2 Rise to the Miller plateau voltage V at that moment ml . The expression of the collector-emitter current is formula (3):
I CE ＝I n +I P (3)
wherein, I p For the hole current, it is calculated as equation (4):
Figure RE-GDA0002657884650000122
wherein the content of the first and second substances,
Figure RE-GDA0002657884650000123
τ Hb 、τ Ab 、τ r five intermediate quantities related to the internal parameters of the device are obtained by deducing an IGBT physical model; the derivation of the IGBT physical model comprises the doping concentration of a base region, the width of the base region, the service life of excess carriers of the base region, the doping concentration of a buffer layer (a field stop layer), the width of the buffer layer, the service life of the excess carriers of the buffer layer, the carrier mobility, the chip area and the voltage of the IGBT device; b L Represents a value of electron-to-hole mobility ratio, which is obtained from the ratio of electron-to-hole mobility; q T The total charge quantity in the IGBT is expressed and obtained by a semiconductor charge control equation.
I n For the electron current, it is calculated as equation (5):
Figure RE-GDA0002657884650000131
wherein, I MOS The current flowing through the MOS channel is represented and obtained by a MOSFET current characteristic expression; c DSJ Representing the capacitance between a drain electrode and a source electrode in the MOS structure, and obtaining the capacitance from physical model parameters; v ds Representing the drain-source voltage in the MOS structure, this phase V ds ＝V CE 。
The expression for the miller plateau voltage is formula (6):
Figure RE-GDA0002657884650000132
wherein, V ml Is the Miller plateau voltage; v T As threshold voltage, obtained from the device handbook; k P Is transconductance, obtained from the device handbook; i is Lm The current value is the current value at the ending moment of the current rising stage and is obtained by processing of the signal acquisition unit; β is a channel current coefficient, and is calculated according to equation (7):
β＝I mos /I CE (7)
the semiconductor physical formula is calculated according to equation (8):
Figure RE-GDA0002657884650000133
in the formula, A GD Is the gate-drain overlap area; epsilon si Is the dielectric constant of silicon; q is an electron charge amount constant; n is a radical of hydrogen L Is the n-base region doping concentration.
Miller capacitance C GD (t) is calculated by the following equation (9):
Figure RE-GDA0002657884650000134
in the voltage steep drop stage and the voltage tail stage, the voltage is reduced due to the Miller plateau stage V ml Without changing, let the voltage drop slope in each stage be k, the formula (10) can be obtained from the circuit formula,
Figure RE-GDA0002657884650000141
C GDa is t 2 ～t' 2 、t' 2 ～t 3 、t 3 ～t 4 The equivalent capacitance in the time period is calculated according to equation (11):
Figure RE-GDA0002657884650000142
the reason for this division is V CE From V CE2 Down to V on The variation is large. For the sake of analysis, assume this stage V CE Is linearly varied, and t is 2 ～t 4 Is divided into three segments, respectively t 2 ～t' 2 、t' 2 ～t 3 、t 3 ～t 4 . Wherein, due to the fact that at t 2 ～t 4 In the stage, according to the IGBT physical model and the working mechanism, at t 2 At the moment, the quasi-neutral base region shrinks rapidly due to the rapid expansion of the depletion region, V CE Begins to decrease sharply, t 3 Down to V at any time GD (ii) a Then, because of the conductance modulation effect generated in the quasi-neutral base region, V CE Continues to decrease, but the excess carrier diffusion rate disappears from the base region at this timeAt a slower speed, so that V CE The decline becomes slow, the trailing phenomenon appears, finally at t 4 Momentarily dropping to the on voltage. In this stage, the voltage is changed sharply to make the Miller capacitance increase rapidly, and the gate current is supplied to the Miller capacitance C GD Charging, so that the capacitor C GE Voltage V across GE The miller plateau is maintained constant. In the phase, the change rate of the voltage is gradually reduced when the voltage is steeply dropped, and the steeply dropped process is divided into two sections for fitting representation: v Cn ＝V CE2 /3；C OXD A gate oxide layer capacitor, obtained from a device handbook; wherein V GD ＝V ml -V T Is the demarcation point of the change of the Miller capacitance; v CE2 Is t 2 The gate voltage at that time is calculated by equation (12).
Figure RE-GDA0002657884650000143
The expression of the collector-emitter voltage is formula (13):
Figure RE-GDA0002657884650000151
wherein, t 2 The end time of the current rising phase and the start time of the voltage steep-falling phase are calculated according to equation (14):
Figure RE-GDA0002657884650000152
t 3 the end time of the voltage steep drop stage is also the start time of the voltage tailing stage; t is t 4 The end time of the voltage tailing stage is also the starting time of the grid voltage rising stage; can be calculated from equation (15):
Figure RE-GDA0002657884650000153
wherein, V on Is at on-state voltage dropObtainable from the device handbook, k 22 、k 23 、k 34 Is t 2 ～t’ 2 、t’ 2 ～t 3 、t 3 ～ t 4 The slope of the voltage over the time period.
Assume that the slope of the diode recovery current is α I Get t 1 To t d The expression for the step current rise is formula (16):
I CE (t)＝α I (t-t 2 )+I Lm (16)
assuming that the current drop during reverse recovery of the diode is-alpha in slope I It is at t' d At a time falling to I Lm . Can obtain t' d Is represented by formula (17):
Figure RE-GDA0002657884650000154
wherein, the first and the second end of the pipe are connected with each other,
Figure RE-GDA0002657884650000155
wherein the fitting coefficient a 1 、b 1 、a 2 、b 2 、c 2 Can be extracted through experimental data or physical model simulation results.
Let the voltage V at time t2 CE2 Obtaining V CE2 Is represented by formula (18):
Figure RE-GDA0002657884650000161
this phase voltage can be characterized by equation (19):
Figure RE-GDA0002657884650000162
and at t 4 ～t 5 Stage (2): according to the IGBT physical model and the working mechanism, in the stage I CE Since the inductive load continues to rise linearly, V CE Maintaining the on-state voltage drop, V GE Rising to a driving positive voltage V according to a capacitor charging rule GGn 。
As shown in fig. 3, the IGBT turn-off transient is divided into 5 stages, which specifically include: a turn-off delay stage, a voltage ramp-up stage, a current ramp-down stage and a current tail stage.
Establishing a turn-off relation set of collector-emitter voltage, collector-emitter current and grid voltage under a turn-off transient state according to main internal parameters of an IGBT physical model; the turn-off relation set comprises a collector-emitter voltage, a collector-emitter current and a gate voltage, wherein the gate voltage controls turn-off of the IGBT; the collector-emitter voltage is the voltage at the two ends of the collector-emitter in the turn-off process of the IGBT; the collector-emitter current is the current flowing through the collector-emitter in the turn-off process of the IGBT; the time domain representation of three important characteristic quantities of voltage at two ends of the turn-off transient IGBT, current flowing through the IGBT and a grid voltage control signal is realized.
In the turn-off delay stage, according to the IGBT physical model and the working mechanism, the stage V GE Via a capacitor C OXD 、 C GE Discharge to Miller plateau V ml (ii) a This stage V CE Substantially maintaining the on-state pressure drop V on The change is not changed; i is CE And (4) increasing linearly.
Based on an IGBT physical model and a working mechanism, a method for solving the voltage of the Miller platform as a key quantity at the stage is the same as the method for solving the voltage of the Miller platform in the switching-on transient state, so that the expression of the obtained grid voltage is formula (20):
Figure RE-GDA0002657884650000163
wherein, t 6 The start of the turn-off delay phase is calculated from the instant the IGBT switch is turned off.
Similar to the opening phase, wherein C GDa Calculating the equivalent capacitance according to (21):
Figure RE-GDA0002657884650000171
in the formula (I), the compound is shown in the specification,
Figure RE-GDA0002657884650000172
at t of which 7 ～t 8 、t 8 ～t′ 8 、t′ 8 ～t 9 Equivalent linear capacitance in phase of C GDa 。
In the voltage ramp-up stage and the voltage ramp-up stage, according to an IGBT physical model and an operating mechanism, at t 7 At the beginning of time, the depletion layer begins to expand to t 8 The depletion layer expands to a maximum at that time, so V CE First slowly rises to V GD Then begins to ramp up, as in the method in the turn-on transient, V CE The steep rise stage is fitted in two linear stages and is set at t' 8 Reaches V at all times Cf Reaches the bus voltage V at the moment DC 。V GE The miller plateau is maintained constant. I is CE Is substantially unchanged.
Based on the IGBT physical model and the working mechanism, the solution of the critical quantity at the stage is similar to the method in the switching-on transient state:
the expression of the collector-emitter voltage is formula (22):
Figure RE-GDA0002657884650000173
in the formula, t 7 The end time of the turn-off delay stage is also the start time of the voltage ramp-up stage; t is t 8 The end time of the voltage gradual rising phase is also the start time of the voltage steep rising phase; t is t 9 The end time of the voltage steep-rise stage and the start time of the current steep-fall stage are also provided; t' 8 For the voltage to reach V cf The time point of (a); similar to the opening phase, the time point of this phase can be calculated by equation (23):
Figure RE-GDA0002657884650000181
wherein k is 78 、k 88 、k 89 Is t 7 ～t 8 、t 8 ～t’ 8 、t 8 ～t 9 The slope of the voltage over the time period.
In the current steep drop phase, according to the IGBT physical model and the working mechanism, the phase is V GE Less than a threshold voltage V T The conduction channel is closed, the electron current disappears, the hole current is relatively slow due to the diffusion and recombination effects, and the current I CE Starting tailing; collector-emitter voltage V CE Maintaining the bus voltage unchanged; grid capacitance C GE The discharge is continued through the gate resistor, and the gate voltage V GE And (4) descending. At t 9 Moment the Miller platform ends, V GE At t 10 Falling to threshold voltage V at time T (ii) a The electron current path is closed due to the disappearance of the channel, I CE Rapidly drops to a tail current value I tail (ii) a VCE at t 'due to effects of line stray inductance and the like' 9 The collector-emitter voltage reaches the maximum value at the moment; t' 9 Is t 9 And t 10 Intermediate value of (1), t' 9 ＝(t 9 +t 10 )/2. Wherein, t 10 The end time of the current steep-falling phase and the start time of the current tailing phase are calculated according to the formula (24):
Figure RE-GDA0002657884650000182
the maximum value of the collector-emitter voltage is calculated by equation (25):
Figure RE-GDA0002657884650000183
wherein, V CEm Is the maximum value of the collector-emitter voltage; l is s The line stray inductance is obtained by external circuit measurement; r s The stray resistance of the line is measured by an external circuit; i is Lm The value of the collector-emitter current collected at this stage; i is tail For the initial value of the tail current, it is calculated as equation (26):
I tail ＝I p ＝I Lm -I n ＝(1-β)I Lm (26)
k 910 for the current decrease slope, it is calculated as equation (27):
Figure RE-GDA0002657884650000184
in the current tailing stage, the current tailing stage process is simplified according to a physical model modeling mechanism, and the collector-emitter current is calculated according to the formula (28):
Figure RE-GDA0002657884650000191
wherein, I Keff And τ eff Is the diffusion coefficient with holes D P Width W of Buffer layer H The doping concentration N of the Buffer layer H And Buffer layer carrier lifetime τ H The two constants of the correlation can be obtained by experiment or data manual information calculation.
S200, correcting the main internal parameters of the IGBT physical model according to the influence of the temperature in the switching-on transient state and the switching-off transient state on the main internal parameters of the IGBT physical model.
The influence of the temperature on the switching characteristics of the IGBT is reflected on the model, namely, the parameters in the model are changed. The mechanism of influence of the internal parameters of the model with temperature change is shown in fig. 4a and 4 b. The change rule of the IGBT internal parameters along with the temperature is generally obtained by performing parameter correction according to the formula (29):
Figure RE-GDA0002657884650000192
wherein V T(T0) 、K P(T0) 、μ n(T0) 、μ p(T0) Respectively representing the threshold voltage, transconductance, electron mobility and hole mobility at T 0 Typical value at temperature. Alpha is 0.88T j -0.146 ，T 0 Generally 300K, T j Is an arbitrary set temperature. FIGS. 5a and 5b show the temperature profile at different temperatures, respectivelyThe simulation results of the segment simplified model and the physical model are obviously compared.
S300, collecting and outputting external parameters of the IGBT; the external parameters of the IGBT comprise a driving signal, bus voltage, temperature and input current, wherein: the input current is measured by an ammeter in the branch associated with the IGBT; the temperature is the IGBT junction temperature and is preset manually or coupled with a heat transfer network; the bus voltage is manually preset according to the setting parameters of the power supply;
establishing expressions of collector-emitter voltage, collector-emitter current and grid voltage under the switching relation set; establishing expressions of collector-emitter voltage, collector-emitter current and gate voltage under the switching-off relation set;
as shown in fig. 6, establishing an IGBT simulation model according to the main internal parameters of the IGBT physical model, the expressions of the collector-emitter voltage, the collector-emitter current, and the gate voltage in the set of on-relations, and the expressions of the collector-emitter voltage, the collector-emitter current, and the gate voltage in the set of off-relations; the main internal parameters of the IGBT physical model comprise a gate-drain electrode overlapping area A GD Gate-emitter capacitance C GE And a gate oxide layer capacitor C OXD IGBT base region doping concentration N L IGBT transconductance K P IGBT base region electron mobility mu n IGBT base region hole mobility rate mu p (ii) a The IGBT simulation model comprises an input module, an acquisition unit, an IGBT transient characteristic calculation unit and an output module; wherein:
the input module transmits external parameters of the IGBT to the acquisition unit; the input module comprises a driving module; the driving module adds a driving signal into external parameters of the IGBT; the input module processes the driving signal and the emitter current to obtain time information and current value information when the driving signal changes; the input module comprises a driving signal input end, a bus voltage input end, a temperature signal input end and an input current signal input end; the acquisition unit transmits the acquired IGBT external parameters to the IGBT transient characteristic calculation unit; the IGBT transient characteristic calculation unit simulates the collector-emitter voltage, the collector-emitter current and the grid voltage of the IGBT in time according to the acquired external parameters of the IGBT and by combining the expressions of the main internal parameters of the physical model of the IGBT, the collector-emitter voltage, the collector-emitter current and the grid voltage under the switching-on transient state and the expressions of the collector-emitter voltage, the collector-emitter current and the grid voltage under the switching-off transient state, and synchronously transmits the simulation results of the collector-emitter voltage, the collector-emitter current and the grid voltage of the IGBT to the output module; and the output module outputs simulation results of the collector-emitter voltage, the collector-emitter current and the grid voltage of the IGBT.
The IGBT simulation model also comprises a clock unit; the clock unit provides synchronous clock signals for the acquisition unit and the IGBT transient characteristic calculation unit at the same time.
And S400, combining with the practical application requirements of scientific research personnel for carrying out complex circuit simulation, if only voltage spikes are concerned, the output part of the simulation model can be further simplified, and the internal calculation method is unchanged. Simplifying the 5 phases of the IGBT turn-off transient state into 2 phases, specifically comprising: the on-state voltage rises to the voltage spike section and the voltage spike falls to the bus voltage section, which is set to reach the voltage spike at the middle of the turn-off transient for the convenience of simulation. (ii) a The initial time of the on-state voltage rising to the voltage peak section is t 6 The end time is t f1 (ii) a The starting time when the voltage peak drops to the bus voltage section is t f1 The end time is t 10 ；t f1 Calculated according to equation (30):
t f1 ＝(t 6 +t 10 )/2 (30)
the schematic diagram of the further simplified model turn-off transient waveform is shown in fig. 9, where t f0 ＝t 6 For the off signal start time, t f2 ＝t 10 Time for voltage spike to just drop to bus voltage, t f1 ＝(t f0 +t f2 )/2。
After further simplification, simulation can be carried out by using a Simulink automatic step size mode or a larger step size. The Variable-step mode changes the step size in the simulation process, adopts a smaller step size when the state of the model changes rapidly, and adopts a larger step size when the state of the model changes slowly so as to reduce unnecessary calculation. Although calculating step size increases a certain amount of time for calculation, it reduces the total number of steps, which in general reduces the simulation time required for models with rapidly changing or piecewise continuous states. In the Variable-step mode, in the embodiment shown in the figure, the time of one fundamental wave period of 0.02s is simulated, the time of an ideal model is 0.82s, and the time of the simulation of the model is 11s, so that a better compromise is obtained between the simulation efficiency and the simulation precision.
In the embodiment shown in fig. 7, the experimental waveform, the present model, the Simulink ideal model result pair are shown in fig. 8. It can be seen that the ideal model does not accurately characterize the electrical characteristics of the switching transients, and the model established herein enables simulation analysis of the electrical characteristics of devices in complex circuits. Partial simulation results of the voltage and current of the model built herein are shown in table 1, and a voltage simulation result graph of one fundamental wave period when VDC ═ 400V of the three-phase inverter circuit of fig. 10a, a voltage experimental waveform graph of one fundamental wave period when VDC ═ 400V of the three-phase inverter circuit of fig. 10a, a current simulation result graph of one fundamental wave period of the three-phase inverter circuit of fig. 11a, and a current experimental waveform graph of one fundamental wave period of the three-phase inverter circuit of fig. 11a may be plotted according to table 1:
TABLE 1 partial data table of voltage and current simulation results
Figure RE-GDA0002657884650000221
Figure RE-GDA0002657884650000231
Figure RE-GDA0002657884650000241
Figure RE-GDA0002657884650000251
Compared with the ideal model, in fig. 9 and 10, the relative errors of the voltage and current spikes are within 10%, and basically reach the acceptable range of engineering application.
In the foregoing detailed description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the subject matter require more features than are expressly recited in each claim. Rather, as the following claims reflect, invention lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate preferred embodiment of the invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. To those skilled in the art; various modifications to these embodiments will be readily apparent, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
What has been described above includes examples of one or more embodiments. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the aforementioned embodiments, but one of ordinary skill in the art may recognize that many further combinations and permutations of various embodiments are possible. Accordingly, the embodiments described herein are intended to embrace all such alterations, modifications and variations that fall within the scope of the appended claims. Furthermore, to the extent that the term "includes" is used in either the detailed description or the claims, such term is intended to be inclusive in a manner similar to the term "comprising" as "comprising" is interpreted when employed as a transitional word in a claim. Furthermore, any use of the term "or" in the specification of the claims is intended to mean a "non-exclusive or".
The above-mentioned embodiments, objects, technical solutions and advantages of the present invention are further described in detail, it should be understood that the above-mentioned embodiments are only examples of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (6)

  1. The method for establishing the IGBT switch transient model is suitable for complex circuit simulation and is characterized by comprising the following steps: comprises the following steps:
    s100, dividing the IGBT turn-on transient state into 5 stages, specifically comprising: a switching-on delay stage, a current rising stage, a voltage steep-falling stage, a voltage tailing stage and a grid voltage rising stage;
    establishing a switching-on relation set under a switching-on transient state according to main internal parameters of the IGBT physical model; the set of turn-on relationships includes a collector-emitter voltage, a collector-emitter current, and a gate voltage, wherein: the grid voltage controls the turn-on of the IGBT; the voltage of the collector and emitter is the voltage at two ends of the collector and emitter in the turn-on process of the IGBT; the current of the collector and the emitter is the current flowing through the collector and the emitter in the turn-on process of the IGBT;
    dividing the IGBT turn-off transient into 5 phases, specifically including: a turn-off delay stage, a voltage slow-rising stage, a voltage steep-rising stage, a current steep-falling stage and a current tailing stage;
    establishing a turn-off relation set of collector-emitter voltage, collector-emitter current and grid voltage under a turn-off transient state according to main internal parameters of an IGBT physical model; the set of turn-off relationships includes the collector-emitter voltage, collector-emitter current, and gate voltage, wherein: the gate voltage controls the turn-off of the IGBT; the voltage of the collector and emitter is the voltage at two ends of the collector and emitter in the turn-off process of the IGBT; the current of the collector and the emitter is the current flowing through the collector and the emitter in the turn-off process of the IGBT;
    s300, collecting and outputting external parameters of the IGBT; the external parameters of the IGBT comprise a driving signal, bus voltage, temperature and input current, wherein: the input current is measured by an ammeter in a branch associated with the IGBT; the temperature is IGBT junction temperature and is preset manually or coupled with a heat transfer network; the bus voltage is manually preset according to the setting parameters of the power supply;
    establishing expressions of collector-emitter voltage, collector-emitter current and grid voltage under the switching relation set; establishing expressions of collector-emitter voltage, collector-emitter current and gate voltage under the switching-off relation set;
    establishing an IGBT simulation model according to main internal parameters of an IGBT physical model, expressions of collector-emitter voltage, collector-emitter current and grid voltage under the switching-on relation set and expressions of collector-emitter voltage, collector-emitter current and grid voltage under the switching-off relation set; the main internal parameters of the IGBT physical model comprise a gate-drain electrode overlapping area, a gate-emitter electrode capacitance, a gate oxide layer capacitance, an IGBT base region doping concentration, an IGBT transconductance, an IGBT base region electron mobility and an IGBT base region hole mobility; the IGBT simulation model comprises an input module, an acquisition unit, an IGBT transient characteristic calculation unit and an output module; wherein:
    the input module transmits external parameters of the IGBT to the acquisition unit; the input module comprises a driving module; the driving module adds the driving signal to the external parameters of the IGBT; the input module processes the driving signal and the emitter current to obtain time information and current value information when the driving signal changes; the input module comprises a driving signal input end, a bus voltage input end, a temperature signal input end and an input current signal input end; the acquisition unit transmits the acquired IGBT external parameters to the IGBT transient characteristic calculation unit; the IGBT transient characteristic calculation unit simulates the collector-emitter voltage, the collector-emitter current and the grid voltage of the IGBT in time according to the acquired external parameters of the IGBT and by combining the expressions of main internal parameters of the physical model of the IGBT, the collector-emitter voltage, the collector-emitter current and the grid voltage under the switching-on transient state and the expressions of the collector-emitter voltage, the collector-emitter current and the grid voltage under the switching-off transient state, and synchronously transmits the simulation results of the collector-emitter voltage, the collector-emitter current and the grid voltage of the IGBT to the output module; and the output module outputs simulation results of the collector-emitter voltage, the collector-emitter current and the grid voltage of the IGBT.
  2. 2. The method for establishing the IGBT switch transient model according to claim 1, characterized in that: in the turn-on delay phase, the expression of collector-emitter current and collector-emitter voltage is:
    I CE ＝0；V CE ＝V DC
    wherein, I CE Is the collector-emitter current; v CE Is the collector-emitter voltage; v DC Is the bus voltage;
    in the turn-on delay stage, the expression of the gate voltage is:
    Figure FDA0002498971610000031
    wherein, V GE Is the gate voltage; v GGf The negative voltage value representing the grid voltage is provided by external parameters of the IGBT; v GGn A positive voltage value representing the gate voltage, provided by an IGBT external parameter; t represents the current time; t is t 0 The starting time of the turn-on delay stage is represented and is calculated from the moment when the IGBT switch is turned on; r is g The driving resistance is represented and is manually preset during circuit design or obtained by a driver board user manual; c GE Represents the gate capacitance, obtained from the device handbook;
    in the current rise phase, the expression of the collector-emitter current is:
    I CE ＝I n +I P
    wherein, I p For hole current, it is calculated as follows:
    Figure FDA0002498971610000032
    wherein the content of the first and second substances,
    Figure FDA0002498971610000033
    τ Hb 、τ Ab 、τ r five intermediate quantities related to the internal parameters of the device are obtained by deducing an IGBT physical model; the derivation of the IGBT physical model comprises the doping concentration of a base region, the width of the base region, the service life of excess carriers of the base region, the doping concentration of a buffer layer, the width of the buffer layer, the service life of excess carriers of the buffer layer, the carrier mobility, the area of a chip and the voltage of the IGBT device; b L Represents a value of electron-to-hole mobility ratio, which is obtained from the ratio of electron-to-hole mobility; q T The total charge quantity inside the IGBT is represented and obtained by a semiconductor charge control equation;
    I n for electron current, it is calculated as follows:
    Figure FDA0002498971610000034
    wherein, I MOS The current flowing through the MOS channel is represented and obtained by a MOSFET current characteristic expression; c DSJ Representing the capacitance between a drain electrode and a source electrode in the MOS structure, and obtaining the capacitance from physical model parameters; v ds Representing the drain-source voltage in the MOS structure, this phase V ds ＝V CE ；
    The expression for the miller plateau voltage is:
    Figure FDA0002498971610000041
    wherein, V ml Is the Miller plateau voltage; v T As threshold voltage, obtained from the device handbook; k P Is transconductance, obtained from the device handbook; i is Lm The current value at the ending moment of the current rising stage is obtained by processing of the signal acquisition unit; beta is the channel current coefficient and is calculated according to the following formula:
    β＝I mos /I CE
    the semiconductor physical formula is calculated according to the following formula
    Figure FDA0002498971610000042
    In the formula, A GD Is the gate-drain overlap area; epsilon si Is the dielectric constant of silicon; q is an electron charge amount constant; n is a radical of L N-base region doping concentration;
    miller capacitance C GD (t) is:
    Figure FDA0002498971610000043
    in the voltage steep drop phase and the voltage tail phase, the voltage is in the Miller plateau phase V ml And (3) if the voltage drop slope in each stage is constant, calculating according to the following formula:
    Figure FDA0002498971610000044
    C GDa for equivalent capacitance, it is calculated as follows:
    Figure FDA0002498971610000045
    wherein, V Cn ＝V CE2 /3；C OXD A gate oxide layer capacitor, obtained from a device handbook; wherein V GD ＝V ml -V T Is the demarcation point of the change of the Miller capacitance; v CE2 Is t 2 The gate voltage at that time is calculated by the following equation;
    Figure FDA0002498971610000046
    the expression for the collector-emitter voltage is:
    Figure FDA0002498971610000051
    wherein, t 2 The end time of the current rising phase and the start time of the voltage steep-falling phase are calculated according to the following formula:
    Figure FDA0002498971610000052
    t 3 the end time of the voltage steep-drop stage is also the start time of the voltage tailing stage; t is t 4 The end time of the voltage tailing stage is also the starting time of the grid voltage rising stage; can be calculated from the following formula:
    Figure FDA0002498971610000053
    Figure FDA0002498971610000054
    Figure FDA0002498971610000055
    wherein, V on For on-state voltage drop, available from device handbook, k 22 、k 23 、k 34 Is t 2 ～t’ 2 、t’ 2 ～t 3 、t 3 ～t 4 The slope of the voltage over the time period.
  3. 3. The method for establishing the IGBT switch transient model according to claim 2, characterized in that: in the turn-off delay phase, the expression of the gate voltage is:
    Figure FDA0002498971610000056
    wherein, t 6 Starting from the moment the IGBT switch is turned off for the start of the turn-off delay phaseCalculating;
    similar to the opening phase, wherein C GDa For equivalent capacitance, it is calculated as follows:
    Figure FDA0002498971610000061
    in the formula (I), the compound is shown in the specification,
    Figure FDA0002498971610000062
    in the voltage ramp-up stage and the voltage ramp-up stage, the expression of the collector-emitter voltage is as follows:
    Figure FDA0002498971610000063
    in the formula, t 7 The end time of the turn-off delay stage is also the start time of the voltage ramp-up stage; t is t 8 The end time of the voltage gradual rising phase is also the start time of the voltage steep rising phase; t is t 9 The end time of the voltage steep-rise stage and the start time of the current steep-fall stage are also provided; t' 8 For the voltage to reach V cf The time point of (a); similar to the turn-on phase, the time point of this phase can be calculated by the following formula:
    Figure FDA0002498971610000064
    Figure FDA0002498971610000065
    Figure FDA0002498971610000066
    wherein k is 78 、k 88 、k 89 Is t 7 ～t 8 、t 8 ～t’ 8 、t 8 ～t 9 A slope of the voltage over the time period;
    in the current steep descending stage, at t' 9 The moment the collector-emitter voltage reaches a maximum value; t' 9 Is t 9 And t 10 Intermediate value of (1), t' 9 ＝(t 9 +t 10 ) /2, wherein t 10 The end time of the current steep-falling stage and the start time of the current tailing stage are calculated according to the following formula:
    Figure FDA0002498971610000067
    the maximum value of the collector-emitter voltage is calculated as follows:
    Figure FDA0002498971610000071
    wherein, V CEm Is the maximum value of the collector-emitter voltage; l is s The line stray inductance is obtained by external circuit measurement; r is s The stray resistance of the line is measured by an external circuit; i is Lm The value of the collector-emitter current collected at this stage; i is tail For the initial value of the tail current, it is calculated as follows:
    I tail ＝I p ＝I Lm -I n ＝(1-β)I Lm
    k 910 for the current ramp-down slope, it is calculated as follows:
    Figure FDA0002498971610000072
    in the current tail phase, the collector-emitter current is calculated as follows:
    Figure FDA0002498971610000073
    wherein, I Keff And τ eff Is the diffusion coefficient with holes D P Width W of Buffer layer H The doping concentration N of the Buffer layer H And Buffer layer carrier lifetime τ H The two constants of the correlation can be obtained by experiment or data manual information calculation.
  4. 4. The method for establishing the IGBT switch transient model according to claim 3, characterized in that: the IGBT simulation model is built in a Simulink tool box in MATLAB software by adopting an S-Function mode.
  5. 5. The method for establishing the IGBT switch transient model according to claim 4, characterized in that: the IGBT simulation model further comprises a clock unit; and the clock unit simultaneously provides synchronous clock signals for the acquisition unit and the IGBT transient characteristic calculation unit.
  6. 6. The method for establishing the IGBT switch transient model according to claim 5, characterized in that: comprises the following steps:
    s400, simplifying the 5 stages of the IGBT turn-off transient state into 2 stages, and specifically comprising the following steps: the on-state voltage rises to a voltage spike section and the voltage spike falls to a bus voltage section; the starting time of the on-state voltage rising to the voltage spike section is t 6 The end time is t f1 (ii) a The end time when the voltage spike drops to the bus voltage section is t 10 The starting time is calculated as follows:
    t f1 ＝(t 6 +t 10 )/2
    wherein, t f1 The starting moment when the voltage spike drops to the bus voltage segment.
CN202010426807.7A 2020-05-19 2020-05-19 Method for establishing IGBT switch transient model Active CN111767634B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010426807.7A CN111767634B (en) 2020-05-19 2020-05-19 Method for establishing IGBT switch transient model

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010426807.7A CN111767634B (en) 2020-05-19 2020-05-19 Method for establishing IGBT switch transient model

Publications (2)

Publication Number Publication Date
CN111767634A CN111767634A (en) 2020-10-13
CN111767634B true CN111767634B (en) 2022-09-27

Family

ID=72719360

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010426807.7A Active CN111767634B (en) 2020-05-19 2020-05-19 Method for establishing IGBT switch transient model

Country Status (1)

Country Link
CN (1) CN111767634B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112433115B (en) * 2020-11-12 2022-07-08 中南大学 Aging injector, power device and traction converter aging modeling method
CN112630544B (en) * 2020-12-22 2022-12-09 西安交通大学 High-voltage SiC MOSFET drain-source interelectrode nonlinear capacitance measurement and modeling method
CN115951192B (en) * 2023-03-09 2023-06-23 长沙丹芬瑞电气技术有限公司 Junction temperature detection device, method and medium of power device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102368274A (en) * 2011-09-07 2012-03-07 中国人民解放军海军工程大学 Electro-thermal simulation method for FS (Field Stop) type IGBT (Insulated Gate Bipolar Transistor) transient temperature characteristic
JP2012150574A (en) * 2011-01-17 2012-08-09 Fuji Electric Co Ltd Simulation cooperation method and simulation device
CN105631083A (en) * 2015-03-20 2016-06-01 华北电力大学 Method for establishing high-voltage IGBT module switch transient model suitable for circuit simulation
CN106991221A (en) * 2017-03-24 2017-07-28 清华大学 A kind of sectional broken line model based on IGBT device transient physical process
CN109344419A (en) * 2018-08-06 2019-02-15 清华大学 A kind of transient state piecewise analysis model for IGBT and PIN diode convertor unit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012150574A (en) * 2011-01-17 2012-08-09 Fuji Electric Co Ltd Simulation cooperation method and simulation device
CN102368274A (en) * 2011-09-07 2012-03-07 中国人民解放军海军工程大学 Electro-thermal simulation method for FS (Field Stop) type IGBT (Insulated Gate Bipolar Transistor) transient temperature characteristic
CN105631083A (en) * 2015-03-20 2016-06-01 华北电力大学 Method for establishing high-voltage IGBT module switch transient model suitable for circuit simulation
CN106991221A (en) * 2017-03-24 2017-07-28 清华大学 A kind of sectional broken line model based on IGBT device transient physical process
CN109344419A (en) * 2018-08-06 2019-02-15 清华大学 A kind of transient state piecewise analysis model for IGBT and PIN diode convertor unit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
适用于复杂电路分析的IGBT模型;邓夷等;《中国电机工程学报》;20100325(第09期);全文 *

Also Published As

Publication number Publication date
CN111767634A (en) 2020-10-13

Similar Documents

Publication Publication Date Title
CN111767634B (en) Method for establishing IGBT switch transient model
Takamiya et al. Power electronics 2.0: IoT-connected and Al-controlled power electronics operating optimally for each user
Awwad et al. Operation of planar and trench SiC MOSFETs in a 10kW DC/DC-converter analyzing the impact of the body diode
Li et al. Comparison between 1.7 kV SiC SJT and MOSFET power modules
Li et al. Modelling GaN-HEMT dynamic on-state resistance in high frequency power converter
Mitova et al. Fully integrated gate drive supply around power switches
Rashid et al. An efficient electro-thermal compact model of SiC power MOSFETs including third quadrant behavior
Xu et al. A datasheet-based behavioral model of SiC MOSFET for power loss prediction in electromagnetic transient simulation
Ren et al. Gate drive investigations of IGBT modules with SiC-Schottky freewheeling diodes
Eial Awwad On the perspectives of SiC MOSFETs in high-frequency and high-power isolated DC/DC converters
Withanage et al. IGBT parameter extraction for the Hefner IGBT model
Zhuolin et al. A simple SiC power MOSFET model
Yu et al. Understanding the degradation of 1.2-kV planar-gate SiC MOSFETs under repetitive over-load current stress
Awwad et al. Investigation of 1.2 kV SiC MOSFETs for hard-and soft-switching converters
JP4332645B2 (en) Power conversion device design method and system, and design program
CN115496032A (en) Silicon carbide MOSFET switching process analysis method
Kang et al. Mechanisms of asymmetrical turn-on and turn-off and the origin of dynamic C GD hysteresis for hard-switching superjunction MOSFETs
Hao et al. Transient Analytical Model of High-Voltage and High-Power IGBT Device Based on Nondual Relationship for the Switching Process
Xue et al. A Temperature-Dependent $ dV_ {CE}/dt $ and $ dI_ {C}/dt $ Model for Field-Stop IGBT at Turn-on Transient
Ma et al. Research on switching characteristics of SiC MOSFET in pulsed power supply with analytical model
Yang et al. Analysis of Gate-Source Voltage Spike Generated by Miller Capacitance and Common Source Inductance
Xing et al. 3.3-kV SiC MOSFET performance and short-circuit capability
Yang et al. A model parameter optimization method of SiC power MOSFETs
Tulbure et al. Experimental comparation of switching with IGBT and MOSFET
Hirose et al. Development of the HiSIM-IGBT model for EV/HV electric circuit simulation

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant