CN111756221A - Method and circuit for inhibiting generation of over-high voltage during starting - Google Patents

Abstract

The invention provides a voltage suppression circuit for suppressing generation of an excessive voltage when a power supply unit is started and a realization method thereof. The voltage suppression circuit is connected between the grid and the source of the power conversion MOS tube in parallel; during the generation period of the initial pulse driven by the pulse width modulation voltage, the voltage suppression circuit slows down the rising speed of the voltage amplitude between the grid electrode and the source electrode of the power conversion MOS tube; after the initial pulse driven by the pulse width modulation voltage, the voltage suppression circuit does not influence the switching-on speed of the power supply conversion MOS tube. The voltage-suppressing circuit is easy to realize, does not need software control, is simple in circuit design, does not need to change the original design greatly, and is low in cost and high in efficiency.

Description

Method and circuit for inhibiting generation of over-high voltage during starting

Technical Field

The invention relates to the technical field of electronics, in particular to a circuit for inhibiting generation of an over-high voltage during starting and an implementation method thereof.

Background

In the current power supply unit or power module of network communication equipment or other electronic equipment, at the initial stage of power-on start, because the buffer circuit in the power supply unit has not entered into the normal working state yet, an excessive overvoltage is generated on some devices in the power supply unit or power module at the initial stage of power-on start, which can greatly increase the failure risk of the power supply unit of the communication equipment; and after power-up is initiated, the over-voltage condition disappears. For this case, the related components with higher rated voltage can be selected to satisfy the working environment during start-up and normal operation, but this method will increase the cost and increase the circuit area. Therefore, it is a subject of considerable research to improve the current design of circuits and to efficiently and inexpensively suppress the generation of an excessive high voltage when a power supply unit is activated.

Disclosure of Invention

The invention aims to provide a voltage suppression circuit for suppressing the generation of an excessive voltage when a power supply unit is started and an implementation method thereof. The circuit is easy to realize, does not need software control, can inhibit the generation of over-high voltage when the power supply unit is powered on or reset to start, and does not influence the normal work of the power supply unit after the power supply unit is powered on or reset to start, thereby providing a high-efficiency and low-cost power supply for a communication equipment system.

According to an embodiment of the first aspect of the present invention, there is provided a voltage suppressing circuit for suppressing generation of an excessive voltage when a power supply unit is started, wherein the power supply unit includes a pulse width modulation voltage drive and a power conversion MOS transistor, a positive electrode of the pulse width modulation voltage drive is connected to a gate of the power conversion MOS transistor, and a negative electrode of the pulse width modulation voltage drive is connected to a source of the power conversion MOS transistor; wherein the content of the first and second substances,

the voltage suppression circuit is connected between the grid and the source of the power conversion MOS tube in parallel; during the generation period of the initial pulse driven by the pulse width modulation voltage, the voltage suppression circuit slows down the rising speed of the voltage amplitude between the grid electrode and the source electrode of the power conversion MOS tube; after the initial pulse driven by the pulse width modulation voltage, the voltage suppression circuit does not influence the switching-on speed of the power conversion MOS tube.

Specifically, the voltage suppressing circuit further includes: the voltage suppressing circuit does not affect the process of restarting the power supply unit.

Specifically, the voltage suppressing circuit includes: a diode, a capacitor and a resistor; the capacitor is connected with the resistor in parallel; the anode of the diode is connected with the anode driven by the pulse width modulation voltage; one end of the parallel resistor capacitor is connected with the cathode of the diode, and the other end of the parallel resistor capacitor is connected with the source electrode of the power supply conversion MOS tube.

Specifically, the capacitance and the resistance satisfy:

Kr*Kc>m*Ts；

wherein Kr is the resistance value of the resistor, Kc is the capacitance value of the capacitor, Ts is the period of the pulse voltage signal generated by the pwm voltage drive, and m is 5.

Specifically, the capacitance and the resistance satisfy:

Kr*Kc<Tp/n；

wherein Tp is the shortest time interval required for restarting the power supply unit, and n is 3.

According to an embodiment of the second aspect of the present invention, there is provided a method for implementing a voltage suppressing circuit for suppressing generation of an excessive voltage at the time of starting a power supply unit, wherein the power supply unit includes a pulse width modulation voltage drive and a power conversion MOS transistor, a positive electrode of the pulse width modulation voltage drive is connected to a gate of the power conversion MOS transistor, and a negative electrode of the pulse width modulation voltage drive is connected to a source of the power conversion MOS transistor; wherein the method comprises the following steps:

s1: the voltage suppression circuit is connected between the grid electrode and the source electrode of the power conversion MOS tube in parallel;

s2: during the generation period of the initial pulse driven by the pulse width modulation voltage, the voltage suppression circuit is enabled to slow down the rising speed of the voltage amplitude between the grid electrode and the source electrode of the power conversion MOS tube; after the initial pulse driven by the pulse width modulation voltage, the voltage suppression circuit does not influence the switching speed of the power conversion MOS tube.

Specifically, the method further comprises:

s3: the suppressing circuit is made not to affect the process of restarting the power supply unit.

Specifically, the step S2 includes:

s21: arranging a diode, a capacitor and a resistor;

s22: connecting the capacitor and the resistor in parallel; connecting the anode of the diode with the anode of the pulse width modulation voltage drive; and connecting one end of the parallel resistor capacitor with the cathode of the diode, and connecting the other end of the parallel resistor capacitor with the source electrode of the power supply conversion MOS tube.

Specifically, the capacitance and the resistance satisfy:

Kr*Kc>m*Ts；

wherein Kr is the resistance value of the resistor, Kc is the capacitance value of the capacitor, Ts is the period of the pulse voltage signal generated by the pwm voltage drive, and m is 5.

Specifically, the capacitance and the resistance satisfy:

Kr*Kc<Tp/n；

wherein Tp is the shortest time interval required for restarting the power supply unit, and n is 3.

According to an embodiment of the third aspect of the present invention, there is provided an electronic apparatus including the voltage suppressing circuit as described above.

Compared with the prior art, the invention has the following advantages: the circuit design is easy to realize, software control is not needed, the generation of the over-high voltage can be inhibited when the power supply unit is powered on or reset to start, the normal work of the power supply unit after the power supply unit is powered on or reset to start cannot be influenced, the circuit design is simple, the original design does not need to be changed greatly, the cost is low, and the efficiency is high.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:

fig. 1 is a schematic diagram of a suppressing circuit for suppressing generation of an excessive voltage at the time of starting a power supply unit according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a suppressing circuit for suppressing generation of an excessive voltage at the time of starting up a power supply unit according to a preferred embodiment of the present invention;

FIG. 3 is a diagram showing simulation results of an application of a suppressing circuit for suppressing generation of an excessive voltage at the time of startup of a power supply unit according to a preferred embodiment of the present invention;

FIG. 4 is a flowchart illustrating a method of implementing a suppressing circuit for suppressing generation of an excessive voltage at the time of starting up a power supply unit according to an embodiment of the present invention;

fig. 5 is a flowchart illustrating a method of implementing a suppressing circuit for suppressing generation of an excessive voltage at the time of startup of a power supply unit according to a preferred embodiment of the present invention.

The same or similar reference numbers in the drawings identify the same or similar elements.

Detailed Description

Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel, concurrently, or simultaneously. In addition, the order of the operations may be re-arranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, sub-circuits, and so on.

The methods discussed below, some of which are illustrated by flow diagrams, may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segments to perform the necessary tasks may be stored in a machine or computer readable medium such as a storage medium. The processor(s) may perform the necessary tasks.

Specific structural and functional details disclosed herein are merely representative and are provided for purposes of describing example embodiments of the present invention. The present invention may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be termed a second element, and, similarly, a second element may be termed a first element, without departing from the scope of example embodiments. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements (e.g., "between" versus "directly between", "adjacent" versus "directly adjacent to", etc.) should be interpreted in a similar manner.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be noted that, in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may, in fact, be executed substantially concurrently, or the figures may sometimes be executed in the reverse order, depending upon the functionality/acts involved.

The present invention is described in further detail below with reference to the attached drawing figures.

Fig. 1 is a schematic diagram of a suppressing circuit for suppressing generation of an excessive voltage at the time of starting a power supply unit according to an embodiment of the present invention. The voltage suppressing circuit according to the embodiment of the present invention can be used in a power supply unit or a power supply circuit of an electronic device. The electronic device includes, but is not limited to, a terminal device, a network device, a communication device, a medical device, a measurement instrument, and the like having a power supply unit. Terminal devices include, but are not limited to, smart phones, tablets, PDAs, PCs, and the like. Network devices include, but are not limited to, a single network server, a server group of multiple network servers, or a Cloud of numerous computers or network servers based on Cloud Computing (Cloud Computing), which is one type of distributed Computing, a super virtual computer consisting of a collection of loosely coupled computers. Communication devices include, but are not limited to, routers, switches, base stations, core networks, wireless local area network controllers, and the like. It should be noted that the electronic devices, including the terminal device, the network device, the communication device, etc., are only examples, and other existing or future electronic devices with a suppression circuit for suppressing the generation of an excessive voltage when the power supply unit is started may be applied to the present invention, and are included in the scope of the present invention and are also included by reference.

In the voltage suppression circuit for suppressing the generation of the over-high voltage when the power supply unit is started, the power supply unit comprises a pulse width modulation voltage drive and a power supply conversion MOS tube, wherein the positive electrode of the pulse width modulation voltage drive is connected with the grid electrode of the power supply conversion MOS tube, and the negative electrode of the pulse width modulation voltage drive is connected with the source electrode of the power supply conversion MOS tube; wherein the content of the first and second substances,

the voltage suppression circuit is connected between the grid and the source of the power conversion MOS tube in parallel; during the generation period of the initial pulse driven by the pulse width modulation voltage, the voltage suppression circuit slows down the rising speed of the voltage amplitude between the grid electrode and the source electrode of the power conversion MOS tube; after the initial pulse driven by the pulse width modulation voltage, the voltage suppression circuit does not influence the switching-on speed of the power conversion MOS tube.

As shown in fig. 1, the power supply unit according to the embodiment of the present invention includes a Pulse Width Modulation voltage driver VP that supplies a Pulse Width Modulation (PWM) periodic Pulse voltage signal. The power supply unit of the embodiment of the invention further includes a power conversion MOS transistor M1, the positive electrode of the pulse width modulation voltage driver VP is connected to the gate of the power conversion MOS transistor M1, and the negative electrode of the pulse width modulation voltage driver VP is connected to the source of the power conversion MOS transistor M1. The power conversion MOS transistor M1 is turned on and off according to the signal of the pulse width modulation voltage driving VP, and completes the conversion and processing of voltage and current together with other circuits of the power supply unit, so as to provide the required voltage or current for the subsequent stage of the power supply unit. The other part of the circuit of the power supply unit refers to the circuit excluding the voltage suppression circuit except the pulse width modulation voltage driving VP and the power conversion MOS transistor M1, and includes the conversion, rectification, filtering, control circuit and the like. When the power-on start or reset start of the power supply unit, the buffer circuit in the power supply unit does not enter a normal operating state, an excessive voltage is generated on some devices in the power supply unit, such as a MOS transistor, and the excessive voltage exceeds the range of the rated service voltage of the device, so that the device operates excessively. Too high a voltage may exceed the voltage range required by the circuit design, so that the relevant module or circuit may not work properly.

The voltage suppression circuit of the embodiment of the invention is connected in parallel between the grid and the source of the power conversion MOS transistor M1. The voltage suppression circuit is connected in parallel between the gate and the source of the power conversion MOS transistor M1, and therefore can affect the voltage between the gate and the source of the power conversion MOS transistor M1. During the initial pulse generation period of the pulse width modulation voltage drive VP, the voltage suppression circuit slows down the voltage rise between the gate and the source of the power conversion MOS transistor M1; after the start pulse of the pulse width modulation voltage drive VP, the voltage suppression circuit does not affect the speed of the rise of the turn-on voltage between the gate and the source of the power conversion MOS transistor M1, i.e., does not affect the turn-on speed of the MOS transistor. The time period represented by the generation period of the start pulse of the pulse width modulation voltage drive is the time period of the effective pulse width of the first pulse period signal generated by the pulse width modulation voltage drive VP after the power-on initial or reset starting of the power supply providing unit; the period of time indicated after the start pulse of the pwm voltage drive refers to the second pulse period signal output by the pwm voltage drive VP and the period of time thereafter. At the beginning of power-on or reset, during the period of effective pulse width of the first pulse period signal generated by driving the VP by the pulse width modulation voltage, the voltage suppression circuit processes the first pulse signal output by the VP to slow down the turn-on speed of the power conversion MOS tube M1, so that the voltage and current conversion speed of the conversion circuit is slowed down, and the influence of parasitic parameters is reduced, thus the buffer circuit in the power conversion unit can effectively play a role, and the generation of excessive high voltage on some devices or nodes in the power conversion unit is suppressed. After the power-on or reset is started, in the second pulse period signal generated by the pulse width modulation voltage drive VP and the time after the second pulse period signal, the voltage suppression circuit for suppressing the generation of the over-high voltage does not work any more, the effective influence on the turn-on speed of the power conversion MOS tube M1 is not generated any more, and the operation of other circuits of the power conversion unit is not influenced. The suppressing circuit of fig. 1 that suppresses the generation of the excessive voltage may be implemented in various ways. The signal of the pwm voltage drive VP may be processed using a digital logic circuit, the start pulse signal generated by VP is detected, and the speed of the pulse amplitude variation of the pulse voltage signal output between the gate and the source of the power conversion MOS transistor M1 is controlled so that the turn-on speed of the power conversion MOS transistor M1 during the effective period of the start pulse becomes slow. The digital logic circuit simultaneously controls the circuit to stop working after the initial pulse of the VP, and the pulse voltage output by the VP is directly connected to the grid and the source of the power supply conversion MOS tube M1. The suppression circuit for suppressing the generation of the over-high voltage can also be realized by combining a detection circuit and a control circuit through software: when the detection circuit detects that the pulse width modulation voltage drives the generation of the initial pulse signal output by the VP, the software outputs a signal to the control circuit to control the change speed of the pulse amplitude of the pulse voltage output to the grid electrode and the source electrode of the power supply conversion MOS tube M1 to be slow or to control the pulse not to be output to the post-stage circuit; and the pulse period signal after the initial pulse is not processed and is directly transmitted to a post-stage circuit.

The voltage suppressing circuit for suppressing generation of an excessive voltage at the time of startup of the power supply unit in one embodiment of the present invention further includes: the process of restarting the power supply unit is not affected. The power supply unit can be restarted after reset or power-off, at the moment, the electric quantity stored on the capacitor and other devices in the voltage-suppressing circuit needs to be discharged before the next startup, and all the devices such as the state machine, the comparator and the like need to be restored to the initial state, so that the restarting process of the power supply unit is not influenced.

Fig. 2 is a schematic diagram of a suppressing circuit for suppressing generation of an excessive voltage at the time of starting up a power supply unit according to a preferred embodiment of the present invention. As shown in fig. 2, the suppressing circuit of the preferred embodiment of the present invention includes a diode D, a capacitor C and a resistor R. The capacitor C is connected with the resistor R in parallel; the anode of the diode D is connected with the anode of the pulse width modulation voltage drive VP; one end of the parallel resistor-capacitor is connected with the cathode of the diode D, and the other end is connected with the source electrode of the power conversion MOS tube M1. It should be noted that a diode, a resistor and a capacitor in the embodiments of the present invention are only examples, and the singular form "a" and "an" used herein also includes plural forms, i.e., a plurality of diodes, a plurality of resistors and a plurality of capacitors, and combinations thereof, so that the final implementation effect is equivalent to that of a diode, a resistor and a capacitor in the embodiments of the present invention, if applicable, and is included in the protection scope of the present invention and is included by reference. The diode D in fig. 2 is used to conduct the current or voltage passing in the forward direction and block the current or voltage passing in the reverse direction. Therefore, the diode D can pass the output of the pwm voltage driver VP, and block the possible reverse output of the capacitor C and the resistor R from the voltage or current of the pwm voltage driver VP, so as to ensure the normal operation of the pwm voltage driver VP. The capacitor C is used to slow the rising speed of the start pulse of the pwm voltage drive VP. The capacitor C absorbs the electric energy of the pwm voltage drive VP to slow the pulse rising speed of the start pulse of the voltage output between the gate and the source of the power conversion MOS transistor M1, thereby slowing the on speed of the power conversion MOS transistor M1 during the generation of the start pulse of the pwm voltage drive VP. The resistor R is used for discharging the electric quantity on the capacitor C, so that the electric quantity on the capacitor C can be released at a set speed when no pulse width modulation voltage signal exists, and the voltage suppression circuit does not influence the normal work of the power supply unit and the reset restart or power-off restart process of the power supply unit.

In a preferred embodiment, the resistance R and the capacitance C of the suppressing circuit in fig. 2 for suppressing the generation of an excessive voltage satisfy: kr × Kc > m × Ts; where Kr is the resistance of the resistor R, Kc is the capacitance of the capacitor C, Ts is the period of the pulse voltage signal generated by the pulse width modulated voltage drive VP, and m is 5. When the resistor R and the capacitor C meet the condition that Kr × Kc >5Ts, the electric quantity on the capacitor C can be kept within the Ts time and cannot be rapidly discharged. The larger the value of Kr × Kc, the more the charge on the capacitor C remains during the time Ts. According to the simulation result, when Kr × Kc is more than 5Ts, enough electric quantity can be kept on the capacitor C; in practical environment, the use effect of the voltage suppression circuit is good.

In another preferred embodiment, the resistance R and the capacitance C of the suppressing circuit in fig. 2 for suppressing the generation of an excessive voltage satisfy: kr × Kc < Tp/n; wherein Tp is the shortest time interval required for restarting the power supply unit, and n is 3. Tp is the minimum time interval from power-down or reset to re-restart of the power supply unit. The value of Tp may be set to 0.1 seconds, typically taking into account the time interval at which a person presses a button, and the path and delay of the restart, etc. When the resistor R and the capacitor C meet the condition of Kr × Kc < Tp/n, the electric quantity on the capacitor C can be basically discharged within the time of Tp. The smaller the value of Kr × Kc, the faster the electric quantity on the capacitor C decreases in the time Tp. According to the simulation result, when Kr × Kc is less than Tp/3, most of electric quantity can be discharged by the capacitor C within the reset interval time, and the process of restarting next time is not influenced; in practical environment, the use effect of the voltage suppression circuit is good.

Fig. 3 is a diagram showing simulation results of an application of a suppressing circuit for suppressing generation of an excessive voltage at the time of startup of a power supply unit according to a preferred embodiment of the present invention. Fig. 3 includes two parts 3a and 3 b. Fig. 3a is a diagram showing simulation results of a voltage across a freewheel MOS transistor in a power supply unit not including the suppressing circuit of the present invention. Without the voltage suppression circuit, as shown in fig. 3a, the drain-source voltage on the freewheel MOS transistor would have an excessive voltage generated during the initial pulse period, but there is no excessive voltage problem after the second pulse period. Fig. 3b is a diagram showing simulation results of the voltage across the freewheel MOS transistor in the power supply unit including the voltage suppressing circuit, corresponding to fig. 3 a. The voltage suppressing circuit includes a diode, a capacitor and a resistor, and the connections and positions of the diode, the capacitor and the resistor in the power supply unit are as shown in the embodiment of fig. 2. Ts is the period of the pulse signal generated by the pulse width modulation voltage drive, which is 4us in the figure; tp is the minimum time interval for restart, which is 0.1 s. The voltage suppression circuit used in fig. 3b has a capacitance Kc of 1uF and a resistance Kr of 10 k. Therefore, Kc Kr 0.01s can satisfy both the conditions of Kc Kr >5 s 4 s 0.00002s and Kc Kr <0.1/3s 0.033 s. As can be seen from the figure, after the voltage suppression circuit is used, the rising edge of the gate-source voltage on the power conversion MOS transistor becomes gentle, the highest voltage of the drain-source voltage on the freewheel MOS transistor in the initial pulse period decreases from 80v to 63v, and the problem of the excessive high voltage disappears. Meanwhile, as Kc x Kr <0.1/3 s-0.033 s, when the power supply unit is restarted after being powered off for 0.1s, the power stored in the capacitor in the voltage-suppressing circuit can be discharged completely, and the restarting process of the power supply unit is not affected.

Fig. 4 is a flowchart illustrating a method of implementing a suppressing circuit for suppressing generation of an excessive voltage at the time of starting up a power supply unit according to an embodiment of the present invention. The method according to an embodiment of the present invention may be used in a power supply unit or a power supply circuit of an electronic device. The electronic device includes, but is not limited to, a terminal device, a network device, a communication device, a medical device, a measurement instrument, and the like having a power supply unit. Terminal devices include, but are not limited to, smart phones, tablets, PDAs, PCs, and the like. Network devices include, but are not limited to, a single network server, a server group of multiple network servers, or a Cloud of numerous computers or network servers based on Cloud Computing (Cloud Computing), which is one type of distributed Computing, a super virtual computer consisting of a collection of loosely coupled computers. Communication devices include, but are not limited to, routers, switches, base stations, core networks, wireless local area network controllers, and the like. It should be noted that the electronic devices, including the terminal device, the network device, the communication device, etc., are only examples, and other existing or future electronic devices with a method for implementing a suppression circuit for suppressing the generation of an excessive voltage when the power supply unit is started may be applied to the present invention, and are included in the scope of the present invention and are also included by reference.

In the method for implementing a voltage suppression circuit for suppressing generation of an excessive voltage when a power supply unit is started, the power supply unit includes a pulse width modulation voltage drive and a power conversion MOS transistor, an anode of the pulse width modulation voltage drive is connected to a gate of the power conversion MOS transistor, and a cathode of the pulse width modulation voltage drive is connected to a source of the power conversion MOS transistor. As shown in fig. 4, the method includes step S1 and step S2. In step S1, the voltage suppressing circuit is connected in parallel between the gate and the source of the power conversion MOS transistor. In step S2, during the generation of the start pulse of the pwm voltage driving, the suppressing circuit is made to slow down the rising speed of the voltage amplitude between the gate and the source of the power conversion MOS transistor; after the initial pulse driven by the pulse width modulation voltage, the voltage suppression circuit does not influence the switching speed of the power conversion MOS tube.

The power supply unit of the embodiment of the present invention includes a Pulse Width Modulation voltage drive VP that supplies a Pulse Width Modulation (PWM) periodic Pulse voltage signal. The power supply unit of the embodiment of the invention further includes a power conversion MOS transistor M1, the positive electrode of the pulse width modulation voltage driver VP is connected to the gate of the power conversion MOS transistor M1, and the negative electrode of the pulse width modulation voltage driver VP is connected to the source of the power conversion MOS transistor M1. The power conversion MOS transistor M1 is turned on and off according to the signal of the pulse width modulation voltage driving VP, and completes the conversion and processing of voltage and current together with other circuits of the power supply unit, so as to provide the required voltage or current for the subsequent stage of the power supply unit. The other part of the circuit of the power supply unit refers to the circuit excluding the voltage suppression circuit except the pulse width modulation voltage driving VP and the power conversion MOS transistor M1, and includes the conversion, rectification, filtering, control circuit and the like. When the power-on start or reset start of the power supply unit, the buffer circuit in the power supply unit does not enter a normal operating state, an excessive voltage is generated on some devices in the power supply unit, such as a MOS transistor, and the excessive voltage exceeds the range of the rated service voltage of the device, so that the device operates excessively. Too high a voltage may exceed the voltage range required by the circuit design, so that the relevant module or circuit may not work properly.

In step S1, a voltage suppressing circuit is connected in parallel between the gate and the source of the power conversion MOS transistor M1. The voltage between the gate and the source of the power conversion MOS transistor M1 can be influenced by connecting the voltage suppressing circuit in parallel between the gate and the source of the power conversion MOS transistor M1.

In step S2, during the start pulse generation period of the pwm voltage drive VP, the voltage suppressing circuit is made to slow down the voltage rise between the gate and the source of the power conversion MOS transistor M1; after the start pulse of the pulse width modulation voltage drive VP, the voltage suppressing circuit is made not to affect the speed of the rise of the on-voltage between the gate and the source of the power conversion MOS transistor M1, i.e., the on-speed. The time period represented by the generation period of the start pulse of the pulse width modulation voltage drive is the time period of the effective pulse width of the first pulse period signal generated by the pulse width modulation voltage drive VP after the power-on initial or reset starting of the power supply providing unit; the period of time indicated after the start pulse of the pwm voltage drive refers to the second pulse period signal output by the pwm voltage drive VP and the period of time thereafter. At the beginning of power-on or reset, during the period of effective pulse width of the first pulse period signal generated by driving the VP by the pulse width modulation voltage, the first pulse signal output by the VP is processed by the voltage suppression circuit, so that the switching speed of the power conversion MOS tube M1 is slowed down, the voltage and current conversion speed of the conversion circuit is slowed down, and the influence of parasitic parameters is reduced, so that the buffer circuit in the power conversion unit can effectively play a role, and the generation of excessive high voltage on some devices or nodes in the power conversion unit is suppressed. After the power-on or reset is started, in the second pulse period signal generated by the pulse width modulation voltage drive VP and the time after the second pulse period signal, the voltage suppression circuit is enabled not to work any more, the effective influence on the switching-on speed of the power conversion MOS transistor M1 is avoided, and the operation of other circuits of the power conversion unit is not influenced. There are various methods of implementing a voltage suppressing circuit that suppresses the generation of an excessive voltage. The signal of the pwm voltage drive VP may be processed using a digital logic circuit, the start pulse signal generated by VP is detected, and the speed of the pulse amplitude variation of the pulse voltage signal output between the gate and the source of the power conversion MOS transistor M1 is controlled so that the turn-on speed of the power conversion MOS transistor M1 during the effective period of the start pulse becomes slow. The digital logic circuit simultaneously controls the circuit to stop working after the initial pulse of the VP, and the pulse voltage output by the VP is directly connected to the grid and the source of the power supply conversion MOS tube M1. The method for realizing the voltage suppression circuit for suppressing the generation of the overhigh voltage can also be realized by combining the detection circuit and the control circuit through software: when the detection circuit detects that the pulse width modulation voltage drives the generation of the initial pulse signal output by the VP, the software outputs a signal to the control circuit to control the change speed of the pulse amplitude of the pulse voltage output to the grid electrode and the source electrode of the power supply conversion MOS tube M1 to be slow or to control the pulse not to be output to the post-stage circuit; and the pulse period signal after the initial pulse is not processed and is directly transmitted to a post-stage circuit.

The method of implementing the suppressing circuit for suppressing generation of the excessive voltage at the time of starting up the power supply unit in one embodiment of the present invention further includes step S3 (not shown in the figure). In step S3, the suppressing circuit is made not to affect the process of restarting the power supply unit. The power supply unit can be restarted after reset or power-off, at the moment, the electric quantity stored on the capacitor and other devices in the voltage-suppressing circuit needs to be discharged before the next startup, and all the devices such as the state machine, the comparator and the like need to be restored to the initial state, so that the restarting process of the power supply unit is not influenced.

Fig. 5 is a flowchart illustrating a method of implementing a suppressing circuit for suppressing generation of an excessive voltage at the time of startup of a power supply unit according to a preferred embodiment of the present invention. As shown in fig. 5, the method of implementing the voltage suppressing circuit of the embodiment of the present invention includes step S1 and step S2. Step S1 of the identification shown in FIG. 5 is the same as that of step S1 described previously with reference to FIG. 4. In the preferred embodiment shown in fig. 5, step S2 includes step S21 and step S22.

In step S21, a diode D, a capacitor C and a resistor R are arranged. It should be noted that a diode, a resistor and a capacitor in the embodiments of the present invention are only examples, and the singular form "a" and "an" used herein also includes plural forms, i.e., a plurality of diodes, a plurality of resistors and a plurality of capacitors, and combinations thereof, so that the final implementation effect is equivalent to that of a diode, a resistor and a capacitor in the embodiments of the present invention, if applicable, and is included in the protection scope of the present invention and is included by reference.

In step S22, the capacitor C and the resistor R are connected in parallel; connecting the anode of the diode D with the anode of the pulse width modulation voltage drive VP; one end of the parallel resistor-capacitor is connected with the cathode of the diode D, and the other end is connected with the source electrode of the power conversion MOS tube M1. The diode D is used to conduct the current or voltage passing in the forward direction and block the current or voltage passing in the reverse direction. Therefore, the diode D can pass the output of the pwm voltage driver VP, and block the possible reverse output of the capacitor C and the resistor R from the voltage or current of the pwm voltage driver VP, so as to ensure the normal operation of the pwm voltage driver VP. The capacitor C is used to slow the rising speed of the start pulse of the pwm voltage drive VP. The capacitor C absorbs the electric energy of the pwm voltage drive VP to slow the pulse rising speed of the start pulse of the voltage output between the gate and the source of the power conversion MOS transistor M1, thereby slowing the on speed of the power conversion MOS transistor M1 during the generation of the start pulse of the pwm voltage drive VP. The resistor R is used for discharging the electric quantity on the capacitor C, so that the electric quantity on the capacitor C can be released at a set speed when no pulse width modulation voltage signal exists, and the voltage suppression circuit does not influence the normal work of the power supply unit and the reset restart or power-off restart process of the power supply unit.

In a preferred embodiment, the resistance R and the capacitance C of the suppressing circuit that suppresses the generation of the excessive voltage satisfy: kr × Kc > m × Ts; where Kr is the resistance of the resistor R, Kc is the capacitance of the capacitor C, Ts is the period of the pulse voltage signal generated by the pulse width modulated voltage drive VP, and m is 5. When the resistor R and the capacitor C meet the condition that Kr × Kc >5Ts, the electric quantity on the capacitor C can be kept within the Ts time and cannot be rapidly discharged. The larger the value of Kr × Kc, the more the charge on the capacitor C remains during the time Ts. According to the simulation result, when Kr × Kc is more than 5Ts, enough electric quantity can be kept on the capacitor C; in practical environment, the use effect of the voltage suppression circuit is good.

In another preferred embodiment, the resistance R and the capacitance C of the suppressing circuit that suppresses the generation of the excessive voltage satisfy: kr × Kc < Tp/n; wherein Tp is the shortest time interval required for restarting the power supply unit, and n is 3. Tp is the minimum time interval from power-down or reset to re-restart of the power supply unit. The value of Tp may be set to 0.1 seconds, typically taking into account the time interval at which a person presses a button, and the path and delay of the restart, etc. When the resistor R and the capacitor C meet the condition of Kr × Kc < Tp/n, the electric quantity on the capacitor C can be basically discharged within the time of Tp. The smaller the value of Kr × Kc, the faster the electric quantity on the capacitor C decreases in the time Tp. According to the simulation result, when Kr × Kc is less than Tp/3, most of electric quantity can be discharged by the capacitor C within the reset interval time, and the process of restarting next time is not influenced; in practical environment, the use effect of the voltage suppression circuit is good.

Fig. 3 is a diagram showing simulation results of an application of a suppressing circuit for suppressing generation of an excessive voltage at the time of startup of a power supply unit according to a preferred embodiment of the present invention. Fig. 3a is a diagram showing simulation results of a voltage across a freewheel MOS transistor in a power supply unit not including the suppressing circuit of the present invention. Without the voltage suppression circuit, as shown in fig. 3a, the drain-source voltage on the freewheel MOS transistor would have an excessive voltage generated during the initial pulse period, but there is no excessive voltage problem after the second pulse period. Fig. 3b is a diagram showing simulation results of the voltage across the freewheel MOS transistor in the power supply unit including the voltage suppressing circuit, corresponding to fig. 3 a. The voltage suppressing circuit includes a diode, a capacitor and a resistor, and the connection and implementation steps of the diode, the capacitor and the resistor are as shown in the embodiment of fig. 5. Ts is the period of the pulse signal generated by the pulse width modulation voltage drive, which is 4us in the figure; tp is the minimum time interval for restart, which is 0.1 s. The voltage suppression circuit used in fig. 3b has a capacitance Kc of 1uF and a resistance Kr of 10 k. Therefore, Kc Kr 0.01s can satisfy both the conditions of Kc Kr >5 s 4 s 0.00002s and Kc Kr <0.1/3s 0.033 s. As can be seen from the figure, after the voltage suppression circuit is used, the rising edge of the gate-source voltage on the power conversion MOS transistor becomes gentle, the highest voltage of the drain-source voltage on the freewheel MOS transistor in the initial pulse period decreases from 80v to 63v, and the problem of the excessive high voltage disappears. Meanwhile, as Kc x Kr <0.1/3 s-0.033 s, when the power supply unit is restarted after being powered off for 0.1s, the power stored in the capacitor in the voltage-suppressing circuit can be discharged completely, and the restarting process of the power supply unit is not affected.

It should be noted that the circuitry of the present invention may be implemented in an Application Specific Integrated Circuit (ASIC) or any other similar hardware device.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned. Furthermore, it is obvious that the word "comprising" does not exclude other elements or steps, and the singular does not exclude the plural. A plurality of units or means recited in the system claims may also be implemented by one unit or means in software or hardware. The terms first, second, etc. are used to denote names, but not any particular order.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Claims (11)

1. A voltage suppression circuit for suppressing the generation of an over-high voltage when a power supply unit is started, wherein the power supply unit comprises a pulse width modulation voltage drive and a power supply conversion MOS tube, the positive pole of the pulse width modulation voltage drive is connected with the grid electrode of the power supply conversion MOS tube, and the negative pole of the pulse width modulation voltage drive is connected with the source electrode of the power supply conversion MOS tube; wherein the content of the first and second substances,

the voltage suppression circuit is connected between the grid and the source of the power conversion MOS tube in parallel; during the generation period of the initial pulse driven by the pulse width modulation voltage, the voltage suppression circuit slows down the rising speed of the voltage amplitude between the grid electrode and the source electrode of the power conversion MOS tube; after the initial pulse driven by the pulse width modulation voltage, the voltage suppression circuit does not influence the switching-on speed of the power conversion MOS tube.

2. The suppression circuit according to claim 1, further comprising: the voltage suppressing circuit does not affect the process of restarting the power supply unit.

3. The suppression circuit according to claim 1 or 2, wherein the suppression circuit includes:

a diode, a capacitor and a resistor; the capacitor is connected with the resistor in parallel; the anode of the diode is connected with the anode driven by the pulse width modulation voltage; one end of the parallel resistor capacitor is connected with the cathode of the diode, and the other end of the parallel resistor capacitor is connected with the source electrode of the power supply conversion MOS tube.

4. The suppression circuit according to claim 3, wherein the capacitance and the resistance satisfy:

Kr*Kc>m*Ts；

wherein Kr is the resistance value of the resistor, Kc is the capacitance value of the capacitor, Ts is the period of the pulse voltage signal generated by the pwm voltage drive, and m is 5.

5. The suppression circuit according to claim 3, wherein the capacitance and the resistance satisfy:

Kr*Kc<Tp/n；

wherein Tp is the shortest time interval required for restarting the power supply unit, and n is 3.

6. A method for realizing a voltage suppression circuit for suppressing the generation of an over-high voltage when a power supply unit is started, wherein the power supply unit comprises a pulse width modulation voltage drive and a power supply conversion MOS tube, the positive pole of the pulse width modulation voltage drive is connected with the grid electrode of the power supply conversion MOS tube, and the negative pole of the pulse width modulation voltage drive is connected with the source electrode of the power supply conversion MOS tube; wherein the method comprises the following steps:

s1: the voltage suppression circuit is connected between the grid electrode and the source electrode of the power conversion MOS tube in parallel;

s2: during the generation period of the initial pulse driven by the pulse width modulation voltage, the voltage suppression circuit is enabled to slow down the rising speed of the voltage amplitude between the grid electrode and the source electrode of the power conversion MOS tube; after the initial pulse driven by the pulse width modulation voltage, the voltage suppression circuit does not influence the switching speed of the power conversion MOS tube.

7. The method of claim 8, further comprising:

s3: the suppressing circuit is made not to affect the process of restarting the power supply unit.

8. The method according to claim 6 or 7, wherein the step S2 includes:

s21: arranging a diode, a capacitor and a resistor;

s22: connecting the capacitor and the resistor in parallel; connecting the anode of the diode with the anode of the pulse width modulation voltage drive; and connecting one end of the parallel resistor capacitor with the cathode of the diode, and connecting the other end of the parallel resistor capacitor with the source electrode of the power supply conversion MOS tube.

9. The method of claim 8, wherein the capacitance and the resistance satisfy:

Kr*Kc>m*Ts；

wherein Kr is the resistance value of the resistor, Kc is the capacitance value of the capacitor, Ts is the period of the pulse voltage signal generated by the pwm voltage drive, and m is 5.

10. The method of claim 10, wherein the capacitance and the resistance satisfy:

Kr*Kc<Tp/n；

wherein Tp is the shortest time interval required for restarting the power supply unit, and n is 3.

11. An electronic device comprising the voltage suppressing circuit as claimed in any one of claims 1 to 5.

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