CN111755453A

CN111755453A - 3D memory device and method of manufacturing the same

Info

Publication number: CN111755453A
Application number: CN202010478571.1A
Authority: CN
Inventors: 姚兰; 吴继君; 霍宗亮; 高晶; 周文斌
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-05-29
Filing date: 2020-05-29
Publication date: 2020-10-09
Anticipated expiration: 2040-05-29
Also published as: CN111755453B

Abstract

A3D memory device and a method of manufacturing the same are disclosed. The 3D memory device comprises a substrate, wherein a doped well region is formed on the substrate; a stacked structure on the first surface of the substrate, the stacked structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked; a plurality of channel pillars penetrating the stacked structure; the stop layer is positioned between the bottom of the channel column and the doped well region of the substrate; and a plurality of through holes penetrating through the substrate and extending from the second surface of the substrate to the bottom of each channel column respectively, wherein the through holes are filled with polysilicon, and the bottoms of the channel columns form common source connection through the polysilicon and the doped well region. The stop layer is added between the well region and the laminated structure of the substrate of the memory device, the etching depth of the channel column and the through hole is guaranteed, the through hole filled with the polycrystalline silicon is formed on the second surface of the substrate, the channel column is connected with the polycrystalline silicon through the common source formed by the well region, the erasing speed and the programming speed of the memory are improved, and the yield and the reliability of the memory device are improved.

Description

3D memory device and method of manufacturing the same

Technical Field

The present invention relates to the field of memory technology, and more particularly, to a 3D memory device and a method of manufacturing the same.

Background

The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes becomes smaller, the storage density of memory devices becomes higher. In order to further increase the memory density, a memory device of a three-dimensional structure (i.e., a 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can increase integration in multiples on a unit area of a wafer, and can reduce cost.

Existing 3D memory devices are mainly used as non-volatile flash memories. Two major non-volatile flash memory technologies employ NAND and NOR architectures, respectively. Compared with the NOR memory device, the NAND memory device has a fast writing speed, a simple erasing operation, and a smaller memory cell can be realized, thereby achieving a higher memory density. Therefore, the 3D memory device adopting the NAND structure is widely used.

In the 3D memory device of the NAND structure, gate conductors of the selection transistor and the memory transistor are provided in a stacked structure, and electrical connection of the transistors to an external circuit is provided using a large number of metal wirings. The 3D memory with the existing horizontal laminated structure can be etched from the back of a wafer to realize common source connection, but the manufacturing process is complex and difficult to control, and the formed memory structure can only perform low-speed GIDL P/E (gate-induced drain leakage program/erase), namely low-speed gate-induced leakage programming/erasing, and cannot ensure good storage efficiency of the memory. It is desirable to further improve the structure of the 3D memory device and the method of fabricating the same to improve the yield and reliability of the 3D memory device.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a 3D memory device and a method for fabricating the same, in which a stop layer is formed between a stacked structure and a well region on a substrate, an etching rate is controlled so that a channel layer can simultaneously contact a polysilicon and the well region in the substrate, and programming and erasing speeds are increased to improve yield and reliability of the 3D memory device.

According to an aspect of the present invention, there is provided a 3D memory device, comprising:

the semiconductor device comprises a substrate, a first substrate and a second substrate, wherein a doped well region is formed on the substrate;

a stacked structure on the first surface of the substrate, the stacked structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked;

a plurality of channel pillars penetrating the stacked structure;

a stop layer between the bottom of the channel pillar and the doped well region of the substrate; and

a plurality of vias extending through the substrate from the second surface of the substrate to the bottom of each of the channel pillars, respectively, the vias being filled with a semiconductor material,

wherein the first surface and the second surface are opposite surfaces of the substrate, and the bottoms of the plurality of channel pillars form a common source connection with the doped well region through the semiconductor material.

Preferably, the doped well region extends inwardly from the first surface of the substrate.

Preferably, the stop layer is a high work function dielectric layer.

Preferably, the stop layer comprises an aluminium oxide layer and the semiconductor material comprises polysilicon.

Preferably, the 3D memory device further includes:

the conductive channel penetrates through the laminated structure and is electrically connected with the CMOS circuit or the peripheral circuit on the side, far away from the substrate, of the laminated structure; and

a bit line on top of the channel pillar in electrical connection with the channel pillar.

Preferably, the doped well region covers a plurality of the channel pillars, and the channel pillars are respectively connected to the bit lines correspondingly.

According to another aspect of the present invention, there is provided a method of manufacturing a 3D memory device, including:

forming a doped well region on the substrate;

forming a stop layer and a stacked structure on a first surface of the substrate, the stacked structure including a plurality of gate conductors and a plurality of interlayer insulating layers that are alternately stacked;

forming a plurality of channel pillars penetrating through the laminated structure, wherein the stop layer is positioned between the bottoms of the channel pillars and the doped well region of the substrate;

forming a plurality of through holes respectively extending from the second surface of the substrate to the bottom of each channel column and penetrating through the substrate; and

and filling a semiconductor material into the through hole, wherein the bottoms of the channel columns form a common source connection through the semiconductor material and the doped well region, and the first surface and the second surface are two opposite surfaces of the substrate.

Preferably, the doped well region is doped P-type.

Preferably, the stop layer is a high work function dielectric layer.

Preferably, the manufacturing method further includes:

forming a conductive channel penetrating through the laminated structure, wherein the conductive channel is electrically connected with a CMOS circuit or a peripheral circuit on one side of the laminated structure far away from the substrate; and

a bit line is formed atop the channel pillar in electrical connection with the channel pillar.

Preferably, the step of forming the stop layer includes:

depositing a stop layer on the first surface of the substrate;

forming a stacked structure over the stop layer;

forming a plurality of channel pillars and via holes through the stacked structure; and

and etching the stop layer along the bottom of the channel hole, and reserving part of the stop layer at the bottom of the channel column.

According to the 3D memory device and the manufacturing method thereof provided by the invention, the stop layer is added between the well region and the laminated structure of the substrate, so that the etching depth of the trench column and the through hole is ensured, and the through hole filled with the polysilicon is formed on the second surface of the substrate, so that the trench column and the polysilicon form common source connection together, the erasing and programming speed of the memory is improved, the batch programming and erasing can be realized, and the yield and the reliability of the 3D memory device are improved.

Furthermore, in the 3D memory device, the high-work-function dielectric layer is used as the stop layer, so that the etching depth of a channel column, a through hole and the like can be ensured, the problems of erasing saturation and the like can be relieved, the structure of the 3D memory device is stable, the erasing and programming speeds are increased, and the operation speed and the reliability of the 3D memory device are increased.

Furthermore, the 3D memory device is etched from the back of the wafer substrate to form a through hole reaching the bottom of the channel hole so as to form common source connection, so that the preparation process is simplified, the cost is reduced, the manufacture of other processes on the surface of the substrate is not influenced, and the structure is stable and reliable.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1a and 1b show an equivalent circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device.

Fig. 2 illustrates a perspective view of a 3D memory device according to an embodiment of the present invention.

Fig. 3 illustrates a schematic cross-sectional view of a conventional 3D memory device.

Fig. 4a to 4p show schematic cross-sectional views of stages of a method of manufacturing a 3D memory device according to an embodiment of the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

If for the purpose of describing the situation directly on another layer, another area, the expression "directly on … …" or "on … … and adjacent thereto" will be used herein.

In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

In the 3D memory device of the NAND structure, gate conductors of the selection transistor and the memory transistor are provided in a stacked structure, and electrical connection is provided using a large number of metal wirings. The increase in metal wiring density will not only increase the process cost and process complexity, but also create problems of short circuit, increased parasitic capacitance, increased parasitic resistance, etc. In addition, the wirings distributed on one side may cause an increase in complexity of the CMOS circuit, thereby reducing an operation speed of the 3D memory device, affecting yield and reliability of the 3D memory device.

The inventors of the present application have noticed the above-mentioned problems affecting the yield and reliability of the 3D memory device, and thus have proposed a further improved 3D memory device and a method of manufacturing the same.

The present invention may be embodied in various forms, some examples of which are described below.

Fig. 1a and 1b show a circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device. The case where the memory cell string includes 4 memory cells is shown in this embodiment. It is to be understood that the present invention is not limited thereto, and the number of memory cells in the memory cell string may be any number, for example, 32 or 64.

As shown in fig. 1a, a first terminal of the memory cell string 100 is connected to a bit line BL, and a second terminal is connected to a source line SL. The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first select transistor Q1, memory transistors M1-M4, and a second select transistor Q2. The gate of the first select transistor Q1 is connected to a string select line SSL, and the gate of the second select transistor Q2 is connected to a ground select line GSL. The gates of the memory transistors M1 through M4 are connected to corresponding ones of the word lines WL1 through WL4, respectively.

As shown in fig. 1b, the first and second select transistors Q1 and Q2 of the memory cell string 100 include

gate conductors

122 and 123, respectively, and the memory transistors M1 through M4 include gate conductors 121, respectively. The

gate conductors

121, 122, and 123 correspond to a stacking order of transistors in the memory cell string 100, and adjacent gate conductors are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. Channel pillar 110 extends through the gate stack structure. In the middle portion of the channel pillar 110, a tunnel dielectric layer 112, a charge storage layer 113, and a blocking dielectric layer 114 are interposed between the gate conductor 121 and the channel layer 111, thereby forming memory transistors M1 through M4. A blocking dielectric layer 114 is sandwiched between the

gate conductors

122 and 123 and the channel layer 111 at both ends of the channel pillar 110, thereby forming a first selection transistor Q1 and a second selection transistor Q2.

In this embodiment, the channel layer 111 is composed of, for example, doped polysilicon, the tunneling dielectric layer 112 and the blocking dielectric layer 114 are respectively composed of an oxide such as silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals such as silicon nitride containing particles of a metal or a semiconductor, and the

gate conductors

121, 122, and 123 are composed of a metal such as tungsten. The channel layer 111 serves to provide channel regions for controlling the selection transistor and the memory transistor, and the doping type of the channel layer 111 is the same as that of the selection transistor and the memory transistor. For example, for N-type select and memory transistors, the channel layer 111 may be N-type doped polysilicon.

In this embodiment, the core of channel pillar 110 is channel layer 111, and tunnel dielectric layer 112, charge storage layer 113, and blocking dielectric layer 114 form a stacked structure around the core sidewall. In an alternative embodiment, the core of channel pillar 110 is an additional insulating layer, and channel layer 111, tunnel dielectric layer 112, charge storage layer 113, and blocking dielectric layer 114 form a stacked structure surrounding the core.

In this embodiment, the first and second selection transistors Q1 and Q2, the memory transistors M1 to M4 use the common channel layer 111 and the blocking dielectric layer 114. In the channel pillar 110, the channel layer 111 provides source-drain regions and a channel layer of a plurality of transistors. In an alternative embodiment, the semiconductor layer and the blocking dielectric layer of the first and second selection transistors Q1 and Q2 and the semiconductor layer and the blocking dielectric layer of the memory transistors M1 to M4, respectively, may be formed in separate steps from each other.

In a write operation, the memory cell string 100 writes data to a selected one of the memory transistors M1 through M4 using FN tunneling efficiency. Taking the memory transistor M2 as an example, while the source line SL is grounded, the ground selection line GSL is biased to a voltage of about zero volts, so that the selection transistor Q2 corresponding to the ground selection line GSL is turned off, and the string selection line SSL is biased to a high voltage VDD, so that the selection transistor Q1 corresponding to the string selection line SSL is turned on. Further, BIT line BIT2 is grounded, word line WL2 is biased at the programming voltage VPG, e.g., around 20V, and the remaining word lines are biased at the low voltage VPS 1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 via the tunneling dielectric layer 112, thereby converting data into charges stored in the charge storage layer 113 of the memory transistor M2.

In a read operation, the memory cell string 100 determines the amount of charge in the charge storage layer from the on-state of a selected one of the memory transistors M1 through M4, thereby obtaining data indicative of the amount of charge. Taking the memory transistor M2 as an example, the word line WL2 is biased at the read voltage VRD, and the remaining word lines are biased at the high voltage VPS 2. The on state of the memory transistor M2 is related to its threshold voltage, i.e., the amount of charge in the charge storage layer, so that a data value can be determined according to the on state of the memory transistor M2. The memory transistors M1, M3, and M4 are always in a conductive state, and therefore, the conductive state of the memory cell string 100 depends on the conductive state of the memory transistor M2. The control circuit judges the conductive state of the memory transistor M2 based on the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.

Fig. 2 illustrates a perspective view of a 3D memory device according to an embodiment of the present invention. For clarity, the respective insulating layers in the 3D memory device are not shown in fig. 2.

The 3D memory device shown in this embodiment includes 4 x 4 and 16 memory cell strings 100 in total, each memory cell string 100 including 4 memory cells, thereby forming a memory array of 64 memory cells in total 4 x 4. It is understood that the present invention is not limited thereto and the 3D memory device may include any number of memory cell strings, for example, 1024, and the number of memory cells in each memory cell string may be any number, for example, 32 or 64.

In the 3D memory device, the memory cell strings respectively include the respective channel pillars 110, and the common gate conductor layers 121, 122, and 123. The gate conductor layers 121, 122, and 123 are in accordance with the stacking order of the transistors in the memory cell string 100, and adjacent gate conductor layers are spaced apart from each other with an interlayer insulating layer 151, thereby forming a gate stack structure 120.

The internal structure of the channel pillar 110 is shown in fig. 1b and will not be described in detail. In the middle portion of the channel pillar 110, the gate conductor layer 121 forms memory transistors M1 through M4 together with the channel layer 111, the tunnel dielectric layer 112, the charge storage layer 113, and the gate dielectric layer 114 inside the channel pillar 110. At both ends of the channel pillar 110, the gate conductor layers 122 and 123 form the selection transistors Q1 and Q2 together with the channel layer 111 and the gate dielectric layer 114 inside the channel pillar 110.

The channel pillars 110 penetrate through the gate stack structure 120 and are arranged in an array, and a plurality of channel pillars 110 in a same column have first ends commonly connected to a same bit line (i.e., one of the bit lines BL1 to BL 4), second ends commonly connected to the substrate 101, and second ends forming a common source connection through the substrate 100.

The gate conductor 122 of the string selection transistor Q1 is divided into different gate lines by a gate line slit (gate line slit). Gate lines of the plurality of channel pillars 110 of the same row are commonly connected to the same string selection line (i.e., one of string selection lines SGD1 through SGD 4).

The gate conductors 121 of the memory transistors M1 and M4 are integrally connected at different levels. If the gate conductors 121 of the memory transistors M1 and M4 are split into different gate lines by the gate line slit, the gate lines of the same level reach the interconnect layer 132 via the respective electrical connection structures 131 to be interconnected with each other, and then are connected to the same word line (i.e., one of the word lines WL1 to WL 4) via the electrical connection structure 133.

The gate conductors of the ground select transistors Q2 are connected in one piece. If the gate conductor 123 of the ground selection transistor Q2 is split into different gate lines by the gate line slit, the gate lines reach the interconnect layer 132 via the respective electrical connection structures 131 to be interconnected with each other, and then are connected to the same ground selection line SGS via the electrical connection structure 133.

Further, a dummy channel pillar (not shown) may be included in this embodiment, and the dummy channel pillar may have the same internal structure as the channel pillar 110 and pass through at least a portion of the gate conductor in the gate stack structure. However, the dummy channel pillar is not connected to the bit line, thereby providing only a mechanical support function, and is not used for forming the select transistor and the memory transistor. Therefore, the dummy channel pillar also does not form an effective memory cell.

As shown in fig. 3, which is an inverted structure of the conventional 3D memory device, it includes a substrate 301 and a stacked structure stacked on a first surface of the substrate 301. The stacked structure includes a plurality of gate conductors 332 and 332 'and a plurality of interlayer insulating layers 351 and 351' alternately stacked, and the memory device further includes a plurality of channel pillars (4 are shown) penetrating the stacked structure. Preferably, the number of the stacked structures is, for example, 2, and two stacked structures are sequentially stacked, the first stacked structure includes a plurality of gate conductors 332 and a plurality of interlayer insulating layers 351, and the second stacked structure includes a plurality of gate conductors 332 'and a plurality of interlayer insulating layers 351'. Each laminated structure is provided with a channel column penetrating through the laminated structure, and when the two laminated structures are stacked, the corresponding channel columns are communicated with each other. Due to the etching process, the widths of the bottom and the top of the channel column are different, so that a step structure is formed at the joint of the two channel columns. The inside of the channel column is the same as the structure shown in fig. 1b, the channel column of the present embodiment includes a channel layer 311 extending along the inner wall of the channel hole, a tunneling dielectric layer 312, a charge storage layer 313 and a blocking dielectric layer 314, and an insulating gap 316 and a filling insulating layer 315 wrapping the insulating gap are further formed in the channel hole. Since the conventional 3D memory device structure is a common structure, it is not described in more detail.

The 3D memory device further includes conductive blocks 371 and bit line structures 382 formed on top of the channel pillars (at an end away from the substrate 301), and a chemically-mechanically polished insulating material 383.

In this inverted structure, to implement common source connection, an etching operation is performed on the second surface of the substrate 301 to form a via hole communicating with the plurality of trench pillars, and the via hole is filled with a polysilicon layer 392. The via is etched through the bottom of each channel pillar so that the polysilicon layer 392 is connected to the channel layer 311 at the bottom of the channel pillar. However, the process is complex and difficult to control, and the formed three-dimensional structure can only perform low-speed gate induced drain leakage current erase (GIDL), and the storage effect is poor.

The embodiment of the invention is improved on the basis of the traditional 3D memory device so as to improve the erasing and programming speed of the memory and improve the storage performance. A 3D memory device and a method of fabricating the same according to an embodiment of the present invention will be described in detail with reference to fig. 4a to 4 p.

Fig. 4a to 4p show cross-sectional views of stages of a method of manufacturing a 3D memory device according to an embodiment of the present invention. The cross-sectional view is taken along line AA in fig. 2.

First, a semiconductor substrate is provided, and then a doped well region is formed on the substrate. As shown in fig. 4a, a plurality of doped well regions are formed on a substrate 101. In this embodiment, the semiconductor substrate 101 is, for example, a single crystal silicon substrate.

In this embodiment, in order to facilitate a program operation on a memory cell in the 3D memory device, a plurality of well regions are formed in the substrate 101. The well regions include, for example, a deep N-well region 102, a high-voltage P-type doped well region 103 located in the deep N-well region 102, a high-voltage N-well region 105 adjacent to the high-voltage P-type doped well region 103, a P + doped region 104 located in the high-voltage P-type doped well region 103, and an N + doped region 106 located in the high-voltage N-well region 105. In this embodiment, the high voltage P-type doped well region 103 serves as a common source line of the channel column, the high voltage N-well 105 serves to pre-charge the common source line, and the P + doped region 104 and the N + doped region 106 serve as contact regions, respectively, to reduce contact resistance. As described later, the doped well region 103 is etched to form a common source line serving as a plurality of channel pillars in a group, and is located below the insulating stacked structure. Preferably, the doped well region 103 extends inward from the first surface of the substrate 101.

Further, a stopper layer 107 and a stacked structure including a plurality of gate conductors and a plurality of interlayer insulating layers which are alternately stacked are formed on the first surface of the substrate 101.

As shown in fig. 4b, a stop layer 107 is formed on the first surface of the substrate 101, for example, the stop layer 107 is deposited by atomic layer deposition. The stop layer 107 is used to control the etch depth of subsequent channel holes and vias and can slow the erase saturation effect in the memory device. Preferably, the stop layer 107 isThe high work function dielectric layer (high-K dielectrics), the stop layer 107, for example, comprises an aluminum oxide layer or an aluminum oxide layer, or hafnium oxide (HfO)₂). The higher dielectric constant of the stop layer 107 may improve performance by increasing program and erase rates, improving the memory window (memory window) in the threshold voltage of the memory cell.

As shown in fig. 4c, an insulating stack structure is formed on the stop layer 107. The insulating stack structure includes a plurality of interlayer insulating layers 151 and a plurality of sacrificial layers 152 alternately stacked. In this embodiment, the interlayer insulating layer 151 is composed of, for example, silicon oxide, and the sacrificial layer 152 is composed of, for example, silicon nitride. The interlayer insulating layer 151 and the sacrificial layer 152 have a certain selectivity ratio in the same etching/etching process to ensure that the interlayer insulating layer 151 is hardly removed when the sacrificial layer 152 is removed. In this case, the insulating stacked Layer structure may be formed by a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD) process. The number of the interlayer insulating layer 151 and the sacrificial layer 152 in the insulating stacked structure may include 32, 64, 96, or 128 layers, and the like, and may be set according to actual needs, which is not limited herein.

As described below, the sacrificial layer 152 will be replaced with a gate conductor 132, the gate conductor 132 being further connected to a word line. To form a conductive path from the gate conductor 132 to the word line, the plurality of sacrificial layers 152 are, for example, patterned in a step shape, i.e., an edge portion of each sacrificial layer 152 is exposed with respect to an overlying sacrificial layer to provide an electrical connection region. After the patterning step of the plurality of sacrificial layers 152, the insulating stack structure may be covered with an insulating layer. However, the present invention is not limited thereto, and the interlayer insulating layer between and over the plurality of sacrificial layers 152 may be formed using a plurality of independent deposition steps.

Furthermore, a plurality of channel columns penetrating through the laminated structure are formed, and the stop layer is located between the bottoms of the channel columns and the doped well region of the substrate.

As shown in fig. 4d, a channel hole 110 is formed in the middle region (core region) of the insulation stack structure. In this embodiment, a trench hole 110 is formed in the insulating stack structure, for example, by forming a photoresist mask on the surface of the semiconductor structure and then performing anisotropic etching. The anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. Due to the presence of the stop layer 107, the etching depth of the channel hole 110 is controlled, and after the channel hole 110 reaches the stop layer 107, a portion of the stop layer 107 is etched away, followed by stopping. The stop layer 107 is located between the bottom of the channel hole 110 and the P-type doped well 103. The photoresist mask is removed by dissolving or ashing in a solvent after etching.

In one embodiment, a 3D memory device includes a plurality of stacked structures and a plurality of trench holes communicating up and down. That is, it is necessary to stack one to more stacked structures again over the stacked structure in which the channel hole 110 has been formed. The present embodiment is illustrated by a two-layer stacked structure.

As shown in fig. 4e, filling the hole filling sacrificial layer 141 in the channel hole 110 of the formed first insulation stacked structure, a deposition process may be used to deposit a hole filling sacrificial material layer on the surface of the structure, and then a chemical mechanical polishing process is performed to polish the top of the hole filling sacrificial layer to be flush with the upper surface of the first insulation stacked structure, so as to obtain a first hole filling sacrificial layer, wherein the material of each hole filling sacrificial layer may be selected to be polysilicon, and the hole filling sacrificial layer is removed in a subsequent process.

Next, as shown in fig. 4f, an interlayer insulating layer 151 'and a sacrificial layer 152' are sequentially and alternately deposited on the structure with the first hole-filling sacrificial layer, so as to form another insulating stacked structure, i.e., a second insulating stacked structure.

Continuing, as shown in fig. 4g, a second channel hole 110 is formed in the subsequently formed second insulating stacked structure, and the second channel hole and the previously formed first channel hole are correspondingly disposed one on top of the other, and the channel hole of the upper layer exposes the corresponding hole-filling sacrificial layer 141 in the channel hole of the lower layer. The arrangement of the second insulating stack is similar to that of the first layer and will not be described here.

Finally, as shown in fig. 4h, the first hole-filling sacrificial layer 141 of the lower layer is removed based on the second channel hole 110 formed in the upper layer, thereby obtaining the channel holes 110 disposed to be communicated up and down, and exposing the stop layer 107 at the bottom of the channel holes 110. Wherein, a wet etching method may be used to remove each hole-filling sacrificial layer 141.

Further, a channel pillar is formed in the channel hole 110, as shown in fig. 4 i. The channel pillar has a structure of, for example, ONOP (oxide-nitride-oxide-polysilicon), that is, the channel pillar includes a functional sidewall layer and a channel layer 111, the functional sidewall layer continuously extending along the inside of the channel hole 110 is formed, the functional sidewall layer sequentially includes a blocking dielectric layer 114, a charge storage layer 113 and a tunneling dielectric layer 112 from the sidewall of the channel hole 110 to the center, the channel layer 111 is located on the surface of the functional sidewall layer and extends along the inner wall of the channel hole 110, and the channel layer 111 is a polysilicon layer.

The functional sidewall layer may be formed by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. In one example, blocking dielectric layer 114 may include, but is not limited to, a silicon oxide layer, charge storage layer 113 may include, but is not limited to, a silicon nitride layer, and tunneling dielectric layer 112 may include, but is not limited to, a silicon oxide layer.

In one example, the sum of the thicknesses of the functional sidewall layer and the channel layer 111 may be less than half of the width of the channel hole 110, and at this time, a reserved space for filling the insulating layer remains in the channel hole 110 after the channel layer 111 is formed. When the reserved space is reserved, the method further includes a step of forming the filling insulating layer 115 in the trench hole 110, and the filling insulating layer 115 may be formed in the trench hole 110 by using a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. The material of the filling insulation layer 115 may include an oxide dielectric layer, such as silicon oxide, etc., and the filling insulation layer 115 may fill the channel hole 110. In addition, in one example, the insulating gap 116 may also be formed in the filling insulating layer 115 by controlling the deposition process parameters of the filling insulating layer 115.

As an example, the forming of the channel layer 111 further includes the steps of: the trench hole 110 is filled with an insulating layer 115, a connection block 171 is formed on the insulating layer 115, the side edge of the connection block 171 contacts the channel layer 111, and an insulating cover 183 (shown in a subsequent process diagram) covers the surface of the connection block 117. Specifically, after the trench hole 110 is filled, the filling insulating layer 115 is etched back, and a conductive material is deposited correspondingly to form a connection block 171, where the connection block 171 is located at the top of the trench hole 110 and contacts with the functional sidewall layer and the channel layer 111 to achieve electrical connection.

Further, the specific steps of forming the stop layer 107 are as follows:

depositing a stop layer 107 on the first surface of the substrate 101; forming a stacked structure over the stop layer 107; forming a plurality of channel pillars and via holes 160 penetrating the stacked structure; and etching the stop layer 107 along the bottom of the via hole 160, leaving a portion of the stop layer at the bottom of the trench pillar.

As shown in fig. 4j, via holes 160 are formed in the stacked structure, and a space is formed between the via holes 160 and the trench holes 110. Specifically, the method comprises the following steps: forming a patterned mask layer (not shown) on the upper surface of the stacked structure, wherein an opening pattern defining the same purchased shape and position as 160 is formed in the patterned mask layer; the stacked structure is etched based on the patterned mask layer to form the via hole 160, and specifically, the stacked structure may be etched using a dry etching process or a wet etching process. The channel hole 160 extends to the upper side of the doped well region 103.

Further, as shown in fig. 4k, based on the removal of part of the stop layer 107 at the bottom of the via hole 160, the stop layer 107 may be removed by, but not limited to, a wet etching process, and the stop layer outside the trench pillar is removed to form a bottom gap. The stop layer 107 at the bottom of the trench pillar is preserved due to the influence of the etching process.

Further, the sacrificial layer 152 is removed by etching through the via hole 160 using the plurality of interlayer insulating layers 151 as an etch stop layer to form a cavity, as shown in fig. 4 l.

In forming the cavity, the cavity is formed by removing the sacrificial layer 152 in the insulating stacked structure using isotropic etching using the via hole 160 as an etchant via. The isotropic etching may employ selective wet etching or vapor etching. An etching solution is used as an etchant in wet etching, wherein the semiconductor structure is immersed in the etching solution. Etching gases are used as etchants in vapor phase etching, wherein the semiconductor structure is exposed to the etching gas.

In the case where the interlayer insulating layer 151 and the sacrificial layer 152 in the insulating stacked layer structure are composed of silicon oxide and silicon nitride, respectively, a phosphoric acid solution may be used as an etchant in wet etching, and one or more of C4F8, C4F6, CH2F2, and O2 may be used in vapor phase etching. During the etching step, the passage hole 160 is filled with an etchant. The end of the sacrificial layer 152 in the insulation stack structure is exposed in the opening of the via hole 160, and thus, the sacrificial layer 152 is contacted to the etchant. The etchant gradually etches the sacrificial layer 152 from the opening of the via hole 160 toward the inside of the insulating stack structure. The etching removes the sacrificial layer 152 with respect to the interlayer insulating layer 151 in the insulating stack structure due to the selectivity of the etchant.

Further, forming a conductive channel penetrating through the laminated structure, wherein the conductive channel is electrically connected with the peripheral circuit; and filling the cavity with a metal layer to form a gate conductor 122, wherein the plurality of gate conductors 122 and the plurality of interlayer insulating layers 151 are alternately stacked such that the plurality of channel pillars 110 penetrate the gate stack structure, as shown in fig. 4 m.

As shown in fig. 4m, first, metal is filled in the cavity and the bottom gap to form gate conductors 132 and 132'. Specifically, in forming the gate conductors 132 and 132', the cavities on both sides of the channel hole 160 are filled with a metal layer using Atomic Layer Deposition (ALD) using the channel hole 160 as a deposition channel.

In this embodiment, the metal layer is composed of tungsten, for example. The precursor source used in atomic layer deposition is, for example, tungsten hexafluoride WF6, and the reducing gas used is, for example, silane SiH4 or diborane B2H 6. In the step of atomic layer deposition, the deposition process is realized by obtaining tungsten material by chemical adsorption of a reaction product of tungsten hexafluoride WF6 and silane SiH 4.

In another embodiment, for example, an oxide layer is filled in the bottom gap and a metal is filled in the cavity to form a tungsten gate.

In the semiconductor structure, a selection transistor and a memory transistor are formed. In the middle portion of channel pillar 110, gate conductor 132 forms a memory transistor together with channel layer 111, tunnel dielectric layer 112, charge storage layer 113, and blocking dielectric layer 114 inside channel pillar 110. At both ends of channel pillar 110, gate conductor 132 forms a select transistor together with channel layer 111 (or semiconductor layer 116) and blocking dielectric layer 114 inside channel pillar 110.

Then, the insulating layer 108 on the sidewall thereof and the conductive layer connected thereto are formed in the via hole 160. An isolation layer 108 is deposited on the sidewalls of the gate line slit 104. Isolation layer 108 is formed using an insulating material, such as silicon oxide. Then, using the isolation layer 108 as a mask, a conductive layer covering the bottom and the sidewall of the via hole 160 is deposited, wherein the conductive layer includes a first conductive material layer 141 and a second conductive material layer 142. First, a first conductive material layer 141 is formed covering the bottom and top of the via hole 160 and the sidewall of the isolation layer 108. In this step, the material of the first conductive material layer 141 is titanium, the first conductive material layer 141 forms a contact region with the semiconductor substrate 101, and the material of the contact region is a conductive compound TixSiy, so that the first conductive material layer 141 and the doped region form a better ohmic contact. After the first conductive material layer 141 is formed, a second conductive material layer 142 is formed covering the first conductive material layer 141, and the second conductive material layer 142 is titanium nitride.

Further, the via hole 160 is filled with a conductive material to form the conductive pillar 143. In this step, a conductive material is deposited on the bottom and sidewalls of the conductive layer to fill the via hole 160, and a conductive pillar 143 is formed, where the material of the conductive pillar 143 includes, for example, metal tungsten. The conductive posts 143 are in direct contact with the conductive layer to make electrical connection with the doped regions. Further, the conductive layer and the conductive post 143 stacked on the upper surface of the stacked structure are removed by a Chemical Mechanical Polishing (CMP) process, i.e., etching and planarization processes are performed. Furthermore, a plurality of bit lines are formed on the tops of the channel pillars, and the channel pillars are respectively connected with the bit lines correspondingly.

As shown in fig. 4n, a plurality of bit lines 182 are formed on top of the channel pillars, and connection blocks 171 provide electrical connections between the channel pillars and the bit lines 182, the connection blocks 171 being, for example, tungsten. Specifically, a plurality of bit lines BL are formed on the connection block 171, and an insulating material 183 is filled around the plurality of bit lines BL to fix the plurality of bit lines BL and smooth the surface of the insulating material 183. The bit line BL is made of Ti/TiN or W, for example, and the insulating material 183 is silicon oxide, for example. A method of smoothing the surface of the insulating material 183 is, for example, chemical mechanical polishing.

Further, a back end of line (BEOL) and peripheral circuits are formed around the channel pillar. For example, pads may also be provided around the channel pillars for connection to peripheral circuitry, or to form CMOS circuitry.

Further, the semiconductor structure is inverted, and a plurality of through holes which respectively extend from the second surface of the substrate to the bottom of each channel column and penetrate through the substrate are formed.

As shown in fig. 4o, the semiconductor structure is flipped over and etched from the second surface of the substrate 101 to form a via 191 extending from the second surface of the substrate 101 to the bottom of the channel pillar, the via 191 penetrating the substrate 101 and reaching the bottom of the channel layer 111 through the stop layer 107. Due to the presence of the stop layer 107, the depth of the via 191 is controlled.

Further, filling polysilicon into the via, wherein the bottoms of the plurality of channel pillars form a common source connection through the polysilicon and the doped well region.

As shown in fig. 4p, the via 191 is filled with a semiconductor material 192, the semiconductor material 192 being, for example, polysilicon, so that the polysilicon is connected to the channel layer 111 inside the channel pillar through the via. Also, the channel layer 111 forms a common source connection with the doped well region 103 through polysilicon. The doped well 103 is a P-type doped region and includes monocrystalline silicon. The tunneling of electrons and holes is more pronounced in single-crystal silicon than in polysilicon, so the 3D memory device structure can increase the tunneling of electrons and holes, thereby increasing the erase and program speed of the memory. The embodiment utilizes the property of the high-work-function dielectric medium of the stop layer 107, improves the programming and erasing speed of the memory, utilizes the etching resistance of the stop layer to limit the etching depth of the channel hole and the through hole, ensures the structural stability of the device, enables the channel layer to be communicated with the polysilicon and the monocrystalline silicon, improves the tunneling efficiency of electrons and holes, and increases the erasing and programming speed of the memory.

In summary, according to the 3D memory device and the manufacturing method thereof provided by the present invention, the stop layer is added between the well region and the stacked structure of the substrate, so as to ensure the etching depth of the trench pillar and the via hole, and the via hole filled with the polysilicon is formed from the second surface of the substrate, so that the trench pillar forms a common source connection through the well region and the polysilicon, thereby increasing the erasing and programming speed of the memory, and realizing batch programming and erasing, thereby increasing the yield and reliability of the 3D memory device.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.

Claims

1. A 3D memory device, comprising:

a plurality of channel pillars penetrating the stacked structure;

2. The 3D memory device of claim 1, wherein the doped well region extends inward from the first surface of the substrate.

3. The 3D memory device of claim 1, wherein the stop layer is a high work function dielectric layer.

4. The 3D memory device of claim 3, wherein the stop layer comprises an aluminum oxide layer and the semiconductor material comprises polysilicon.

5. The 3D memory device of claim 1, further comprising:

6. The 3D memory device of claim 5, wherein the doped well region covers a plurality of the channel pillars, the channel pillars being respectively correspondingly connected to the bit lines.

7. A method of manufacturing a 3D memory device, comprising:

forming a doped well region on the substrate;

8. The method of manufacturing of claim 7, wherein the doped well region extends inward from the first surface of the substrate.

9. The method of claim 8, wherein the doped well region is P-type doped.

10. The manufacturing method according to claim 7, wherein the stop layer is a high work function dielectric layer.

11. The manufacturing method according to claim 7, further comprising:

forming a conductive channel penetrating through the laminated structure, wherein the conductive channel is electrically connected with a CMOS circuit or a peripheral circuit on one side of the laminated structure far away from the substrate; and forming a bit line on top of the channel pillar in electrical connection with the channel pillar.

12. The method of claim 11, wherein the doped well region covers a plurality of channel pillars, and the channel pillars are respectively connected to the bit lines.

13. The manufacturing method according to claim 7, wherein the step of forming the stop layer includes:

depositing a stop layer on the first surface of the substrate;

forming a stacked structure over the stop layer;