CN111739455A - Device and method for converting self-adaptive arbitrary frame frequency digital video signal and VGA (video graphics array) - Google Patents
Device and method for converting self-adaptive arbitrary frame frequency digital video signal and VGA (video graphics array) Download PDFInfo
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Abstract
The invention relates to a device and a method for self-adapting to the conversion of digital video signals with any frame frequency and VGA, wherein the method comprises the following steps: acquiring the resolution of an original digital video signal; establishing a cache region; conversion of arbitrary frame rate digital signals and VGA. The invention can realize the conversion between the output digital video of the common infrared/visible light camera and the VGA analog output. The digital video frame frequency of the invention can be randomly selected between 25Hz-300Hz, and the device can be self-adaptively converted into the frame frequency required by the standard VGA signal.
Description
Technical Field
The invention relates to a conversion method, in particular to self-adaptive conversion of any frame frequency digital video signals and VGA (video graphics array), and also relates to a conversion device, belonging to the field of imaging.
Background
In the field of infrared thermal imaging and visible light imaging at present, digital reading is the trend of a video image output interface, the output type solves the problem of loss of original image quality caused by traditional analog-to-digital conversion, and the data transmission flow is shortened.
In general, the output digital video signal includes parallel image data that is 8, 12, 14, 16 bits wide, as well as line/field sync signals (HSY, VSY) and a sync clock. The digital signals are directly connected with the FPGA pin as a main processor, so that the digital signals generally conform to the common level standard of the FPGA IO pin. The common display interface is a VGA interface, which is a display standard using analog signals, and its industry standard frame frequency is typically 60 Hz. In practical application, a display can be connected only when a video signal with a specific frame frequency is converted into a VGA interface through a special switching chip (namely FPGA).
Disclosure of Invention
In order to solve the problems, the invention provides a device and a method for self-adapting to any frame frequency digital video signal and VGA conversion. The data format conversion of the VGA display interface of any frame frequency digital video signal and standard frame frequency is also finished through the FPGA.
The technical scheme of the invention is as follows:
a self-adaptive arbitrary frame frequency digital video signal and VGA conversion method comprises the following steps:
step (1), obtaining the resolution of an original digital video signal;
step (2) establishing a cache area
The FPGA establishes two buffer areas in an external memory and performs ping-pong buffer under high frame frequency input;
step (3) conversion of arbitrary frame frequency digital signal and VGA
Setting a frame frequency threshold, when the frame frequency of the digital signal is less than the threshold, only using one buffer area for buffering, and when the frame frequency of the digital signal is more than or equal to the threshold, starting ping-pong buffering; generating an asynchronous clock in the FPGA;
when the frame frequency of the digital signal is smaller than the threshold value, the FPGA reads and caches the image in one cache region every rising edge according to the asynchronous clock, and transmits the image to a rear-end chip, and the chip completes D/A conversion according to the VGA standard frame rate and outputs an analog video image;
when the frame frequency of the digital signal is more than or equal to the threshold value, the FPGA sequentially reads images in the first buffer area and the second buffer area in a crossed manner every time of a rising edge according to the asynchronous clock, transmits the images to a rear-end chip, and the chip completes D/A conversion according to the VGA standard frame rate and outputs an analog video image;
the FPGA analyzes the input digital video signals with any frame frequency, converts the digital video signals into analog VGA time sequence signals with composite standard, and displays the analog VGA time sequence signals on the general display.
Further, in the step (1), the input digital video signal is detected through the FPGA, the number of rising edges of the frame synchronization is counted within one second, so as to obtain the frame frequency of the original digital video signal, the number of rising edges of the line synchronization signal is counted during the effective period of the frame synchronization, so as to obtain the number of lines of the image, and then the number of columns of the image is obtained according to the pulse width of the line synchronization signal, so as to obtain the resolution of the original digital video signal.
Further, in step (2), the size of each buffer is equal to the size of the image, and the sizes of the two buffer areas are the same.
Further, in the step (2), the ping-pong caching process is as follows: the front-end input image sequentially and respectively enters a first cache region and a second cache region for caching, the first cache region caches the output image at the same time, the second cache region caches the updated image in a mode of covering the previous frame of image, and after the second cache region caches the updated image, the second cache region caches the output image and the first cache region caches the updated image.
Further, in the step (3), the frame rate threshold is 100 Hz.
Further, in the step (3), the asynchronous clock is a fixed 60Hz clock.
Further, in the step (3), when the frame frequency of the digital signal is smaller than the threshold, the input video frame directly enters the first buffer cache, when a new video frame enters, the first buffer cache is updated, and the second buffer cache is reserved but not used;
when the frame frequency of the digital signal is larger than the threshold value, the input video frames sequentially enter a first cache region, a second cache region, a third cache region, a fourth cache region and the like, wherein the first frame, the second frame, the third frame, the fourth frame and the third frame enter the first cache region and the second cache region, and when a new video frame enters the first cache region or the second cache region, the original content is automatically replaced.
The invention also relates to a self-adaptive arbitrary frame frequency digital video signal and VGA conversion device, which comprises a memory, an FPGA module connected with the memory, a DAC chip connected with the FPGA module and a VGA display connected with the DAC chip; the memory comprises a first cache region and a second cache region; the memory is connected with the digital video output end with any frame frequency;
generating an asynchronous clock inside the FPGA module; when the frame frequency of the digital signal is smaller than the threshold value, the FPGA module reads and caches the image in one cache region every rising edge according to the asynchronous clock, and transmits the image to a DAC chip at the rear end, and the DAC chip completes D/A conversion according to the VGA standard frame rate and outputs an analog video image;
when the frame frequency of the digital signal is larger than or equal to the threshold value, the FPGA module sequentially reads the images in the first buffer area and the second buffer area in a crossed manner every time of the rising edge according to the asynchronous clock, the images are transmitted to the rear-end chip, the DAC chip completes D/A conversion according to the VGA standard frame rate, and analog video images are output.
Furthermore, the FPGA module controls an external video DAC chip to generate an analog signal required by a display driving interface; the FPGA module analyzes the input digital video signals with any frame frequency, converts the digital video signals into analog VGA time sequence signals with composite standard, and displays the analog VGA time sequence signals on the general display.
Compared with the prior art, the invention has the following beneficial effects:
(1) the invention adopts the FPGA chip to divide two storage areas, and because the FPGA chip has high integration level and good pin compatibility, a conversion circuit is not required to be added, so that the hardware circuit is less and stable; the software code is concise, the execution efficiency is high, and the utilization rate of the storage space is high; the FPGA is flexible to select, and bridging chips are reduced. Therefore, the requirement on the cache space is not high, and the cache space is not more than 2.4MB by taking 1024 × 768 and 14bit gray level images as examples. (2) The invention can realize the conversion between the output digital video of the common infrared/visible light camera and the VGA analog output. (3) The digital video frame frequency of the invention can be randomly selected between 25Hz-300Hz, and the device can be self-adaptively converted into the frame frequency required by the standard VGA signal.
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Fig. 1 is a block diagram of the apparatus of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Unless otherwise defined, technical or scientific terms used in the embodiments of the present application should have the ordinary meaning as understood by those having ordinary skill in the art to which the present invention belongs. The use of "first," "second," and similar language in the embodiments of the present invention does not denote any order, quantity, or importance, but rather the terms "first," "second," and similar language are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. "mounted," "connected," and "coupled" are to be construed broadly and may, for example, be fixedly coupled, detachably coupled, or integrally coupled; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. "Upper," "lower," "left," "right," "lateral," "vertical," and the like are used solely in relation to the orientation of the components in the figures, and these directional terms are relative terms that are used for descriptive and clarity purposes and that can vary accordingly depending on the orientation in which the components in the figures are placed.
Example 1
As shown in fig. 1, the FPGA-based adaptive arbitrary frame rate digital video signal and VGA conversion apparatus of this embodiment includes a DDR3 memory, an FPGA module connected to a DDR3 memory, a DAC chip connected to the FPGA module, and a VGA display connected to the DAC chip; the DDR3 memory includes a first cache bank A and a second cache bank B; the memory is connected with the digital video output end with any frame frequency.
The hardware circuit of the device comprises a connector which is used as an input interface and meets the FPGA IO level standard, an FPGA processing chip, a peripheral DDR3 memory (random access memory), a DA control chip and an output connector which meets the electrical characteristics of the standard VGA.
The FPGA chip can manage the peripheral storage device and realize the management of the ping-pong cache structure in the peripheral storage (random access memory), and is also connected with an external video DAC chip to control the external video DAC chip and generate analog signals required by the display driving interface.
As shown in fig. 1, digital signals of any frame frequency enter a buffer area, an FPGA chip switches a buffer channel according to the frame frequency, low-frequency digital video is only buffered by a buffer area a, high-frequency digital video is buffered by the buffer area a or B to realize ping-pong alternate storage, finally the FPGA chip captures real-time images according to an internal asynchronous clock (60 Hz), and finally the images are input to a DAC chip, and the chip analyzes the input digital video data and converts the digital signals into analog signals and synchronous control signals of a VGA.
Based on the above device, the method for converting the digital video signal with any self-adaptive frame rate and the VGA based on the FPGA of the embodiment includes the following steps:
step (1), obtaining the resolution of an original digital video signal;
the FPGA module detects an input digital video signal, counts the number of rising edges of frame synchronization within one second to obtain the frame frequency F of the original digital video signal, counts the number of the rising edges of a line synchronization signal during the effective period of the frame synchronization to obtain the number of lines of an image, and obtains the number of columns of the image according to the pulse width of the line synchronization signal so as to obtain the resolution Q of the original digital video signal.
Step (2) establishing a cache area
The FPGA module establishes two cache areas in an external DDR3 memory, the two cache areas are named as an A cache and a B cache respectively, the size of each cache is equal to the size of an image, and therefore ping-pong cache under high frame frequency input is achieved: the front-end input images sequentially enter an A/B cache respectively, the A cache outputs the images at the same moment, the B cache updates the images in a mode of covering the previous frame of image, and after the B cache updating is finished, the B cache outputs the images and the A cache updates the images.
Step (3) conversion of arbitrary frame frequency digital signal and VGA
Setting frame frequency threshold value as 100Hz, when the frame frequency F of the digital signal is less than 100Hz, only using A buffer, when the frame frequency F of the digital signal is more than or equal to 100Hz, starting ping-pong buffer. While a fixed 60Hz clock (asynchronous clock T1) is generated internally in the FPGA.
When the frame frequency of the digital signal is F <100Hz, the read-write and refresh rate of the DDR3 meets the real-time transmission requirement because the frame frequency is lower. At the moment, the input video frame directly enters the buffer A, the buffer A is updated after a new video frame enters, and the buffer B is reserved but not used.
And the FPGA reads the image in the buffer A at each rising edge according to the asynchronous clock T1, transmits the image to a DAC chip at the rear end, and the DAC chip finishes D/A conversion according to the VGA standard frame rate of 60Hz and outputs an analog video image.
When the frame frequency F of the digital signal is larger than or equal to 100Hz, the read-write and refresh rates of the DDR3 are difficult to meet the real-time transmission requirement because the frame frequency is higher. At this time, a second block buffer B (the size is the same as A) is opened up, and ping-pong operation is realized by the A/B buffer. The input video frames enter A in sequence from the first frame, B in sequence from the second frame, A in sequence from the third frame, B in sequence from the fourth frame, and so on. For A/B caching, when a new video frame enters, the original content is automatically replaced.
And the FPGA sequentially reads the images in the A and B caches in a crossing way at each rising edge according to the asynchronous clock T1, and transmits the images to the DAC chip at the rear end, and the DAC chip finishes D/A conversion according to the VGA standard frame rate of 60Hz and outputs analog video images.
Finally, the conversion of the digital signal with any frame frequency and the VGA is realized.
The FPGA module realizes the function of a video controller, analyzes an input digital video signal with any frame frequency, converts the digital video signal into an analog VGA time sequence signal with a composite standard, and can directly display the analog VGA time sequence signal on a general display.
The embodiment is applied to a long-wave infrared imaging demonstration device, the detector specification is 768 × 8, the front cut-off wavelength is not more than 7.9uM, the rear cut-off wavelength is not less than 10.5uM, the image output frequency is 40Hz, the image is a 14-bit gray image, and the digital image signal level standard LVCMOS is 3.3V, however, other level standards including TTL, CMOS, LVTTL, ECL, PECL, LVPECL at low rate and LVDS, GTL, PGTL, CML, HSTL, SSTL and the like at high rate are also applicable.
The digital image is directly displayed on a rear-end VGA liquid crystal display after being automatically subjected to frame frequency and resolution conversion by the device of the embodiment.
The cache chip can use DDR 2-5 (DDR: Double Data Rate Synchronous Random-Access Memory). The FPGA main processing chip selects XilinxKintex-7 series, and the DAC chip selects Analog Device company ADV 7125. The FPGA switches a cache channel according to the frame frequency, the low-frequency digital video only passes through the A cache, the high-frequency digital video passes through the A/B cache to realize ping-pong alternate storage, finally the FPGA captures a real-time image according to an internal asynchronous clock (60 Hz), and finally the image is input into a DAC chip which analyzes input digital video data and converts the digital signal into an analog signal and a synchronous control signal of the VGA.
Example 2
The FPGA-based adaptive arbitrary frame rate digital video signal and VGA conversion apparatus and method of this embodiment are the same as those of embodiment 1.
The embodiment is applied to a search and tracking sensing head of a certain air defense system, the detector specification is 640 x 512, the spectral response wavelength range is 3.7-4.8 uM, the image output frequency is 100Hz, the image is a 16-bit gray image, and two paths of LVDS digital outputs are provided.
The digital image is directly displayed on a rear-end VGA liquid crystal display after frame frequency and resolution conversion is automatically completed by the device of the embodiment.
The cache chip uses an SRAM (Static Random-Access Memory). The FPGA main processing chip selects Xilinx Artix-7 series, and the DAC chip selects ADV7123 of AD company. The FPGA switches a cache channel according to the frame frequency, the low-frequency digital video only passes through the A cache, the high-frequency digital video passes through the A/B cache to realize ping-pong alternate storage, finally the FPGA captures a real-time image according to an internal asynchronous clock (60 Hz), and finally the image is input into a DAC chip which analyzes input digital video data and converts the digital signal into an analog signal and a synchronous control signal of the VGA.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent methods or equivalent procedures that are used in the present specification and drawings, or directly or indirectly applied to other related technical fields are also included in the scope of the present invention.
Claims (9)
1. A self-adaptive conversion method of any frame frequency digital video signal and VGA is characterized in that: the method comprises the following steps:
step (1), obtaining the resolution of an original digital video signal;
step (2) establishing a cache area
The FPGA establishes two buffer areas in an external memory and performs ping-pong buffer under high frame frequency input;
step (3) conversion of arbitrary frame frequency digital signal and VGA
Setting a frame frequency threshold, when the frame frequency of the digital signal is less than the threshold, only using one buffer area for buffering, and when the frame frequency of the digital signal is more than or equal to the threshold, starting ping-pong buffering; generating an asynchronous clock in the FPGA;
when the frame frequency of the digital signal is smaller than the threshold value, the FPGA reads and caches the image in one cache region every rising edge according to the asynchronous clock, and transmits the image to a rear-end chip, and the chip completes D/A conversion according to the VGA standard frame rate and outputs an analog video image;
when the frame frequency of the digital signal is more than or equal to the threshold value, the FPGA sequentially reads images in the first buffer area and the second buffer area in a crossed manner every time of a rising edge according to the asynchronous clock, transmits the images to a rear-end chip, and the chip completes D/A conversion according to the VGA standard frame rate and outputs an analog video image;
the FPGA analyzes the input digital video signals with any frame frequency, converts the digital video signals into analog VGA time sequence signals with composite standard, and displays the analog VGA time sequence signals on the general display.
2. The method of adaptive arbitrary frame rate digital video signal and VGA conversion according to claim 1, wherein: in the step (1), the input digital video signal is detected through the FPGA, the number of the rising edges of the frame synchronization is counted within one second, the frame frequency of the original digital video signal is obtained, the number of the rising edges of the line synchronization signal is counted during the effective period of the frame synchronization, the number of lines of the image is obtained, and then the number of columns of the image is obtained according to the pulse width of the line synchronization signal, so that the resolution of the original digital video signal is obtained.
3. The method of adaptive arbitrary frame rate digital video signal and VGA conversion according to claim 1, wherein: in the step (2), the size of each cache region is equal to the size of the image, and the sizes of the two cache regions are the same.
4. The method of adaptive arbitrary frame rate digital video signal and VGA conversion according to claim 1, wherein: in the step (2), the ping-pong caching process is as follows: the front-end input image sequentially and respectively enters a first cache region and a second cache region for caching, the first cache region caches the output image at the same time, the second cache region caches the updated image in a mode of covering the previous frame of image, and after the second cache region caches the updated image, the second cache region caches the output image and the first cache region caches the updated image.
5. The method of adaptive arbitrary frame rate digital video signal and VGA conversion according to claim 1, wherein: in the step (3), the frame frequency threshold is 100 Hz.
6. The method of adaptive arbitrary frame rate digital video signal and VGA conversion according to claim 1, wherein: in the step (3), the asynchronous clock is a fixed 60Hz clock.
7. The method of adaptive arbitrary frame rate digital video signal and VGA conversion according to claim 1, wherein: in the step (3), when the frame frequency of the digital signal is smaller than the threshold value, the input video frame directly enters the first cache region for caching, when a new video frame enters, the first cache region is updated, and the second cache region is reserved but not used;
when the frame frequency of the digital signal is larger than the threshold value, the input video frames sequentially enter a first cache region, a second cache region, a third cache region, a fourth cache region and the like, wherein the first frame, the second frame, the third frame, the fourth frame and the third frame enter the first cache region and the second cache region, and when a new video frame enters the first cache region or the second cache region, the original content is automatically replaced.
8. An adaptive arbitrary frame frequency digital video signal and VGA conversion device, characterized in that: the device comprises a memory, an FPGA module connected with the memory, a DAC chip connected with the FPGA module and a VGA display connected with the DAC chip; the memory comprises a first cache region and a second cache region; the memory is connected with the digital video output end with any frame frequency;
generating an asynchronous clock inside the FPGA module; when the frame frequency of the digital signal is smaller than the threshold value, the FPGA module reads and caches the image in one cache region every rising edge according to the asynchronous clock, and transmits the image to a DAC chip at the rear end, and the DAC chip completes D/A conversion according to the VGA standard frame rate and outputs an analog video image;
when the frame frequency of the digital signal is larger than or equal to the threshold value, the FPGA module sequentially reads the images in the first buffer area and the second buffer area in a crossed manner every time of the rising edge according to the asynchronous clock, the images are transmitted to the rear-end chip, the DAC chip completes D/A conversion according to the VGA standard frame rate, and analog video images are output.
9. The apparatus according to claim 8, wherein said means for adaptively converting between arbitrary frame rate digital video signals and VGA comprises: the FPGA module controls an external video DAC chip to generate an analog signal required by a display driving interface; the FPGA module analyzes the input digital video signals with any frame frequency, converts the digital video signals into analog VGA time sequence signals with composite standard, and displays the analog VGA time sequence signals on the general display.
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| CN105577985A (en) * | 2015-12-29 | 2016-05-11 | 上海华力创通半导体有限公司 | Digital image processing system |
| CN110287130A (en) * | 2018-03-19 | 2019-09-27 | 爱思开海力士有限公司 | Storage device and its operating method |
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| CN113030872A (en) * | 2021-03-18 | 2021-06-25 | 中国电子科技集团公司第三十八研究所 | High-low frequency excitation waveform alternate generation method suitable for Mars subsurface detection radar |
| CN113030872B (en) * | 2021-03-18 | 2023-05-16 | 中国电子科技集团公司第三十八研究所 | High-low frequency excitation waveform alternate generation method suitable for Mars subsurface detection radar |
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