CN111726119B - Key detection circuit and detection method - Google Patents
Key detection circuit and detection method Download PDFInfo
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- CN111726119B CN111726119B CN202010613177.4A CN202010613177A CN111726119B CN 111726119 B CN111726119 B CN 111726119B CN 202010613177 A CN202010613177 A CN 202010613177A CN 111726119 B CN111726119 B CN 111726119B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M11/00—Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
- H03M11/20—Dynamic coding, i.e. by key scanning
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Abstract
The application discloses a key detection circuit and a key detection method. The key detection circuit comprises a voltage detection module, an I/O interface detection module, a selection module and a first isolation module, wherein the voltage detection module is used for detecting voltage signals caused by different keys; the I/O interface detection module is used for detecting high-low level sequence signals caused by different keys; the selection module is used for switching and connecting with the I/O interface detection module or the voltage detection module; the first isolation module is used for isolating the selection module and the I/O interface detection module. According to the technical scheme provided by the embodiment of the application, the heavy workload caused by respectively using the two detection plates to detect the voltage and the I/O interface in the existing key detection can be solved by providing the key detection circuit which can select between the I/O interface detection module and the voltage detection module.
Description
Technical Field
The present disclosure relates generally to the field of embedded system detection, and more particularly, to a key detection circuit and a detection method.
Background
In the display field, the display device includes various keys such as a power key, a frequency modulation key, a sound key, and the like. These keys are detected either through I/O interface detection or voltage detection. According to the characteristics of different display devices, the two detection modes need to be switched, and the detection is performed by switching different detection plates back and forth, so that the workload is increased and the personnel is wasted.
Disclosure of Invention
In view of the foregoing drawbacks or shortcomings of the prior art, it is desirable to provide a key detection circuit that can support switching between different detection modes.
In a first aspect, a key detection circuit is provided, including a voltage detection module, an I/O interface detection module, a selection module, and a first isolation module, where,
the voltage detection module is used for detecting voltage signals caused by different keys;
the I/O interface detection module is used for detecting high-low level sequence signals caused by different keys;
the selection module is used for switching and connecting with the I/O interface detection module or the voltage detection module;
the first isolation module is used for isolating the selection module and the I/O interface detection module.
In some embodiments, the selection module includes a switching transistor having a gate receiving the selection control signal, a first pole connected to the first isolation module, and a second pole connected to the first power signal.
In some embodiments, the first isolation module includes a plurality of diodes, a first pole of each diode being connected to a first pole of a corresponding key, and a second pole of each diode being connected to the selection module.
In some embodiments, the voltage detection module includes a voltage dividing resistor, a detection node, a plurality of detection resistors, and a voltage detector, wherein a first pole of the voltage dividing resistor is connected to the second power signal, a second pole of the voltage dividing resistor is connected to the detection node, a first pole of each detection resistor is connected to the detection node, a second pole of each detection resistor is connected to a second pole of a corresponding key, and the voltage detector detects a voltage of the detection node.
In some embodiments, each sense resistor takes on a different resistance value than the other.
In some embodiments, the voltage detection module includes a voltage dividing resistor, a detection node, a plurality of detection resistors, and a voltage detector, wherein a first pole of the voltage dividing resistor is connected with the second power signal, a second pole of the voltage dividing resistor is connected with the detection node, a first pole of each detection resistor is connected with the detection node, a second pole of each detection resistor is respectively connected with a second pole of a corresponding key, and the voltage detector detects the voltage of the detection node; the selection control signal and the second power supply signal adopt the same signal.
In some embodiments, the I/O interface detection module includes an I/O interface detector coupled to a first pole of the key and a second pole of the key is coupled to the third power signal.
In some embodiments, the first isolation module further includes a plurality of diodes, a first pole of each diode is connected to a second pole of a corresponding key, and a second pole of each diode is connected to a third power signal.
In some embodiments, the selection module includes a switching transistor having a gate receiving the selection control signal, a first pole connected to the first isolation module, and a second pole connected to the first power signal;
the first isolation module comprises a plurality of diodes, a first pole of each diode is connected with a first pole of a corresponding key, and a second pole of each diode is connected with the selection module;
the voltage detection module comprises voltage dividing resistors, detection nodes, a plurality of detection resistors and a voltage detector, wherein a first pole of each voltage dividing resistor is connected with a second power supply signal, a second pole of each voltage dividing resistor is connected with the detection node, the first pole of each detection resistor is connected with the detection node, the second pole of each detection resistor is respectively connected with the second pole of the corresponding key, and the voltage detector detects the voltage of the detection node;
the I/O interface detection module comprises an I/O interface detector, the I/O interface detector is connected with a first pole of the key, and a second pole of the key is connected with a third power supply signal;
the second isolation module comprises a plurality of diodes, the first poles of the diodes are respectively connected with the second poles of the corresponding keys, and the second poles of the diodes are connected with a third power supply signal.
In a second aspect, a detection method for a key detection circuit provided in embodiments of the present application is provided, where the key detection circuit includes a voltage detection mode and an I/O interface detection mode,
when the voltage detection mode is selected, the selection control signal and the second power supply signal are connected to a high level, the high level of the third power supply signal is cut off, the voltage detection module works, and the voltage of the detection node is detected through the voltage detector to determine the key state;
when the voltage detection mode is selected, the third power supply signal is connected with a high level, the high level of the selection control signal and the high level of the second power supply signal are cut off, the I/O interface detection circuit works, and the I/O interface detector detects different high-low level sequences to determine the key state.
According to the technical scheme provided by the embodiment of the application, the heavy workload caused by respectively using the two detection plates to detect the voltage and the I/O interface in the existing key detection can be solved by providing the key detection circuit which can select between the I/O interface detection module and the voltage detection module. Furthermore, according to some embodiments of the present application, by setting the first isolation module, interference of the selection module on the detection of the I/O interface can be further solved, and an accurate detection result is obtained. In addition, according to some embodiments of the present application, by setting the second isolation module, interference of the I/O interface detection module on voltage detection can be further solved, and an accurate detection result is obtained.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings, in which:
FIG. 1 shows an exemplary block diagram of a detection circuit according to an embodiment of the present application;
fig. 2 shows an exemplary schematic diagram of a detection circuit according to an embodiment of the present application.
Detailed Description
The present application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be noted that, for convenience of description, only the portions related to the invention are shown in the drawings.
Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
The inventor finds that the following problems exist in key detection: the various keys of the display device are detected by means of I/O interface detection or voltage detection. The voltage detection is to judge the key pressing state by detecting different voltages of the detection nodes after different keys are pressed. The I/O interface detection is to judge the key pressing state by detecting the high-low level sequence signals presented on the I/O pins after different keys are pressed. In actual detection, the voltage detection and the I/O interface detection respectively adopt respective detection circuits, and when the two detection boards need to carry out switching detection back and forth, the workload is increased and the personnel is wasted.
In order to solve the above problems, the present application provides a key detection circuit supporting voltage detection and I/O interface detection.
Referring to fig. 1, fig. 1 is a block diagram illustrating a key detection circuit according to an embodiment of the present application. A key detection circuit comprises a voltage detection module 101, an I/O interface detection module 102, a selection module 103 and a first isolation module 104, wherein,
the voltage detection module 101 is used for detecting voltage signals caused by different keys;
the I/O interface detection module 102 is used for detecting high-low level sequence signals caused by different keys;
the selection module 103 is used for switching connection with the I/O interface detection module or connection with the voltage detection module;
the first isolation module 104 is used to isolate the selection module and the I/O interface detection module.
By integrating the voltage detection circuit and the I/O interface detection circuit, the voltage detection and the I/O key detection modes can be used respectively, the applicable scene of the key circuit is enlarged, and the development cost of the key plate detection is reduced.
Fig. 2 shows a schematic diagram of a key detection circuit according to an embodiment of the present application. The selection module comprises a switching transistor T1 and a pull-down resistor R8, wherein a first pole of the gate of the switching transistor T1 receiving a selection control signal EN is connected with the first isolation module 104, and a second pole is connected with the first power supply signal GND; the first pole of the pull-down resistor R8 is connected to the gate of the switching transistor T1 and the second pole is connected to the first power supply signal GND.
Note that, the current limiting resistor R7 is set according to the characteristics of the switching transistor used, and typically, the resistance of the current limiting resistor R7 is smaller than the resistance of the pull-down resistor R8. When the switching transistor needs to be limited, the current limiting resistor R7 is set, otherwise, the current limiting resistor R7 is not set. For example, when a MOS transistor is used as the switching transistor, the current limiting resistor R7 may not be provided. Whether the key detection circuit adopts the voltage detection mode or the I/O interface detection mode can be controlled according to the selection control signal EN. The first power signal GND may be a ground signal. When the selection control signal EN is connected with a high-potential signal, the grid electrode is connected with a high potential so that the switching transistor T1 is turned on; when the selection control signal EN turns off the high potential signal, the gate potential is low by the pull-down resistor R8, so that the switching transistor T1 is turned off.
In some embodiments, the first isolation module 104 includes a plurality of diodes D2 to D5, a first pole of each diode being connected to a first pole of a corresponding key, and a second pole being connected to the selection module 103.
As shown in fig. 2, the first isolation module is not disposed between the keys R2 to R5, so that the first pole level of the key detected by the I/O detector will be the same, and therefore, it is necessary to dispose the first isolation module between the selection module 103 and the I/O detection pin, i.e., the first pole of the key, to isolate the interference to the I/O interface detection.
The diode has unidirectional conductivity, so that the interference of the first pair of switch transistors on the detection of the I/O interface can be isolated, and detection errors caused by the same level detected by the I/O detector are avoided.
In some embodiments, the voltage detection module 101 includes a voltage dividing resistor R1, a detection node N, a plurality of detection resistors R2 to R5, and a voltage detector, wherein a first pole of the voltage dividing resistor R1 is connected to the second power supply signal pwer_adc, a second pole is connected to the detection node N, a first pole of each detection resistor is connected to the detection node N, a second pole of each detection resistor is connected to a second pole of a corresponding key, and the voltage detector detects a voltage of the detection node N.
Wherein, each detection resistor adopts different resistance values.
When different keys are pressed, different detection resistors participate in voltage division, so that the voltage of the detection node N is different. By detecting different voltages by the voltage detector, it is possible to determine which key has been pressed. The voltage detector may be implemented as an ADC module of an SOC chip, which may be a SOC chip model RK 3399.
Specifically, when the key K2 is closed, the voltage dividing resistor R1 and the detection resistor R2 divide the second power supply signal pwer_adc, and at this time, the voltage value of the detection node N is r2++r2)/(r1+r2) ×pwer_adc; when the key K3 is closed, the voltage dividing resistor R1 and the detection resistor R3 divide the second power supply signal pwer_adc, and at this time, the voltage value of the detection node N is r3++r3) ×pwer_adc. Similarly, when K4 and K5 are closed, the voltage value of the corresponding detection node N is r4++r4) ×pwer_adc and r5++r5) ×pwer_adc, respectively. When a plurality of keys are pressed at the same time, the corresponding detection resistors are connected in parallel and then participate in voltage division. For example, when the keys K2 and K3 are closed, the detection resistors R2 and R3 are connected in parallel and then divided by the dividing resistor. Similarly, when the keys K2, K3 and K4 are closed, the detection resistors R2, R3 and R4 are connected in parallel and then divided by the voltage dividing resistor. The voltage at the detection node will be different for different key presses. Here, no analysis is performed for each case.
In some embodiments, the I/O interface detection module includes an I/O interface detector coupled to a first pole of the key, a second pole of the key coupled to a third POWER signal POWER_I/O. At this time, the I/O interface detector will receive different high and low levels when different keys are pressed. The third power supply signal is high level, and when the key K2 is pressed, the high-low level sequence received by the I/O interface detector is 1000; when the key K3 is pressed, the high-low level sequence received by the I/O interface detector is 0100; when the keys K2 and K3 are pressed, the high-low level sequence received by the I/O interface detector is 1100. It can be understood that the I/O interface corresponding to the pressed key will become high level, so the pressed state of each key can be determined by the high-low level sequence received by the I/O interface detector. The I/O interface detector can be a single chip microcomputer or an SOC chip. Voltage detection and I/O detection may be implemented with one SOC chip, for example, with the RK3399 chip. It should be noted that, in this embodiment, only 4 cases of keys are given, and any number of keys may be used according to the detected keys.
In some embodiments, the second isolation module 105 further includes a second isolation module 105, where the second isolation module 105 includes a plurality of diodes D6 to D9, and a first pole of each diode is connected to a second pole of a corresponding key, and a second pole of each diode is connected to the third POWER signal power_i/O. Thus, the I/O interface detection module is isolated from interfering with ADC detection. If the second isolation module 105 is not provided, the second poles of the keys are interconnected, so that all the detection circuits are connected in parallel, and the voltage values of the detection nodes are the same, thereby causing detection errors.
In addition, in order to save the number of signals, the selection control signal and the second power supply signal use the same signal.
Next, the operation of the entire key detection circuit of fig. 2 will be described.
When the POWER_ADC and the selection control signal EN are connected with a high-level signal and cut off the high-level signal of the POWER_I/O, the switch transistor T1 is turned on, the voltage detection module works, the POWER_ADC level signal is divided by the voltage dividing resistor and the detection resistor according to the key press, and the corresponding voltage is acquired at the detection node N, so that the key press condition is judged.
When the POWER_I/O is connected with a high level, the POWER_ADC and a high level signal of the selection control signal EN are cut off, the switch transistor T1 is cut off, the I/O interface detection module works, and the I/O interface detector receives a corresponding high-low level sequence signal according to the key press, so that the key press condition is judged.
The application also provides a detection method for the key detection circuit provided by the embodiments of the application, the key detection circuit comprises a voltage detection mode and an I/O interface detection mode,
when the voltage detection mode is required to be selected, the selection control signal and the second power supply signal are connected to a high level, the third power supply signal is cut off to a high level, the voltage detection module works, and the voltage of the detection node is detected through the voltage detector to determine the key state;
when the voltage detection mode is required to be selected, the third power supply signal is connected with a high level, the selection control signal and the second power supply signal are cut off from the high level, the I/O interface detection circuit works, and the I/O interface detector detects different high-low level sequences to determine the key state.
The foregoing description is only of the preferred embodiments of the present application and is presented as a description of the principles of the technology being utilized. It will be appreciated by persons skilled in the art that the scope of the invention referred to in this application is not limited to the specific combinations of features described above, but it is intended to cover other embodiments in which any combination of features described above or equivalents thereof is possible without departing from the spirit of the invention. Such as the above-described features and technical features having similar functions (but not limited to) disclosed in the present application are replaced with each other.
Claims (10)
1. A key detection circuit is characterized by comprising a voltage detection module, an I/O interface detection module, a selection module and a first isolation module, wherein,
the voltage detection module is used for detecting voltage signals caused by different keys;
the I/O interface detection module is used for detecting high-low level sequence signals caused by different keys;
the selection module is used for switching and connecting with the I/O interface detection module or the voltage detection module;
the first isolation module is used for isolating the selection module and the I/O interface detection module.
2. The key detection circuit of claim 1, wherein the selection module comprises a switching transistor and a pull-down resistor,
the grid electrode of the switching transistor receives a selection control signal, the first electrode is connected with the first isolation module, and the second electrode is connected with a first power supply signal;
the first pole of the pull-down resistor is connected with the grid electrode of the switch transistor, and the second pole is connected with a first power supply signal.
3. The key detection circuit of claim 1, wherein the first isolation module comprises a plurality of diodes, a first pole of each diode being connected to a first pole of a corresponding key, a second pole of each diode being connected to the selection module.
4. The key detection circuit according to claim 1, wherein the voltage detection module includes a voltage dividing resistor, a detection node, a plurality of detection resistors, and a voltage detector, a first pole of the voltage dividing resistor is connected to the second power signal, a second pole of the voltage dividing resistor is connected to the detection node, a first pole of each of the detection resistors is connected to the detection node, a second pole of each of the detection resistors is connected to a second pole of a corresponding key, and the voltage detector detects a voltage of the detection node.
5. The key detection circuit of claim 4, wherein each of the detection resistors has a different resistance value from each other.
6. The key detection circuit of claim 2, wherein,
the voltage detection module comprises voltage dividing resistors, detection nodes, a plurality of detection resistors and a voltage detector, wherein a first pole of each voltage dividing resistor is connected with a second power supply signal, a second pole of each voltage dividing resistor is connected with the detection node, a first pole of each detection resistor is connected with the detection node, a second pole of each detection resistor is respectively connected with a second pole of a corresponding key, and the voltage detector detects the voltage of each detection node;
the selection control signal and the second power supply signal adopt the same signal.
7. The key detection circuit of claim 1, wherein the I/O interface detection module comprises an I/O interface detector, the I/O interface detector coupled to a first pole of the key and a second pole of the key coupled to a third power signal.
8. The key detection circuit of any of claims 1-7, further comprising a second isolation module, the second isolation module comprising a plurality of diodes, a first pole of each diode being respectively connected to a second pole of a corresponding key, a second pole of each diode being connected to a third power signal.
9. The key detection circuit of claim 1, wherein the selection module comprises a switching transistor, a gate of the switching transistor receives a selection control signal, a first pole is connected to the first isolation module, and a second pole is connected to a first power signal;
the first isolation module comprises a plurality of diodes, a first pole of each diode is connected with a first pole of a corresponding key, and a second pole of each diode is connected with the selection module;
the voltage detection module comprises voltage dividing resistors, detection nodes, a plurality of detection resistors and a voltage detector, wherein a first pole of each voltage dividing resistor is connected with a second power supply signal, a second pole of each voltage dividing resistor is connected with the detection node, a first pole of each detection resistor is connected with the detection node, a second pole of each detection resistor is respectively connected with a second pole of a corresponding key, and the voltage detector detects the voltage of each detection node;
the I/O interface detection module comprises an I/O interface detector, the I/O interface detector is connected with a first pole of a key, and a second pole of the key is connected with a third power supply signal;
the first electrode of each diode is respectively connected with the second electrode of the corresponding key, and the second electrode of each diode is connected with the third power supply signal.
10. A detection method for a key detection circuit according to any one of claims 1 to 7 or claim 9, wherein the key detection circuit includes a voltage detection mode and an I/O interface detection mode,
when a voltage detection mode is selected, the selection control signal and the second power supply signal are connected to a high level, the high level of the third power supply signal is cut off, the voltage detection module works, and the voltage of the detection node is detected through the voltage detector to determine the pressing state of each key;
when the voltage detection mode is selected, the third power supply signal is connected with a high level, the high level of the selection control signal and the high level of the second power supply signal are cut off, the I/O interface detection circuit works, and the I/O interface detector detects different high-low level sequences to determine the pressing state of each key.
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