CN111726119A - Key detection circuit and detection method - Google Patents

Key detection circuit and detection method Download PDF

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Publication number
CN111726119A
CN111726119A CN202010613177.4A CN202010613177A CN111726119A CN 111726119 A CN111726119 A CN 111726119A CN 202010613177 A CN202010613177 A CN 202010613177A CN 111726119 A CN111726119 A CN 111726119A
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detection
pole
voltage
key
module
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CN111726119B (en
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王志懋
管恩慧
李咸珍
李亮
刘根禹
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M11/00Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
    • H03M11/20Dynamic coding, i.e. by key scanning

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  • Theoretical Computer Science (AREA)
  • Input From Keyboards Or The Like (AREA)

Abstract

The application discloses a key detection circuit and a detection method. The key detection circuit comprises a voltage detection module, an I/O interface detection module, a selection module and a first isolation module, wherein the voltage detection module is used for detecting voltage signals caused by different keys; the I/O interface detection module is used for detecting high and low level sequence signals caused by different keys; the selection module is used for switching and connecting the I/O interface detection module or the voltage detection module; the first isolation module is used for isolating the selection module and the I/O interface detection module. According to the technical scheme provided by the embodiment of the application, the key detection circuit capable of selecting between the I/O interface detection module and the voltage detection module is provided, so that heavy workload caused by the fact that two detection boards are used for voltage detection and I/O interface detection in the conventional key detection can be solved.

Description

Key detection circuit and detection method
Technical Field
The present disclosure relates generally to the field of embedded system detection, and more particularly, to a key detection circuit and a key detection method.
Background
In the display field, the display device includes various keys such as a power key, a frequency modulation key, a sound key, and the like. These keys are detected by I/O interface detection or voltage detection. According to the characteristics of different display devices, switching needs to be carried out in two detection modes, and the detection is carried out by adopting different detection plates to carry out switching back and forth, so that the workload is increased and the personnel waste is caused.
Disclosure of Invention
In view of the above-mentioned shortcomings or drawbacks of the prior art, it is desirable to provide a key detection circuit capable of supporting switching between different detection modes.
In a first aspect, a key detection circuit is provided, which comprises a voltage detection module, an I/O interface detection module, a selection module, and a first isolation module,
the voltage detection module is used for detecting voltage signals caused by different keys;
the I/O interface detection module is used for detecting high and low level sequence signals caused by different keys;
the selection module is used for switching and connecting the I/O interface detection module or the voltage detection module;
the first isolation module is used for isolating the selection module and the I/O interface detection module.
In some embodiments, the selection module includes a switching transistor having a gate receiving the selection control signal, a first pole coupled to the first isolation module, and a second pole coupled to the first power signal.
In some embodiments, the first isolation module includes a plurality of diodes, a first pole of each diode is connected to a first pole of a corresponding key, and a second pole of each diode is connected to the selection module.
In some embodiments, the voltage detection module includes a voltage dividing resistor, a detection node, a plurality of detection resistors, and a voltage detector, a first pole of the voltage dividing resistor is connected to the second power signal, a second pole of the voltage dividing resistor is connected to the detection node, a first pole of each detection resistor is connected to the detection node, a second pole of each detection resistor is connected to a second pole of the corresponding key, and the voltage detector detects a voltage of the detection node.
In some embodiments, the detection resistors have different resistance values.
In some embodiments, the voltage detection module includes a voltage dividing resistor, a detection node, a plurality of detection resistors, and a voltage detector, a first pole of the voltage dividing resistor is connected to the second power signal, a second pole of the voltage dividing resistor is connected to the detection node, a first pole of each detection resistor is connected to the detection node, a second pole of each detection resistor is connected to a second pole of the corresponding key, and the voltage detector detects the voltage of the detection node; the selection control signal and the second power supply signal adopt the same signal.
In some embodiments, the I/O interface detection module includes an I/O interface detector connected to a first pole of the key and a second pole of the key connected to the third power signal.
In some embodiments, the touch key further comprises a second isolation module, wherein the second isolation module comprises a plurality of diodes, a first pole of each diode is connected with a second pole of the corresponding key, and a second pole of each diode is connected with the third power signal.
In some embodiments, the selection module comprises a switching transistor, a gate of the switching transistor receives the selection control signal, a first pole of the switching transistor is connected with the first isolation module, and a second pole of the switching transistor is connected with the first power supply signal;
the first isolation module comprises a plurality of diodes, the first pole of each diode is connected with the first pole of the corresponding key, and the second pole of each diode is connected with the selection module;
the voltage detection module comprises voltage division resistors, detection nodes, a plurality of detection resistors and a voltage detector, wherein the first poles of the voltage division resistors are connected with a second power signal, the second poles of the voltage division resistors are connected with the detection nodes, the first poles of the detection resistors are connected with the detection nodes, the second poles of the detection resistors are respectively connected with the second poles of the corresponding keys, and the voltage detector detects the voltage of the detection nodes;
the I/O interface detection module comprises an I/O interface detector, the I/O interface detector is connected with a first pole of the key, and a second pole of the key is connected with a third power supply signal;
the first isolation module comprises a plurality of diodes, the first pole of each diode is connected with the second pole of the corresponding key, and the second pole of each diode is connected with the third power supply signal.
In a second aspect, a detection method for a key detection circuit provided in various embodiments of the present application is provided, where the key detection circuit includes a voltage detection mode and an I/O interface detection mode,
when the voltage detection mode is selected, the control signal and the second power supply signal are selected to be connected into a high level, the high level of the third power supply signal is cut off, the voltage detection module works, and the voltage of the detection node is detected through the voltage detector to determine the state of the key;
when the voltage detection mode is selected, the third power supply signal is switched in high level, the high level of the selection control signal and the high level of the second power supply signal are cut off, the I/O interface detection circuit works, and different high-low level sequences are detected through the I/O interface detector to determine the key state.
According to the technical scheme provided by the embodiment of the application, the key detection circuit capable of selecting between the I/O interface detection module and the voltage detection module is provided, so that heavy workload caused by the fact that two detection boards are used for voltage detection and I/O interface detection in the conventional key detection can be solved. Furthermore, according to some embodiments of the present application, by providing the first isolation module, interference of the selection module on the detection of the I/O interface can be solved, and an accurate detection result is obtained. In addition, according to some embodiments of the present application, by providing the second isolation module, the interference of the I/O interface detection module to the voltage detection can be solved, and an accurate detection result can be obtained.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1 shows an exemplary block diagram of a detection circuit according to an embodiment of the present application;
FIG. 2 illustrates an exemplary schematic diagram of a detection circuit according to an embodiment of the present application.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
The inventor finds that the key detection has the following problems: various keys of the display device are detected by an I/O interface detection or a voltage detection method. The voltage detection is to judge the key pressing state by detecting different voltages of the detection nodes after different keys are pressed. The I/O interface detection is to judge the key pressing state by detecting the high-low level sequence signal presented on the I/O pin after different keys are pressed. In actual detection, voltage detection and I/O interface detection respectively adopt respective detection circuits, and when two detection plates need to be switched back and forth for detection, workload is increased and personnel waste is caused.
In order to solve the above problems, the present application provides a key detection circuit supporting voltage detection and I/O interface detection.
Referring to fig. 1, fig. 1 is a block diagram of a key detection circuit according to an embodiment of the present disclosure. A key detection circuit comprises a voltage detection module 101, an I/O interface detection module 102, a selection module 103 and a first isolation module 104, wherein,
the voltage detection module 101 is used for detecting voltage signals caused by different keys;
the I/O interface detection module 102 is configured to detect high and low level sequence signals caused by different keys;
the selection module 103 is used for switching and connecting the I/O interface detection module or the voltage detection module;
the first isolation module 104 is used to isolate the selection module and the I/O interface detection module.
By integrating the voltage detection circuit and the I/O interface detection circuit, the respective use of the voltage detection and the I/O key detection modes can be realized, the applicable scene of the key circuit is increased, and the development cost of key board detection is also reduced.
Fig. 2 is a schematic diagram of a key detection circuit according to an embodiment of the present application. The selection module comprises a switch transistor T1 and a pull-down resistor R8, wherein the grid of the switch transistor T1 receives a selection control signal EN, the first pole is connected with the first isolation module 104, and the second pole is connected with the first power supply signal GND; the pull-down resistor R8 has a first pole connected to the gate of the switching transistor T1 and a second pole connected to the first power signal GND.
It should be noted that the current limiting resistor R7 is set according to the characteristics of the switching transistor used, and the resistance of the current limiting resistor R7 is usually smaller than that of the pull-down resistor R8. When the switch transistor needs to limit the current, the current limiting resistor R7 is arranged, otherwise, the current limiting resistor R7 is not arranged. For example, when a MOS transistor is used as the switching transistor, the current limiting resistor R7 may not be provided. The key detection circuit can be controlled to adopt a voltage detection mode or an I/O interface detection mode according to the selection control signal EN. The first power signal GND may be a ground signal. When the selection control signal EN is switched on the high potential signal, the gate is switched on the high potential to make the switching transistor T1 turned on; when the selection control signal EN turns off the high-potential signal, the gate potential is low due to the pull-down resistor R8, and the switching transistor T1 is turned off.
In some embodiments, the first isolation module 104 includes a plurality of diodes D2-D5, each having a first pole connected to the first pole of the corresponding key and a second pole connected to the selection module 103.
As shown in fig. 2, the first isolation module is not disposed between the keys R2-R5, and the first poles of the keys detected by the I/O detector will be the same, so it is necessary to dispose the first isolation module between the selection module 103 and the I/O detection pin, i.e., the first pole of the key, to isolate the interference with the detection of the I/O interface.
The diode has unidirectional conductivity, so that the interference of the first pole of the switch transistor on the detection of the I/O interface can be isolated, and the detection error caused by the same level detected by the I/O detector can be avoided.
In some embodiments, the voltage detection module 101 includes a voltage dividing resistor R1, a detection node N, a plurality of detection resistors R2 to R5, and a voltage detector, wherein a first pole of the voltage dividing resistor R1 is connected to the second power signal PWER _ ADC, a second pole of the voltage dividing resistor R2 is connected to the detection node N, a first pole of each detection resistor is connected to the detection node N, a second pole of each detection resistor is connected to a second pole of the corresponding key, and the voltage detector detects the voltage at the detection node N.
Wherein, each detection resistor adopts different resistance values.
When different keys are pressed, different detection resistors participate in voltage division, so that the voltages of the detection nodes N are different. The different voltages detected by the voltage detector can determine which key has been pressed. The voltage detector can be realized by an ADC module of an SOC chip, and the SOC chip with the model number RK3399 can be adopted.
Specifically, when the key K2 is closed, the voltage dividing resistor R1 and the detection resistor R2 divide the voltage of the second power signal PWER _ ADC, and at this time, the voltage value of the detection node N is R2 ÷ (R1+ R2) × PWER _ ADC; when the key K3 is closed, the voltage dividing resistor R1 and the detection resistor R3 divide the voltage of the second power signal PWER _ ADC, and at this time, the voltage value of the detection node N is R3 ÷ (R1+ R3) × PWER _ ADC. Similarly, when the voltage values of the detection nodes N are R4 ÷ (R1+ R4) × PWER _ ADC and R5 ÷ (R1+ R5) × PWER _ ADC, respectively, when the voltages of K4 and K5 are closed, respectively. When a plurality of keys are pressed simultaneously, the corresponding detection resistors are connected in parallel and participate in voltage division. For example, when the keys K2 and K3 are closed, the detection resistors R2 and R3 are connected in parallel and then divided by voltage dividing resistors. Similarly, when the keys K2, K3 and K4 are closed, the detection resistors R2, R3 and R4 are connected in parallel and then are subjected to voltage division with the voltage division resistor. Therefore, the voltage of the detection node will be different corresponding to the pressing of different keys. Here, no one for each case is analyzed.
In some embodiments, the I/O interface detection module includes an I/O interface detector, the I/O interface detector is connected to a first pole of the key, and a second pole of the key is connected to the third POWER signal POWER _ I/O. At this time, when different keys are pressed, the high and low levels received by the I/O interface detector will be different. The third power supply signal is high level, and when the key K2 is pressed, the sequence of high and low levels received by the I/O interface detector is 1000; when the key K3 is pressed, the high-low level sequence received by the I/O interface detector is 0100; when the keys K2 and K3 are pressed, the sequence of high and low levels received by the I/O interface detector is 1100. It can be understood that the I/O interface corresponding to the pressed key will become high level, so that the pressed state of each key can be determined through the high-low level sequence received by the I/O interface detector. The I/O interface detector can be a single chip microcomputer or an SOC chip. Voltage detection and I/O detection may be implemented using one SOC chip, for example, using the RK3399 chip. It should be noted that, in this embodiment, only 4 keys are given, and any number of keys may be used according to the detected key.
In some embodiments, the second isolation module 105 further includes a plurality of diodes D6-D9, a first pole of each diode is connected to a second pole of the corresponding key, and a second pole of each diode is connected to the third POWER signal POWER _ I/O. Therefore, the interference of the I/O interface detection module on the ADC detection is isolated. If the second isolation module 105 is not arranged, the second poles of the keys are interconnected, so that the detection circuits are connected in parallel, the voltage values of the detection nodes are the same, and detection errors are caused.
In addition, in order to save the number of signals, the selection control signal and the second power supply signal adopt the same signal.
Next, the operation of the entire key detection circuit of fig. 2 will be described.
When the POWER _ ADC and the selection control signal EN access the high level signal and cut off the high level signal of the POWER _ I/O, the switching transistor T1 is turned on, the voltage detection module works, the POWER _ ADC level signal is divided by the voltage dividing resistor and the detection resistor according to the key pressing, and the corresponding voltage is obtained at the detection node N, so that the key pressing condition is judged.
When POWER _ I/O is switched on and switched off, POWER _ ADC and the selection control signal EN are switched on and switched off, the switching transistor T1 is turned off, the I/O interface detection module operates, and according to the key press, the I/O interface detector receives the corresponding high-low level sequence signal, thereby determining the key press condition.
The present application further provides a detection method for a key detection circuit provided in the embodiments of the present application, the key detection circuit includes a voltage detection mode and an I/O interface detection mode,
when the voltage detection mode needs to be selected, the control signal and the second power supply signal are selected to be connected into a high level, the third power supply signal cuts off the high level, the voltage detection module works, and the voltage of the detection node is detected through the voltage detector to determine the key state;
when the voltage detection mode needs to be selected, the third power supply signal is connected with a high level, the selection control signal and the second power supply signal are switched off the high level, the I/O interface detection circuit works, and different high-low level sequences are detected through the I/O interface detector to determine the key state.
The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims (10)

1. A key detection circuit is characterized by comprising a voltage detection module, an I/O interface detection module, a selection module and a first isolation module, wherein,
the voltage detection module is used for detecting voltage signals caused by different keys;
the I/O interface detection module is used for detecting high and low level sequence signals caused by different keys;
the selection module is used for switching and connecting the I/O interface detection module or the voltage detection module;
the first isolation module is used for isolating the selection module and the I/O interface detection module.
2. The key detection circuit of claim 1, wherein the selection module comprises a switching transistor and a pull-down resistor,
the grid electrode of the switch transistor receives a selection control signal, the first pole of the switch transistor is connected with the first isolation module, and the second pole of the switch transistor is connected with a first power supply signal;
the first pole of the pull-down resistor is connected with the grid of the switch transistor, and the second pole of the pull-down resistor is connected with a first power supply signal.
3. The key detection circuit of claim 1, wherein the first isolation module comprises a plurality of diodes, a first pole of each diode being coupled to a first pole of a corresponding key, and a second pole of each diode being coupled to the selection module.
4. The key detection circuit of claim 1, wherein the voltage detection module comprises a voltage dividing resistor, a detection node, a plurality of detection resistors, and a voltage detector, wherein a first pole of the voltage dividing resistor is connected to a second power signal, a second pole of the voltage dividing resistor is connected to the detection node, a first pole of each detection resistor is connected to the detection node, a second pole of each detection resistor is connected to a second pole of a corresponding key, and the voltage detector detects a voltage of the detection node.
5. The key detection circuit of claim 4, wherein each of the detection resistors has a resistance value different from each other.
6. The key detection circuit of claim 2,
the voltage detection module comprises a divider resistor, detection nodes, a plurality of detection resistors and a voltage detector, wherein a first pole of the divider resistor is connected with a second power signal, a second pole of the divider resistor is connected with the detection nodes, a first pole of each detection resistor is connected with the detection nodes, the second pole of each detection resistor is respectively connected with a second pole of a corresponding key, and the voltage detector detects the voltage of the detection nodes;
the selection control signal and the second power supply signal adopt the same signal.
7. The key detection circuit of claim 1, wherein the I/O interface detection module comprises an I/O interface detector, the I/O interface detector is coupled to a first pole of the key, and a second pole of the key is coupled to a third power signal.
8. The key detection circuit according to any of claims 1-7, further comprising a second isolation module, wherein the second isolation module comprises a plurality of diodes, wherein a first pole of each of the diodes is connected to a second pole of a corresponding key, and a second pole of each of the diodes is connected to the third power signal.
9. The key detection circuit of claim 1, wherein the selection module comprises a switching transistor, a gate of the switching transistor receives a selection control signal, a first pole of the switching transistor is connected to the first isolation module, and a second pole of the switching transistor is connected to a first power signal;
the first isolation module comprises a plurality of diodes, a first pole of each diode is connected with a first pole of a corresponding key, and a second pole of each diode is connected with the selection module;
the voltage detection module comprises a divider resistor, detection nodes, a plurality of detection resistors and a voltage detector, wherein a first pole of the divider resistor is connected with a second power signal, a second pole of the divider resistor is connected with the detection nodes, a first pole of each detection resistor is connected with the detection nodes, the second pole of each detection resistor is respectively connected with a second pole of a corresponding key, and the voltage detector detects the voltage of the detection nodes;
the I/O interface detection module comprises an I/O interface detector, the I/O interface detector is connected with a first pole of the key, and a second pole of the key is connected with a third power supply signal;
the second isolation module comprises a plurality of diodes, the first pole of each diode is connected with the second pole of the corresponding key, and the second pole of each diode is connected with the third power supply signal.
10. A detection method for the key detection circuit according to any one of claims 1 to 9, wherein the key detection circuit comprises a voltage detection mode and an I/O interface detection mode,
when a voltage detection mode is selected, the selection control signal and the second power supply signal are connected into a high level, the high level of a third power supply signal is cut off, the voltage detection module works, and the voltage of the detection node is detected by the voltage detector to determine the pressing state of each key;
when the voltage detection mode is selected, the third power supply signal is switched in a high level, the high level of the selection control signal and the high level of the second power supply signal are cut off, the I/O interface detection circuit works, and different high-low level sequences are detected by the I/O interface detector to determine the pressing state of each key.
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