CN111725205B - ESD protection device with diagonal bidirectional SCR structure - Google Patents
ESD protection device with diagonal bidirectional SCR structure Download PDFInfo
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- CN111725205B CN111725205B CN201910650593.9A CN201910650593A CN111725205B CN 111725205 B CN111725205 B CN 111725205B CN 201910650593 A CN201910650593 A CN 201910650593A CN 111725205 B CN111725205 B CN 111725205B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
Abstract
The invention relates to an ESD protection device with a diagonal bidirectional SCR structure, which comprises an N well and a P well, wherein the N well and the P well are adjacently arranged; forming a T1 port through the second P+ injection region and the second N+ injection region, forming a T2 port through the first P+ injection region and the first N+ injection region, forming an SCR1 passage through the second P+ injection region, the N well, the P well and the first N+ injection region, and forming an SCR2 passage through the first P+ injection region, the N well, the P well and the second N+ injection region; the SCR1 and the SCR2 are in diagonal structures, so that protection is provided for pulses of chips in all directions, bidirectional protection of a single device to an input/output port is realized, the number of components required by a complete ESD protection circuit is reduced, the layout area is greatly reduced, the corresponding parasitic effect is reduced, and in addition, for circuits with output signal amplitude higher than power supply voltage or lower than ground voltage, no leakage occurs due to the existence of reverse bias PN junctions.
Description
Technical Field
The present invention relates to the field of electrostatic discharge protection of integrated circuits, and in particular, to an ESD protection device with a diagonal bidirectional SCR structure.
Background
The electrostatic discharge (Electrostatic Discharge, ESD for short) phenomenon is the most important reliability problem for causing the failure of integrated circuit products, improves the reliability of ESD protection in integrated circuits, and has non-negligible effects on improving yield and driving industry economic development.
Integrated circuit ESD protection devices include resistors, diodes, transistors, grounded gate mosfet, gate-coupled mosfet, silicon Controlled Rectifier (SCR), and the like. Among the many ESD protection devices, the SCR device will be a popular device for ESD protection of the nanoscale integrated circuit because the SCR structure forms a positive feedback mechanism with the parasitic BJT inside after being turned on, and thus has a stronger current discharge capability on the same area.
CMOS circuits employ SOI substrates for lower power consumption, higher speed and integration, better radiation resistance, etc. The conventional SOI SCR structure is shown in FIG. 1, wherein an N+ injection region and a P+ injection region are respectively arranged in an N well and a P well, the two injection regions in the N well are connected with an anode, and the two injection regions in the P well are connected with a cathode; fig. 2 is an equivalent circuit of the parasitic structure inside the SCR device. Only when the anode performs positive ESD impact to the cathode, the parasitic NPN tube and the PNP tube are conducted, the two parasitic transistors form a positive feedback structure, the SCR starts to release large current generated by ESD, the current release path is a P+ injection region, an N well, a P well and an N+ injection region, and when the anode performs negative ESD impact to the cathode, the parasitic diode in the structure is used for completing, so that the SOI SCR with the traditional structure can only realize unidirectional protection.
As shown in fig. 3, when the conventional SOI SCR protection circuit is used, only negative ESD pulse protection (ND) of I/O to power supply positive electrode Vdd and positive ESD pulse Protection (PS) of I/O to power supply negative electrode (Vss) can be realized, and negative ESD pulse protection (NS) of I/O to Vss and positive ESD pulse Protection (PD) of I/O to Vdd are completed by parasitic diodes in the structure thereof, and when the amplitude of the output signal is required to be higher than the power supply voltage or lower than the ground voltage, the parasitic diodes are turned on, resulting in leakage, thereby affecting the normal operation of the internal circuit.
The traditional SCR device and other ESD protection devices are unidirectional, so that the protection cannot be provided for pulse paths of the chip in all directions, and electric leakage is easy to generate. Therefore, the problems of large layout area, large parasitic parameter introduction and the like caused by the doubling of devices required to realize bidirectional ESD protection by using the traditional SCR device are caused.
Disclosure of Invention
The invention aims to solve the technical problems that the traditional unidirectional SCR device can not provide a protection passage for the pulse of the chip in all directions and is easy to generate electric leakage.
In order to solve the technical problems, the invention discloses an ESD protection device with a diagonal bidirectional SCR structure, which comprises an N well and a P well, wherein the N well and the P well are adjacently arranged;
a first P+ injection region, a third N+ injection region and a second P+ injection region are sequentially arranged in the N well;
a first N+ injection region, a third P+ injection region and a second N+ injection region are sequentially arranged in the P well;
the first P+ injection region and the first N+ injection region are symmetrically arranged about the boundary line of the N well and the P well, and the first P+ injection region and the first N+ injection region form a T2 port;
the second P+ injection region and the second N+ injection region are symmetrically arranged about the boundary line between the N well and the P well, and the second P+ injection region and the second N+ injection region form a T1 port.
Further, the T1 port is used for being connected with an input or output port of the protected integrated circuit chip, and the T2 port is used for being connected with a positive power supply electrode or a negative power supply electrode of the chip;
or, the T2 port is used for being connected with an input or output port of the protected integrated circuit chip, and the T1 is used for being connected with a positive power supply electrode or a negative power supply electrode of the chip.
Further, from the T1 port to the T2 port, an ESD current drain path SCR1 is formed by sequentially passing through the N well, the P well, and the first n+ injection region from the second p+ injection region.
Further, from the T2 port to the T1 port, an ESD current drain path SCR2 is formed by sequentially passing through the N well, the P well, and the second n+ injection region from the first p+ injection region.
Further, the SCR1 and the SCR2 have the same path length and have a diagonal structure.
Further, the third p+ injection region forms a trigger point G1 for connecting with the first trigger circuit, and the third n+ injection region forms a trigger point G2 for connecting with the second trigger circuit.
Further, the first trigger circuit or the second trigger circuit includes at least one of a diode, a GGMOS, or an RC trigger network.
Further, the second p+ implantation region, the N-well and the first p+ implantation region form a BJT1 via.
Further, the first n+ implantation region, the P-well and the second n+ implantation region form a BJT2 path.
Further, the SCR1 and the BJT1 cooperate to bleed current; or, the SCR2 and the BJT2 cooperate to bleed current.
By adopting the technical scheme, the ESD protection device with the diagonal bidirectional SCR structure has the following beneficial effects:
the bidirectional SOI SCR protection structure comprises an N well and a P well, wherein the N well and the P well are adjacently arranged; forming a T1 port through the second P+ injection region and the second N+ injection region, forming a T2 port through the first P+ injection region and the first N+ injection region, forming an SCR1 passage through the second P+ injection region, the N well, the P well and the first N+ injection region, and forming an SCR2 passage through the first P+ injection region, the N well, the P well and the second N+ injection region; the SCR1 and the SCR2 are in diagonal structures, so that protection is provided for pulses of chips in all directions, bidirectional protection of a single device to an input/output port is realized, the number of components required by a complete ESD protection circuit is reduced, the layout area is greatly reduced, the corresponding parasitic effect is reduced, and in addition, for circuits with output signal amplitude higher than power supply voltage or lower than ground voltage, no leakage occurs due to the existence of reverse bias PN junctions.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a longitudinal cross-sectional view of a conventional SOI SCR device;
FIG. 2 is a conventional SCR equivalent circuit;
FIG. 3 is a schematic diagram of a parasitic diode of a substrate of a conventional SOI SCR device;
FIG. 4 shows an ESD protection device with a diagonal bi-directional SCR structure according to an embodiment of the present invention;
the following supplementary explanation is given to the accompanying drawings:
1-N well; 101-a first p+ implant region; 102-a second p+ implant region; 103-a third n+ implant region;
2-P well; 201-a first n+ implant region; 202-a second n+ implant region; 203-third P + implant region.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the invention. In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "top", "bottom", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may include one or more of the feature, either explicitly or implicitly. Moreover, the terms "first," "second," and the like, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein.
Example 1:
as shown in fig. 4, an ESD protection device of a diagonal bidirectional SCR structure includes an N-well 1 and a P-well 2, the N-well 1 and the P-well 2 being adjacently disposed;
a first p+ injection region 101, a third n+ injection region 103 and a second p+ injection region 102 are sequentially arranged in the N well 1;
a first n+ injection region 201, a third p+ injection region 203 and a second n+ injection region 202 are sequentially arranged in the P well 2;
the first p+ injection region 101 and the first n+ injection region 201 are symmetrically arranged about the boundary line between the N well 1 and the P well 2, and the first p+ injection region 101 and the first n+ injection region 201 form a T2 port;
the second p+ implantation region 102 and the second n+ implantation region 202 are symmetrically disposed about the boundary line between the N well 1 and the P well 2, and the second p+ implantation region 102 and the second n+ implantation region 202 form a T1 port.
In this embodiment, the T1 port is used to connect to an input or output port of the protected integrated circuit chip, and the T2 port is used to connect to a positive power supply or a negative power supply of the chip;
in other embodiments of the invention, the T2 port may also be used to connect to an input or output port of a protected integrated circuit chip, and the T1 port may also be used to connect to a positive power supply or a negative power supply of the chip.
From the T1 port to the T2 port, an ESD current drain path SCR1 is defined by the second p+ injection region 102 passing through the N well 1, the P well 2 and the first n+ injection region 201 in sequence.
From the T2 port to the T1 port, an ESD current drain path SCR2 is defined by the first p+ injection region 101 passing through the N well 1, the P well 2 and the second n+ injection region 202 in sequence.
The SCR1 and the SCR2 have the same passage length and are in a diagonal structure.
The second p+ implantation region 102, the N-well 1 and the first p+ implantation region 101 form a BJT1 via.
The first n+ implantation region 201, the P-well 2 and the second n+ implantation region 202 form a BJT2 path.
Upon the arrival of an ESD pulse signal, the SCR1 and the BJT1 cooperate to bleed current, or the SCR2 and the BJT2 cooperate to bleed current.
As shown in fig. 4, the T1 port is connected to a signal I/O port, and the T2 port is connected to a power supply negative electrode (grounded). When the T1 carries out forward ESD impact to the T2 (PS mode), a reverse voltage is applied to a PN junction formed by the N well 1 and the P well 2, the electric field of a depletion region gradually reaches a critical breakdown electric field along with the continuous increase of the voltage, and finally avalanche breakdown occurs to the PN junction, a large number of holes generated by the avalanche breakdown flow to a T2 port at the lower left under the action of the electric field, and voltage drop is generated on the P well resistor, when the voltage drop is larger than 0.7V, a parasitic NPN tube is conducted, the current of the collector of the NPN tube is increased to cause the increase of the current of the base electrode of the PNP tube, so that the PNP tube is conducted, and a passage between an I/O port and a negative electrode of a power supply is formed from the T1 port at the upper right to the T2 port at the lower left (diagonal PNPN), namely the SCR1 passage is discharged, so that ESD impact current is discharged, and internal circuit damage is avoided;
when negative ESD impact is carried out on T1 to T2 (NS mode), a reverse voltage is applied to a PN junction formed by the N well 1 and the P well 2, the electric field of a depletion region gradually reaches a critical breakdown electric field along with the continuous increase of the voltage, avalanche breakdown finally occurs to the PN junction, a large number of holes generated by the avalanche breakdown flow to a T1 port at the right lower part under the action of the electric field, voltage drop is generated on a P well resistor, when the voltage drop is continuously increased and is greater than 0.7V, a parasitic NPN tube is conducted, the increase of collector current of the NPN tube can cause the increase of base current of the PNP tube, the PNP tube is conducted, and a passage between an I/O port and a power supply negative electrode is formed from a T2 port at the left upper part to a T1 port at the right lower part (diagonal PNPN), namely the SCR2 passage, so that ESD impact current is discharged;
taking the T1 port as an example, connecting the signal I/O port, connecting the T2 port as a power positive electrode, and discharging current through the SCR1 passage when the T1 performs forward ESD impact to the T2 (PD mode); when T1 makes a negative ESD surge to T2 (ND mode), current is discharged through the SCR2 path.
In one aspect of the ESD protection device with the diagonal bidirectional SCR structure of the present invention, a T1 port is formed by the second p+ injection region 102 and the second n+ injection region 202, a T2 port is formed by the first p+ injection region 101 and the first n+ injection region 201, an SCR1 path is formed by the second p+ injection region 102, the N well 1, the P well 2 and the first n+ injection region 201, and an SCR2 path is formed by the first p+ injection region 101, the N well 1, the P well 2 and the second n+ injection region 202; the SCR1 and the SCR2 are in diagonal structures, so that the protection is provided for the pulse of the chip in all directions; on the other hand, when the ESD pulse signal comes in, the BJT1 path, that is, the PNP transistor is turned on, is further formed between the second p+ injection region 102 and the first p+ injection region 101, and the SCR1 path and the BJT1 path act together to discharge the ESD current, thereby enhancing the robustness of the device.
The third p+ injection region 203 forms a trigger point G1 for connecting with a first trigger circuit, and the third n+ injection region 103 forms a trigger point G2 for connecting with a second trigger circuit.
The first trigger circuit or the second trigger circuit comprises at least one of a diode, a GGMOS or an RC trigger network.
The ESD protection device with the diagonal bidirectional SCR structure realizes bidirectional protection of a single device for an input/output port, reduces the number of components required by a complete ESD protection circuit, greatly reduces the layout area, reduces the corresponding parasitic effect, and in addition, for circuits with output signal amplitude higher than power supply voltage or lower than ground line voltage, no electric leakage can occur due to the existence of reverse bias PN junctions.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (7)
1. An ESD protection device of a diagonal bi-directional SCR structure, characterized by: the device comprises an N well (1) and a P well (2), wherein the N well (1) and the P well (2) are adjacently arranged;
a first P+ injection region (101), a third N+ injection region (103) and a second P+ injection region (102) are sequentially arranged in the N well (1);
a first N+ injection region (201), a third P+ injection region (203) and a second N+ injection region (202) are sequentially arranged in the P well (2);
the first P+ injection region (101) and the first N+ injection region (201) are symmetrically arranged about the boundary line between the N well (1) and the P well (2), and the first P+ injection region (101) and the first N+ injection region (201) form a T2 port;
the second P+ injection region (102) and the second N+ injection region (202) are symmetrically arranged about the boundary line between the N well (1) and the P well (2), and the second P+ injection region (102) and the second N+ injection region (202) form a T1 port;
the T1 port is used for being connected with an input or output port of the protected integrated circuit chip, and the T2 port is used for being connected with a positive power supply electrode or a negative power supply electrode of the chip;
or, the T2 port is used for being connected with an input or output port of the protected integrated circuit chip, and the T1 is used for being connected with a positive power supply electrode or a negative power supply electrode of the chip;
an ESD current drain path SCR1 from the T1 port to the T2 port is defined by the second p+ injection region (102) passing through the N-well (1), the P-well (2) and the first n+ injection region (201) in sequence;
from the T2 port to the T1 port, an ESD current bleed path SCR2 is defined by the first p+ injection region (101) passing through the N-well (1), the P-well (2) and the second n+ injection region (202) in sequence.
2. The device of claim 1, wherein:
the SCR1 and the SCR2 have the same passage length and are in a diagonal structure.
3. The device of claim 1, wherein: the third P+ injection region (203) forms a trigger point G1 for externally connecting with a first trigger circuit, and the third N+ injection region (103) forms a trigger point G2 for externally connecting with a second trigger circuit.
4. A device according to claim 3, characterized in that: the first trigger circuit or the second trigger circuit comprises at least one of a diode, a GGMOS or an RC trigger network.
5. The device of claim 1, wherein:
the second P+ injection region (102), the N well (1) and the first P+ injection region (101) form a BJT1 path.
6. The device of claim 5, wherein:
the first N+ injection region (201), the P well (2) and the second N+ injection region (202) form a BJT2 path.
7. The device of claim 6, wherein: the SCR1 and the BJT1 cooperate to bleed current; or, the SCR2 and the BJT2 cooperate to bleed current.
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| CN102437174A (en) * | 2011-11-29 | 2012-05-02 | 上海宏力半导体制造有限公司 | Silicon-controlled device |
| CN102544068A (en) * | 2012-03-09 | 2012-07-04 | 浙江大学 | Bidirectional controllable silicon device based on assistant triggering of PNP-type triodes |
| CN108899317A (en) * | 2018-07-09 | 2018-11-27 | 江南大学 | A kind of bidirectional transient voltage suppressor of diode string auxiliary triggering SCR |
| CN109841615A (en) * | 2019-02-26 | 2019-06-04 | 合肥奕斯伟集成电路有限公司 | A kind of overvoltage amplitude of oscillation electrostatic discharge protection component and circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6189964B2 (en) * | 2012-10-22 | 2017-08-30 | シーエスエムシー テクノロジーズ エフエイビー１ カンパニー リミテッド | Semiconductor device for ESD protection |
| US9130008B2 (en) * | 2013-01-31 | 2015-09-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Robust ESD protection with silicon-controlled rectifier |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102437174A (en) * | 2011-11-29 | 2012-05-02 | 上海宏力半导体制造有限公司 | Silicon-controlled device |
| CN102544068A (en) * | 2012-03-09 | 2012-07-04 | 浙江大学 | Bidirectional controllable silicon device based on assistant triggering of PNP-type triodes |
| CN108899317A (en) * | 2018-07-09 | 2018-11-27 | 江南大学 | A kind of bidirectional transient voltage suppressor of diode string auxiliary triggering SCR |
| CN109841615A (en) * | 2019-02-26 | 2019-06-04 | 合肥奕斯伟集成电路有限公司 | A kind of overvoltage amplitude of oscillation electrostatic discharge protection component and circuit |
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