CN111725204B

CN111725204B - ESD protection device with bidirectional SCR structure

Info

Publication number: CN111725204B
Application number: CN201910650174.5A
Authority: CN
Inventors: 周墨; 董业民; 单毅; 张振伟
Original assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Current assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Priority date: 2019-07-18
Filing date: 2019-07-18
Publication date: 2023-05-26
Anticipated expiration: 2039-07-18
Also published as: CN111725204A

Abstract

The invention relates to an ESD protection device with a bi-directional SCR structure, comprising: the first N well, the second N well, the P well and the polysilicon layer; the polysilicon layer is utilized for isolation, an SCR1 passage is formed by the first P+ injection region, the first N well, the P well and the second N+ injection region, and an SCR2 passage is formed by the third P+ injection region, the second N well, the P well and the fourth N+ injection region, the SCR1 passage and the SCR2 passage provide protection for pulses of the chip in all directions, the protection device realizes bidirectional ESD protection of a single device on an input/output port, the number of devices required by a complete ESD protection circuit is reduced, the layout area is greatly reduced, corresponding parasitic effects are reduced, and in addition, for circuits with output signal amplitude higher than power supply voltage or lower than ground voltage, electric leakage cannot occur due to reverse bias PN junctions.

Description

ESD protection device with bidirectional SCR structure

Technical Field

The present invention relates to the field of electrostatic discharge protection of integrated circuits, and in particular, to an ESD protection device with a bidirectional SCR structure.

Background

The electrostatic discharge (Electrostatic Discharge, ESD for short) phenomenon is the most important reliability problem for causing the failure of integrated circuit products, improves the reliability of ESD protection in integrated circuits, and has non-negligible effects on improving yield and driving industry economic development.

Integrated circuit ESD protection devices include resistors, diodes, transistors, grounded gate mosfet, gate-coupled mosfet, silicon Controlled Rectifier (SCR), and the like. Among the many ESD protection devices, the SCR device will be a popular device for ESD protection of the nanoscale integrated circuit because the SCR structure forms a positive feedback mechanism with the parasitic BJT inside after being turned on, and thus has a stronger current discharge capability on the same area.

CMOS circuits employ SOI substrates for lower power consumption, higher speed and integration, better radiation resistance, etc. The conventional SOI SCR structure is shown in FIG. 1, wherein an N+ injection region and a P+ injection region are respectively arranged in an N well and a P well, the two injection regions in the N well are connected with an anode, and the two injection regions in the P well are connected with a cathode; fig. 2 is an equivalent circuit of the parasitic structure inside the SCR device. Only when the anode performs positive ESD impact to the cathode, the parasitic NPN tube and the PNP tube are conducted, the two parasitic transistors form a positive feedback structure, the SCR starts to release large current generated by ESD, the current release path is a P+ injection region, an N well, a P well and an N+ injection region, and when the anode performs negative ESD impact to the cathode, the parasitic diode in the structure is used for completing, so that the SOI SCR with the traditional structure can only realize unidirectional protection.

As shown in fig. 3, when the conventional SOI SCR protection circuit is used, only negative ESD pulse protection (ND) of I/O to power supply positive electrode Vdd and positive ESD pulse Protection (PS) of I/O to power supply negative electrode (Vss) can be realized, and negative ESD pulse protection (NS) of I/O to Vss and positive ESD pulse Protection (PD) of I/O to Vdd are completed by parasitic diodes in the structure thereof, and when the amplitude of the output signal is required to be higher than the power supply voltage or lower than the ground voltage, the parasitic diodes are turned on, resulting in leakage, thereby affecting the normal operation of the internal circuit.

The traditional SCR device and other ESD protection devices are unidirectional, so that the protection cannot be provided for pulse paths of the chip in all directions, and electric leakage is easy to generate. Therefore, the problems of large layout area, large parasitic parameter introduction and the like caused by the doubling of devices required to realize bidirectional ESD protection by using the traditional SCR device are caused.

Disclosure of Invention

The invention aims to solve the technical problems that the traditional unidirectional SCR device can not provide a protection passage for the pulse of the chip in all directions and is easy to generate electric leakage.

In order to solve the technical problems, the invention discloses an ESD protection device with a bidirectional SCR structure, comprising: the first N well, the second N well, the P well and the polysilicon layer;

the first N well is arranged on one side of the polycrystalline silicon layer, the second N well is arranged on the other side of the polycrystalline silicon layer, and the first N well and the second N well are respectively connected with the P well;

the first N well is internally provided with a first P+ injection region and a first N+ injection region, a second P+ injection region and a second N+ injection region are arranged in a region, connected with the first N well, of the P well, a third P+ injection region and a third N+ injection region are arranged in the second N well, and a fourth P+ injection region and a fourth N+ injection region are arranged in a region, connected with the second N well, of the P well.

Further, the first p+ implantation region and the fourth n+ implantation region form a T1 port, and the second n+ implantation region and the third p+ implantation region form a T2 port.

Further, the T1 port is used for being connected with an input or output port of the protected integrated circuit chip, and the T2 port is used for being connected with a positive power supply electrode or a negative power supply electrode of the chip;

or, the T2 port is used for being connected with an input or output port of the protected integrated circuit chip, and the T1 is used for being connected with a positive power supply electrode or a negative power supply electrode of the chip.

Further, from the T1 port to the T2 port, an ESD current drain path SCR1 is formed by sequentially passing through the first N well, the P well, and the second n+ injection region from the first p+ injection region.

Further, from the T2 port to the T1 port, an ESD current drain path SCR2 is that the third p+ injection region sequentially passes through the second N well, the P well, and the fourth n+ injection region.

Further, the SCR1 and the SCR2 have the same path length and have symmetrical structures.

Further, the second p+ injection region and the fourth p+ injection region form a trigger point G1 for connecting with the first trigger circuit.

Further, the first n+ injection region and the third n+ injection region form a trigger point G2 for connecting with a second trigger circuit.

Further, the first trigger circuit or the second trigger circuit includes at least one of a diode, a GGMOS, or an RC trigger network.

Further, the semiconductor device further comprises an oxygen burying layer, and the first N well, the second N well and the P well are all arranged above the oxygen burying layer.

By adopting the technical scheme, the ESD protection device has the following beneficial effects:

the ESD protection device with the bidirectional SCR structure comprises: the first N well, the second N well, the P well and the polysilicon layer; the polysilicon layer is utilized for isolation, an SCR1 passage is formed by the first P+ injection region, the first N well, the P well and the second N+ injection region, and an SCR2 passage is formed by the third P+ injection region, the second N well, the P well and the fourth N+ injection region, the SCR1 passage and the SCR2 passage provide protection for pulses of the chip in all directions.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a longitudinal cross-sectional view of a conventional SOI SCR device;

FIG. 2 is a conventional SCR equivalent circuit;

FIG. 3 is a schematic diagram of a parasitic diode of a substrate of a conventional SOI SCR device;

FIG. 4 shows an ESD protection device with a bi-directional SCR structure according to an embodiment of the present invention;

fig. 5 is an equivalent circuit diagram of an ESD protection device with bi-directional SCR structure according to an embodiment of the present invention;

fig. 6 is a schematic diagram of an ESD protection device with a bi-directional SCR structure externally connected to a first trigger circuit according to an embodiment of the present invention;

the following supplementary explanation is given to the accompanying drawings:

1-a first N-well; 101-a first p+ implant region; 102-a first n+ implant region;

2-a second N-well; 201-a third p+ implant region; 202-a third n+ implant region;

3-P well; 301-a second n+ implant region; 302-a second p+ implant region; 303-fourth n+ implant region; 304-a fourth p+ implant region;

4-polysilicon layer.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the invention. In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "top", "bottom", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may include one or more of the feature, either explicitly or implicitly. Moreover, the terms "first," "second," and the like, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein.

Example 1:

as shown in fig. 4, an ESD protection device having a bi-directional SCR structure includes: a first N well 1, a second N well 2, a P well 3 and a polysilicon layer 4;

the polysilicon layer 4 is arranged above the P well 3, the first N well 1 is arranged on one side of the polysilicon layer 4, the second N well 2 is arranged on the other side of the polysilicon layer 4, and the first N well 1 and the second N well 2 are respectively connected with the P well 3;

a first p+ injection region 101 and a first n+ injection region 102 are arranged in the first N well 1, a second p+ injection region 302 and a second n+ injection region 301 are arranged in a region where the P well 3 is connected with the first N well 1, a third p+ injection region 201 and a third n+ injection region 202 are arranged in the second N well 2, and a fourth p+ injection region 304 and a fourth n+ injection region 303 are arranged in a region where the P well 3 is connected with the second N well 2.

The first p+ implant region 101 and the fourth n+ implant region 303 form a T1 port, and the second n+ implant region 301 and the third p+ implant region 201 form a T2 port.

In this embodiment, the T1 port is used to connect to an input or output port of the protected integrated circuit chip, and the T2 port is used to connect to a positive power supply or a negative power supply of the chip.

From the T1 port to the T2 port, an ESD current drain path SCR1 is that the first p+ injection region 101 sequentially passes through the first N well 1, the P well 3, and the second n+ injection region 301.

From the T2 port to the T1 port, an ESD current drain path SCR2 is defined by the third p+ injection region 201 passing through the second N well 2, the P well 3 and the fourth n+ injection region 303 in sequence.

The SCR1 and the SCR2 have the same passage length and are symmetrical.

As shown in fig. 4, taking the signal I/O port connected to the T1 port and the power supply negative electrode (grounded) as an example, when the T1 performs forward ESD surge to the T2 (PS mode), a reverse voltage is applied to the PN junction formed by the first N-well 1 and the P-well 3, and as shown in fig. 5, the NPN (Q3) tube BC junction is reversely biased, the electric field of the depletion region gradually reaches the critical breakdown electric field as the voltage is continuously increased, eventually avalanche breakdown occurs to the PN junction, a large number of holes generated by avalanche breakdown flow to the T2 under the action of the electric field and generate a voltage drop on the P-well resistor, and as the voltage continues to increase, the parasitic Q3 tube is turned on, the increase of the collector current of the Q3 tube causes the increase of the base current of the PNP (Q2) tube, so that the PNP tube is turned on, and the Q2-Q3 tube (PNPN) forms a path between the I/O port and the power supply negative electrode, i.e., as shown in fig. 4, the SCR1 path is avoided, thereby discharging the ESD surge current and internal circuit damage;

when negative ESD impact is performed from T1 to T2 (NS mode), as shown in fig. 5, that is, the NPN (Q1) tube BC junction is reversely biased, as the voltage is continuously increased, the electric field of the depletion region gradually reaches the critical breakdown electric field, and eventually avalanche breakdown occurs to the PN junction, a large number of holes generated by avalanche breakdown flow to T1 under the action of the electric field and generate voltage drop on the P-well resistor, as the voltage continues to increase, when the voltage drop is greater than 0.7V, the parasitic Q1 tube is turned on, the increase of the collector current of the Q1 tube causes the increase of the base current of the PNP (Q2) tube, so that the Q2 tube is turned on, and the Q2-Q1 tube (PNPN) forms a path between the power supply negative electrode and the I/O port, that is, the SCR2 path as shown in fig. 4, thereby discharging the ESD impact current.

Taking the T1 port as an example, connecting the signal I/O port, connecting the T2 port as a power positive electrode, and discharging current through the SCR1 passage when the T1 performs forward ESD impact to the T2 (PD mode); when T1 makes a negative ESD surge to T2 (ND mode), current is discharged through the SCR2 path.

In one aspect, the ESD protection device with the bidirectional SCR structure of the present invention uses the polysilicon layer 4 to perform isolation, and forms an SCR1 path through the first p+ injection region 101, the first N well 1, the P well 3 and the second n+ injection region 301, and forms an SCR2 path through the third p+ injection region 201, the second N well 2, the P well 3 and the fourth n+ injection region 303, where the SCR1 path and the SCR2 path provide protection for pulses of the chip in all directions; on the other hand, the polysilicon layer 4 can be instantaneously coupled to a certain voltage when an ESD pulse signal arrives, so that the P-well potential is raised, an inversion layer is formed below the polysilicon layer 4, a channel is generated, and the starting speed of the SCR structure is increased.

The second p+ implantation region 302 and the fourth p+ implantation region 304 form a first trigger point G1 for circumscribing a first trigger circuit.

The first n+ implant region 102 and the third n+ implant region 202 form a second trigger point G2 for circumscribing a second trigger circuit.

The first trigger circuit or the second trigger circuit comprises at least one of a diode, a GGMOS or an RC trigger network.

In this embodiment, as shown in fig. 6, the first trigger circuit includes two diodes connected in series, and when the forward ESD pulses are performed from T1 to T2, a current can be injected into the base of the NPN (Q3) tube, so that the voltage difference between the base and the emitter reaches 0.7V, the parasitic BJT is turned on rapidly and forms positive feedback, which accelerates the turn-on speed of the SCR and reduces the trigger voltage.

The ESD protection device with the bidirectional SCR structure is based on an SOI substrate, wherein the SOI substrate comprises an oxygen burying layer, and the first N well 1, the second N well 2 and the P well 3 are all arranged above the oxygen burying layer.

The ESD protection device realizes bidirectional protection of a single device for an input/output port, reduces the number of components required by a complete ESD protection circuit, greatly reduces the layout area, reduces the corresponding parasitic effect, and in addition, for circuits with output signal amplitude higher than power supply voltage or lower than ground line voltage, no electric leakage can occur due to the existence of reverse bias PN junctions.

The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims

1. An ESD protection device having a bi-directional SCR structure, comprising: the device comprises a first N well (1), a second N well (2), a P well (3) and a polycrystalline silicon layer (4);

the polysilicon layer (4) is arranged above the P-well (3), the first N-well (1) is arranged on one side of the polysilicon layer (4), the second N-well (2) is arranged on the other side of the polysilicon layer (4), and the first N-well (1) and the second N-well (2) are respectively connected with the P-well (3);

a first P+ injection region (101) and a first N+ injection region (102) are arranged in the first N well (1), a second P+ injection region (302) and a second N+ injection region (301) are arranged in a region connected with the first N well (1) by the P well (3), a third P+ injection region (201) and a third N+ injection region (202) are arranged in the second N well (2), and a fourth P+ injection region (304) and a fourth N+ injection region (303) are arranged in a region connected with the second N well (2) by the P well (3);

the first P+ injection region (101) and the fourth N+ injection region (303) form a T1 port, and the second N+ injection region (301) and the third P+ injection region (201) form a T2 port;

the T1 port is used for being connected with an input or output port of the protected integrated circuit chip, and the T2 port is used for being connected with a positive power supply electrode or a negative power supply electrode of the chip;

from the T1 port to the T2 port, an ESD current drain path SCR1 is formed by sequentially passing through the first N well (1), the P well (3) and the second n+ injection region (301) from the first p+ injection region (101).

2. The protection device of claim 1, wherein:

the T2 port is used for being connected with an input or output port of the protected integrated circuit chip, and the T1 port is used for being connected with a positive power supply electrode or a negative power supply electrode of the chip.

3. The protection device of claim 1, wherein:

from the T2 port to the T1 port, an ESD current drain path SCR2 is defined by the third p+ injection region (201) passing through the second N well (2), the P well (3) and the fourth n+ injection region (303) in order.

4. A protection device according to claim 3, characterized in that:

the SCR1 and the SCR2 have the same passage length and are symmetrical.

5. The protection device of claim 1, wherein:

the second P+ injection region (302) and the fourth P+ injection region (304) form a trigger point G1 for externally connecting a first trigger circuit.

6. The protection device of claim 5, wherein:

the first N+ injection region (102) and the third N+ injection region (202) form a trigger point G2 for externally connecting a second trigger circuit.

7. The protection device of claim 6, wherein:

8. The protection device of claim 1, wherein: the semiconductor device further comprises an oxygen burying layer, and the first N well (1), the second N well (2) and the P well (3) are all arranged above the oxygen burying layer.