CN111710721B - EDMOS device structure - Google Patents
EDMOS device structure Download PDFInfo
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- CN111710721B CN111710721B CN202010672175.2A CN202010672175A CN111710721B CN 111710721 B CN111710721 B CN 111710721B CN 202010672175 A CN202010672175 A CN 202010672175A CN 111710721 B CN111710721 B CN 111710721B
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- 210000000746 body region Anatomy 0.000 claims abstract description 20
- 230000005684 electric field Effects 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims description 30
- 239000002184 metal Substances 0.000 claims description 30
- 229910021332 silicide Inorganic materials 0.000 claims description 25
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 25
- 230000000903 blocking effect Effects 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 description 8
- 239000012535 impurity Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 206010010144 Completed suicide Diseases 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The application relates to the technical field of semiconductor manufacturing, in particular to an EDMOS device. An EDMOS device structure comprising: the semiconductor device comprises a semiconductor substrate, a first conductive type high-voltage well and a second conductive type high-voltage well, wherein the upper layer of the semiconductor substrate is doped to form the first conductive type high-voltage well; the lightly doped second conduction type drift region is positioned on the upper layer of the first conduction type high-voltage well; the first conduction type body region is positioned in the upper layer of the first conduction type high-voltage well and is adjacent to the lightly doped second conduction type drift region; a gate structure located on an adjacent interface of the first conductivity type body region and the lightly doped second conductivity type drift region; the drain electrode is positioned in the lightly doped second conduction type drift region and is far away from one side of the grid structure; and the control gate is arranged on the lightly doped second conduction type drift region, is positioned between the gate structure and the drain electrode and is used for dispersing the electric field distribution in the lightly doped second conduction type drift region. The EDMOS device structure can solve the problems that the on-resistance is high and the application requirement cannot be met in the related technology.
Description
Technical Field
The present disclosure relates to the field of Semiconductor manufacturing technologies, and in particular, to an EDMOS (Extended Drain Metal Oxide Semiconductor) device.
Background
As shown in fig. 1, an EDMOS generally includes: the high-voltage well region 110 is formed on an upper layer of the substrate, the drain lightly doped drift region 120 and the body region 130 are formed in the high-voltage well region 110, the gate structure 140 is formed on the substrate between the drain lightly doped drift region 120 and the body region 130, and side walls are formed on two sides of the gate structure 140 respectively. Forming a drain 150 in the drain lightly doped drift region 120 at one side of the gate structure 140; a source 160 is fabricated in the body region 130.
In the drain lightly doped drift region, an electric field is concentrated at the gate structure interface near one side of the drain, which is likely to cause device breakdown at the cross section, typically by forming a silicide blocking layer 170 between the drain and the gate structure, and fabricating a field plate structure on the silicide blocking layer (as shown in fig. 1), where the silicide blocking layer 170 extends from the drain to the gate structure along the drain lightly doped drift region and the sidewall surface.
For the EDMOS of the related art, the field plate structure can improve the breakdown voltage of the EDMOS to a certain extent, but the breakdown voltage and the on-resistance of the device are clamped with each other, so that the on-resistance in the related art is relatively high, and the application requirement cannot be met.
Disclosure of Invention
The application provides an EDMOS device structure, which can solve the problems that the on-resistance is higher and the breakdown voltage is lower in the related technology, and the application requirements can not be met.
The technical scheme of this application provides an EDMOS device structure, includes:
the semiconductor device comprises a semiconductor substrate, wherein an upper layer of the semiconductor substrate is doped to form a first conductive type high-voltage well;
the lightly doped second conduction type drift region is positioned on the upper layer of the first conduction type high-voltage well;
the first conduction type body region is positioned in the upper layer of the first conduction type high-voltage well and is adjacent to the lightly doped second conduction type drift region;
a gate structure located on an adjacent interface of the first conductivity type body region and the lightly doped second conductivity type drift region;
the drain electrode is positioned in the lightly doped second conduction type drift region and is far away from one side of the grid structure;
and the control gate is arranged on the lightly doped second conduction type drift region, is positioned between the gate structure and the drain electrode and is used for dispersing the electric field distribution in the lightly doped second conduction type drift region.
Optionally, the EDMOS device structure includes:
a metal silicide barrier layer is arranged between the grid structure and the drain electrode;
the metal silicide barrier layer extends from one side of the drain electrode close to the grid electrode structure to the side wall of the grid electrode structure close to the drain electrode.
Optionally, the metal silicide blocking layer covers a surface of the control gate.
Optionally, there are a plurality of control gates, and the control gates are laterally spaced apart.
Optionally, the control gate is applied with different voltages, so that the electric field distribution in the drift region of the second conductivity type forms multiple gradient changes in the lateral direction.
Optionally, a source is doped in the first conductivity type body region.
Optionally, the upper surfaces of the source electrode, the drain electrode and the gate electrode structure are covered with a metal silicide layer.
Optionally, a metal interconnection structure is connected to the metal silicide layer.
Optionally, isolation trenches are respectively disposed on one side of the lightly doped second conductivity type drift region away from the gate structure and one side of the first conductivity type body region away from the gate structure.
The technical scheme at least comprises the following advantages: the control gate is arranged on the lightly doped N-type drift region between the gate structure and the drain electrode, when voltage is applied to the control gate, the distribution of an electric field in the lightly doped N-type drift region is changed, the electric field is prevented from being concentrated on the interface of the gate structure, the breakdown voltage of the device is improved by dispersing the electric field in the lightly doped N-type drift region, and meanwhile, the device is ensured to have lower on-resistance.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of an EDMOS device structure provided in the related art;
FIG. 2 is a schematic diagram of an EDMOS device according to an embodiment of the present application;
FIG. 3 is a schematic diagram of the structure of an EDMOS device structure shown in FIG. 1 overlaid with a metal interconnect layer;
fig. 4 is a schematic structural diagram of an EDMOS device according to another embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, a fixed connection, a detachable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be connected through the inside of the two elements, or may be connected wirelessly or through a wire. The specific meaning of the above terms in this application will be understood to be a specific case for those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
The first conductivity type and the second conductivity type described in this application are opposite conductivity types. That is, the first and second conductivity types are N-type or P-type, and the second conductivity type is P-type when the first conductivity type is N-type, and conversely, the second conductivity type is N-type when the first conductivity type is P-type. Wherein, the silicon material is doped with impurities, and N-type impurity ions are element ions with valence electron of 5, such as arsenic; the P-type impurity ion is an element ion having a valence electron of 3, such as boron.
The following embodiments take the first conductive type as P-type and the second conductive type as N-type as examples for specific description, and the embodiments in which the first conductive type is N-type and the second conductive type is P-type are also included in the protection scope of the present application and are not described herein again.
Referring to fig. 2, an EDMOS device structure provided by an embodiment of the present application is schematically illustrated, the EDMOS device structure including:
a semiconductor substrate 210, wherein the upper layer of the semiconductor substrate 210 is doped to form a P-type high voltage well 220. The semiconductor substrate 210 may be a single crystal silicon wafer or other material suitable for use in the fabrication of integrated circuits.
A lightly doped N-type drift region 230, the lightly doped N-type drift region 230 being located in an upper layer of the N-type high voltage well.
A P-type body region 240, the P-type body region 240 being located in an upper layer of the P-type high voltage well 220 and adjacently interfacing with the lightly doped second conductivity type drift region. The steps of fabricating the P-type body region 240 and the lightly doped N-type drift region 230 are: p-type impurities and N-type impurities are implanted into the N-type high voltage well and diffused to form P-type body region 240 and N-type drift region adjacent to each other.
A gate structure 250, the gate structure 250 being located on an adjacent interface of the first conductivity type body region and the lightly doped second conductivity type drift region. The gate structure 250 includes a gate dielectric layer and a gate polysilicon layer stacked in sequence, and sidewalls are formed on both sides of the gate structure 250.
A drain 260, the drain 260 being located in the lightly doped N-type drift region 230, on a side away from the gate structure 250. That is, the gate structure 250 is located at one side of the lightly doped N-type drift region 230, and the drain 260 is located at the other side of the lightly doped N-type drift region 230.
A control gate 270, the control gate 270 being disposed on the lightly doped N-type drift region 230 between the gate structure 250 and the drain 260, for dispersing the electric field distribution in the lightly doped N-type drift region 230. The control gate 270 also includes a stacked structure of a gate dielectric layer and a polysilicon layer, and control gate 270 sidewalls disposed on both sides of the stacked structure.
It is known from the background art that, for the electric field distribution in the lightly doped N-type drift region 230, the electric field is mainly concentrated at the gate structure 250 interface near the drain 260 side, and the breakdown is likely to occur at this position because the field intensity at the gate structure 250 interface is larger due to the concentration of the electric field. By arranging the control gate 270 on the lightly doped N-type drift region 230 between the gate structure 250 and the drain 260, when a voltage is applied to the control gate 270, the distribution of the electric field in the lightly doped N-type drift region 230 changes, the electric field is prevented from being concentrated only on the interface of the gate structure 250, the breakdown voltage of the device is improved by dispersing the electric field in the lightly doped N-type drift region 230, and the device is ensured to have lower on-resistance.
In the fabrication of integrated circuits, the active region typically needs to be covered with a metal silicide for use in device contact metallization and device local interconnects to increase device speed and reduce device power consumption. However, in some regions, for example between the gate and the drain 260, a metal silicide cannot be formed in order to prevent device short, and thus these regions need to be protected by a metal silicide blocking layer 280 to prevent the formation of an undesired metal silicide.
To this end, a metal silicide blocking layer 280 is formed between the gate structure 250 and the drain 260, and the metal silicide blocking layer 280 covers and extends from one side of the drain 260 close to the gate structure 250 to the sidewall of the gate structure 250 close to the drain 260. In other words, on the lightly doped N-type drift region 230 between the gate structure 250 and the drain 260 shown in fig. 1, no metal silicide is desirably formed, and thus the formation of an undesired metal silicide is prevented by forming a metal silicide blocking layer 280 on this portion. The metal suicide formed extends from the boundary of the drain 260 near the gate structure 250 to the boundary of the gate structure 250 near the drain 260. The metal silicide covers: the sidewalls at the boundary of the gate structure 250 near the drain 260, the exposed upper surface of the lightly doped N-type drift region 230, and the surface of the control gate 270.
With continued reference to fig. 2, the P-type body regions 240 are doped to form a source 290.
The source 290, drain 260 and gate structure 250 are covered with a metal silicide layer on the upper surface.
Referring to fig. 3, which shows a schematic structural view of the EDMOS device structure shown in fig. 2 covering the metal interconnection layer 211, a metal interconnection structure 212 is formed in the metal interconnection layer 211, and the metal interconnection structure 212 extends downward to be connected with metal silicide layers respectively covering the upper surfaces of the source 290, the drain 260 and the gate structure 250, so as to form an electrical path.
As shown in any one of fig. 2 and 3, isolation trenches are respectively disposed on a side of the lightly doped N-type drift region 230 away from the gate structure 250 and a side of the P-type body region 240 away from the gate structure 250.
Referring to fig. 4, an EDMOS device structure provided in another embodiment of the present application is illustrated, where the EDMOS device is based on the EDMOS device structure illustrated in fig. 2 or fig. 3, and a plurality of control gates 270 are provided and laterally spaced apart from each other, where details of the EDMOS device structure illustrated in fig. 2 and fig. 3 are not repeated herein.
The plurality of control gates 270 may be laterally spaced apart, with the boundary position of the gate structure 250 near the drain 260 as a starting point, and the boundary position of the drain 260 near the gate structure 250 as an ending point, and the control gates 270 are laterally spaced apart.
Different voltages are applied to the control gate 270 so that the electric field distribution in the second conductive-type drift region forms multi-gradient variations in the lateral direction.
As shown in fig. 3, the control gates 270 include a first control gate 270 near the gate structure 250 and a second control gate 270 near the drain 260, and if the operating voltage of the device is VDD, the voltage applied to the first control gate 270 is 1/2VDD and the voltage applied to the second control gate 270 is VDD.
By arranging the control gates 270 at intervals on the lightly doped N-type drift region 230 between the gate structure 250 and the drain 260, when voltages are applied to the control gates 270, the electric field distribution in the lightly doped N-type drift region 230 forms multi-gradient change in the lateral direction, so that the electric field is prevented from being concentrated only on the interface of the gate structure 250, the breakdown voltage of the device is improved by dispersing the electric field in the lightly doped N-type drift region 230, and the device is ensured to have lower on-resistance.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (7)
1. An EDMOS device structure, comprising:
the semiconductor device comprises a semiconductor substrate, a first conductive type high-voltage well and a second conductive type high-voltage well, wherein the upper layer of the semiconductor substrate is doped to form the first conductive type high-voltage well;
the lightly doped second conduction type drift region is formed in the upper layer of the first conduction type high-voltage well;
a first conductive type body region formed in an upper layer of the first conductive type high voltage well and adjacent to the lightly doped second conductive type drift region;
the grid structure is formed on the adjacent interfaces of the first conduction type body region and the lightly doped second conduction type drift region;
the drain electrode is formed in the lightly doped second conduction type drift region and is far away from one side of the grid structure;
the control gate is arranged on the lightly doped second conduction type drift region, is positioned between the gate structure and the drain electrode and is used for dispersing the electric field distribution in the lightly doped second conduction type drift region;
the control gates are distributed at intervals laterally, and comprise a first control gate close to the gate structure and a second control gate close to the drain;
and the voltage applied to the first control gate is 1/2VDD, the voltage applied to the second control gate is VDD, and the VDD is a working voltage, so that the electric field distribution in the second conduction type drift region forms multi-gradient change in the transverse direction.
2. An EDMOS device structure as defined in claim 1, comprising:
a metal silicide barrier layer is arranged between the grid structure and the drain electrode;
the metal silicide blocking layer extends from one side of the drain electrode close to the grid electrode structure to the side wall of the grid electrode structure close to the drain electrode.
3. The EDMOS device structure of claim 2, wherein the metal silicide blocking layer covers a surface of the control gate.
4. The EDMOS device structure of claim 1, wherein the first conductivity type body region is doped to form a source.
5. The EDMOS device structure of claim 4, wherein a metal silicide layer covers an upper surface of the source, drain and gate structures.
6. An EDMOS device structure as defined in claim 5, wherein metal interconnect structures are connected to the metal silicide layer.
7. An EDMOS device structure as defined in claim 1, wherein isolation trenches are respectively provided at a side of the lightly doped second conductivity type drift region remote from the gate structure and at a side of the first conductivity type body region remote from the gate structure.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010672175.2A CN111710721B (en) | 2020-07-14 | 2020-07-14 | EDMOS device structure |
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| CN202010672175.2A CN111710721B (en) | 2020-07-14 | 2020-07-14 | EDMOS device structure |
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| CN111710721B true CN111710721B (en) | 2022-10-28 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100301403A1 (en) * | 2009-05-29 | 2010-12-02 | Won Gi Min | Semiconductor device with multiple gates and doped regions and method of forming |
| US20110260247A1 (en) * | 2010-04-26 | 2011-10-27 | Hongning Yang | Ldmos transistors with a split gate |
| US20150236150A1 (en) * | 2014-02-19 | 2015-08-20 | United Microelectronics Corp. | Semiconductor device and operating method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100301403A1 (en) * | 2009-05-29 | 2010-12-02 | Won Gi Min | Semiconductor device with multiple gates and doped regions and method of forming |
| US20110260247A1 (en) * | 2010-04-26 | 2011-10-27 | Hongning Yang | Ldmos transistors with a split gate |
| US20150236150A1 (en) * | 2014-02-19 | 2015-08-20 | United Microelectronics Corp. | Semiconductor device and operating method thereof |
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