JP2007294556A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To further shorten a termination structure region and a transition region in a semiconductor device, having the termination structure region and the transition region, that is, to place a gate electrode only in an intrinsically necessary region, without elongating a total gate length more than needed. <P>SOLUTION: A trench embedded region 5, having an electrode 20 embedded in a trench slot 19, is provided in the transition region 2 between an active region 1 and the termination structure region 3. A first p-type bypass region 23 is provided along a sidewall and the bottom of the trench slot 19. A second bypass region 6, connected to both the first bypass region 23 and a source electrode 17, is provided on the side of the termination structure region 3 of the slot 19. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a vertical insulated gate semiconductor element for high power.

  Conventionally, as a vertical insulated gate semiconductor element for high power, an insulated gate field effect transistor (hereinafter referred to as MOSFET) and an insulated gate bipolar transistor (hereinafter referred to as IGBT) having a metal-oxide-semiconductor structure are known. It is. These semiconductor elements can be formed alone for high power output applications or as a structure connected in parallel for other high voltage output applications.

  In a semiconductor device having such a vertical semiconductor element, the PN junction is terminated on the main surface on the side where the MOS gate structure is formed (hereinafter referred to as the upper side) outside the active region where the main current flows. It is necessary to provide a planar type termination structure region. When this termination structure region is not provided, the curvature portion of the PN junction exists outside the active region. In this curvature portion, the electric field is more likely to be concentrated than the planar PN junction in the active region. Therefore, the outside of the active region has a higher electric field than the active region, and the critical electric field strength is reached before the active region, resulting in a lower breakdown voltage.

  In general, in a vertical device having a planar termination structure region, the upper electrode is smaller than the opposite electrode among the electrodes in contact with the semiconductor layer for flowing a main current. Therefore, current tends to concentrate on the end of the upper electrode. As a countermeasure, it is known to provide a region (hereinafter referred to as a transition region) that transitions from the active region to the termination structure region.

  As examples of the planar termination structure, a floating guard ring structure, a field plate structure, a RESURF structure, or the like, or a termination structure that combines them is known. Further, a structure in which trench grooves are connected in a loop shape in a planar termination structure region so as to eliminate the end face of the trench groove and prevent a decrease in breakdown voltage due to electric field concentration on the end face of the trench groove is known (for example, (See Patent Document 1).

  Also, a structure is known in which a P-type diffusion region deeper than the trench groove is provided to prevent a breakdown voltage drop due to electric field concentration on the end face of the trench groove (see, for example, Patent Document 2). In Patent Document 2, by providing an inactive cell region surrounding the active cell region and a termination region surrounding the inactive cell region, formation of a parasitic NPN transistor is prevented, and destruction due to current concentration is prevented. Such a structure is also disclosed.

  In the active region, an electrode connected to the emitter electrode is formed in the trench groove through the dielectric film, thereby forming a space charge region in the semiconductor substrate region, and the channel region and the semiconductor substrate region. A structure in which electric field concentration in a space charge region in a semiconductor substrate region is relaxed by coupling with a space charge region generated at a junction is known (see, for example, Patent Document 3). This known example increases the impurity concentration of the semiconductor substrate to such an extent that the on-resistance can be reduced while maintaining a high breakdown voltage.

  Also, a power MOS element having an edge termination structure that completely surrounds the active region is known (see, for example, Patent Document 4). The edge termination structure includes a portion of a termination trench having a conductive material insulated by an insulator at the edge opposite the source region, drain region, and channel region. The conductive material of the edge termination structure is conductively connected to the source region and the drain region through the connection hole, the upper surface metallization, and the connection hole.

  A first conductivity type semiconductor substrate; a second conductivity type epitaxial layer provided on the semiconductor substrate; and a first conductivity type first region extending from the upper surface of the epitaxial layer into the epitaxial layer; A second region extending from the upper surface of the epitaxial layer into the epitaxial layer so as to surround the first region and away from the first region; and from the upper surface of the epitaxial layer through the second region and the epitaxial layer Inclined sidewalls extending into the substrate, respective PN junctions formed between the first region and the second region and the epitaxial layer, and provided in the inclined sidewalls, And a thin implanted layer of a first conductivity type impurity that constitutes a low resistance path that electrically connects the region to the substrate, and controls the breakdown voltage characteristics between the first region and the second region Provided with means to And are semiconductor devices are known. The means for controlling the breakdown voltage characteristics includes a first junction termination extending region extending in the lateral direction from the first region toward the second region, and a first junction termination extending region from the second region. And a second junction terminal extension region extending in the lateral direction toward the surface (see, for example, Patent Document 5).

Further, a structure in which a trench is formed between a cell area where an N ⁺ emitter region is disposed and a non-cell area which is a region other than the cell area and a P base layer is separated is known (for example, Patent Documents). 6). A gate electrode is embedded in the trench. This known example can prevent holes from flowing from the non-cell area to the cell area, and can avoid the occurrence of a latch-up phenomenon.

JP 2001-168329 A (FIGS. 3 and 4) Japanese Patent Laying-Open No. 2005-19734 (FIGS. 9, 10, and 14) JP 2001-85688 A (FIGS. 9 and 18) Japanese translation of PCT publication No. 2003-515915 (see D in FIG. 4) JP-A-2-22869 JP 2001-168324 A (FIG. 3, paragraphs 0029 to 0032)

  However, in the case where the above-described inactive cell region is provided, there is a problem in that the on-resistance per unit area is increased because the inactive cell region is a region where the MOSFET does not operate. In addition, since the gate electrode is embedded in the trench groove sandwiched between the termination structure region and the inactive cell region via an insulating film, the total gate length becomes long and the capacity increases. There is a problem that the reliability of the system is impaired.

  In particular, a corner portion of the semiconductor device has a curved portion in a trench groove in which a gate electrode is embedded. The curvature portion and the region where the other trench grooves are formed in a straight line have a problem that the reliability of the gate is lowered because the growth rate of the insulating film is different. In addition, since it is necessary to provide a certain space or more in order to separate the gate electrode and the source electrode, there is a problem that an operation region of the transistor becomes narrow.

  The present invention provides a semiconductor device having a termination structure region and a transition region in order to eliminate the above-described problems caused by the prior art, and which can further shorten the termination structure region and the transition region. With the goal. The present invention also provides a semiconductor device having a termination structure region and a transition region, in which a gate electrode can be installed only in a region that is originally necessary without making the total gate length longer than necessary. The purpose is to do.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to a first aspect of the present invention is a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region. A drift region of a first conductivity type having a surface and a second main surface, a channel region of a second conductivity type selectively provided along the first main surface, and selectively provided in the channel region A first semiconductor region of a first conductivity type, a first electrode connected to both the first semiconductor region and the channel region, and provided along the channel region between the first semiconductor region and the drift region An active region having a gate insulating film and a gate electrode provided along the gate insulating film; and embedded in a trench groove reaching deeper than the channel region from the first main surface; and on the first electrode Connected A transition region having a second conductivity type bypass region provided along an electrode and a sidewall and a bottom of the trench groove; and a first conductivity type second provided along a second main surface of the drift region. A semiconductor region; a second electrode connected to the second semiconductor region; and a cut surface extending from the first main surface to the second main surface along an outer peripheral edge of the termination structure region. To do.

  According to a second aspect of the present invention, there is provided a semiconductor device having a first main surface and a second main surface in a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region. A drift region of a type, a channel region of a second conductivity type selectively provided along the first main surface, a first semiconductor region of a first conductivity type selectively provided in the channel region, A first electrode connected to both the first semiconductor region and the channel region, a gate insulating film provided along the channel region between the first semiconductor region and the drift region, and along the gate insulating film An active region having a gate electrode, an electrode embedded in a trench groove extending deeper than the channel region from the first main surface and connected to the first electrode, and a sidewall of the trench groove Oh A transition region having a second conductivity type bypass region provided along the bottom, a second conductivity type second semiconductor region provided along a second main surface of the drift region, and the second semiconductor A second electrode connected to the region; and a cut surface extending from the first main surface to the second main surface along an outer peripheral edge of the termination structure region.

  According to a third aspect of the present invention, there is provided a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region, the first conductive surface having a first main surface and a second main surface. A drift region of a type, a channel region of a second conductivity type selectively provided along the first main surface, a first semiconductor region of a first conductivity type selectively provided in the channel region, A first electrode connected to both the first semiconductor region and the channel region; a first trench groove adjacent to the first semiconductor region and penetrating from the first main surface through the channel region to the drift region; An active region having a gate insulating film provided along an inner peripheral surface, a gate electrode embedded in the first trench groove through the gate insulating film, and deeper than the channel region from the first main surface 2nd trench reaching to A transition region having an electrode embedded in and connected to the first electrode, and a second conductivity type bypass region provided along a sidewall and a bottom of the second trench groove, and a first region of the drift region A second semiconductor region of a first conductivity type provided along two main surfaces; a second electrode connected to the second semiconductor region; and the first main surface along an outer peripheral edge of a termination structure region. And a cut surface that reaches the second main surface.

  According to a fourth aspect of the present invention, there is provided a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region, the first conductive surface having a first main surface and a second main surface. A drift region of a type, a channel region of a second conductivity type selectively provided along the first main surface, a first semiconductor region of a first conductivity type selectively provided in the channel region, A first electrode connected to both the first semiconductor region and the channel region; a first trench groove adjacent to the first semiconductor region and penetrating from the first main surface through the channel region to the drift region; An active region having a gate insulating film provided along an inner peripheral surface, a gate electrode embedded in the first trench groove through the gate insulating film, and deeper than the channel region from the first main surface 2nd trench reaching to A transition region having an electrode embedded in and connected to the first electrode, and a second conductivity type bypass region provided along a sidewall and a bottom of the second trench groove, and a first region of the drift region A second conductive type second semiconductor region provided along two main surfaces; a second electrode connected to the second semiconductor region; and the first main surface along the outer periphery of a termination structure region. And a cut surface that reaches the second main surface.

  According to a fifth aspect of the present invention, in the semiconductor device according to the third or fourth aspect, the depth of the first trench groove and the depth of the second trench groove are the same. According to a sixth aspect of the present invention, in the semiconductor device according to any one of the first to fifth aspects, the impurity profile of the bypass region and the impurity profile of the channel region are the same. To do.

  A semiconductor device according to a seventh aspect of the invention is the semiconductor device according to any one of the first to fifth aspects, wherein a second conductivity type body region is selectively provided in the channel region, The impurity profile of the bypass region and the impurity profile of the body region are the same. According to an eighth aspect of the present invention, in the semiconductor device according to any one of the first to seventh aspects, the MOS gate structure of the active region is formed linearly.

  According to the present invention, the trench groove provided in the transition region prevents the minority carriers in the termination structure region from flowing into the active region, and pulls out the minority carriers from the bypass region, thereby turning off in the vicinity of the termination structure region. And avalanche destruction can be avoided. That is, by providing the trench groove in the transition region with a function as a current barrier and a voltage barrier, dynamic tolerance can be improved.

  In addition, by embedding an electrode inside the trench groove in the transition region and fixing the potential of the electrode to a potential different from the gate electrode, an area necessary for insulation from the gate potential is prevented while preventing an increase in the gate electrode area. Can be shortened or eliminated. Therefore, both high gate reliability and a narrow transition region can be realized simultaneously. Furthermore, by making the trench groove depth in the transition region the same as the trench groove depth in the active region, or by making the impurity profile in the bypass region the same as the impurity profile in the channel region or body region, the transition can be performed without adding a process. Since the structure of the region can be manufactured, the semiconductor manufacturing process can be simplified.

  Incidentally, the semiconductor device disclosed in Patent Document 3 increases the impurity concentration of the semiconductor substrate to such an extent that the on-resistance can be reduced. Therefore, it is necessary to form a trench groove over almost the entire surface of the active region, and to form an electrode in the trench groove via a dielectric film. On the other hand, the present invention forms a trench groove in the transition region between the active region and the termination structure region, and fills the trench groove with an electrode. The mechanism and structure are different.

  According to the semiconductor device of the present invention, the termination structure region and the transition region can be further shortened. In addition, the gate electrode can be provided only in a necessary region without making the total gate length longer than necessary.

  Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

Embodiment 1 FIG.
An example in which the present invention is applied to a 600 V planar gate MOSFET will be described. FIG. 1 is a diagram showing a planar layout on the first main surface side of the semiconductor device according to the first embodiment, in which an electrode, an insulating film, and the like formed on the first main surface are omitted. As shown in FIG. 1, the active region 1 is disposed in the central portion of the semiconductor device. The transition region 2 is arranged outside the active region 1 so as to surround the active region 1. The termination structure region 3 is disposed outside the transition region 2 so as to surround the transition region 2.

  In the transition region 2, a channel region 4, a trench buried region 5, and a bypass region 6 are arranged so as to go around the semiconductor chip in this order from the active region 1 to the termination structure region 3. At the corners of the four corners of the semiconductor chip, the trench buried region 5 is formed to be bent at a right angle with a curvature of about 200 μm. The outer peripheral edge of the termination structure region 3 is cut surfaces 7a and 7b extending from the first main surface to the second main surface of the semiconductor device. Although not shown, the termination structure region 3 is formed with a termination structure such as a field limiting ring.

  Although not shown, the active region 1 is formed with a source region, a channel region, a body region, and the like constituting a MOS gate structure. Although not particularly limited, for example, in the active region 1, a plurality of linearly formed MOS gate structures are arranged in parallel in a stripe shape. Here, it is assumed that each MOS gate structure extends in a direction perpendicular to the alternate long and short dash line A-A ′ in FIG. 1 (a direction parallel to the alternate long and short dash line B-B ′). A gate pad 8 is provided in the active region 1. For example, the gate pad 8 is made of metal.

Next, a cross-sectional configuration of the semiconductor device of First Embodiment will be described. FIGS. 2 and 3 are cross-sectional views taken along section lines AA ′ and BB ′ in FIG. 1, respectively. The configuration of the active region 1 is as follows. For example, the concentration and thickness of the N-type drift region 11 are about 2.5 × 10 ¹⁴ cm ⁻³ and about 50 μm, respectively. The P-type channel region 12 is selectively provided along the first main surface of the drift region 11. For example, the depth of the channel region 12 is about 3 μm. The source region 13 which is an N-type first semiconductor region is selectively provided in the channel region 12.

  The gate insulating film 14 is provided on the first main surface along the region of the channel region 12 between the source region 13 and the drift region 11. For example, the gate insulating film 14 is made of silicon oxide. The gate electrode 15 is provided along the gate insulating film 14. For example, the gate electrode 15 is made of highly doped polysilicon.

  A P-type body region 16 is selectively provided in the channel region 12. The source electrode 17 as the first electrode is connected to the source region 13 and is electrically connected to the channel region 12 through the body region 16. For example, the source electrode 17 is made of metal. The source electrode 17 and the gate electrode 15 are insulated by an interlayer insulating film 18. The above-described MOS gate structure is formed by a general DMOS (Double-Difused-MOS) process.

  The configuration of the transition region 2 is as follows. The conductivity type of channel region 4 and bypass region 6 is P-type. The channel region 4 and the bypass region 6 are selectively provided along the first main surface of the drift region 11. The width of the channel region 4 can be designed freely. The channel region 4 and the impurity profile may be the same as the channel region 12 in the active region 1 and the channel region 4 and 12 may be formed by the same process.

The depth of the bypass region 6 is shallower than the depth of the trench groove 19. The depth and impurity profile of the bypass region 6 may be the same as the depth and impurity profile of the channel region 12 of the active region 1, and the bypass region 6 may be formed by the same process as the channel region 12 of the active region 1. This is preferable because it is not necessary to add a step of forming the bypass region 6. For example, by implanting boron ions at a dose of about 2 × 10 ^{13 to} 2 × 10 ¹⁴ cm ⁻² and then performing heat treatment at 1100 ° C. for about 200 minutes, the channel region 12 and the bypass region of the active region 1 6 can be formed simultaneously.

  Alternatively, the depth and impurity profile of the bypass region 6 are made the same as the depth and impurity profile of the body region 16, that is, the body region 22 functions as the bypass region 6, and the body region 22 is processed in the same process as the body region 16. You may make it form. The trench buried region 5 has a configuration in which the trench 20 is filled with the electrode 20. Trench groove 19 is formed so as to reach deeper than channel region 4 of transition region 2 from the first main surface of drift region 11. For example, the width and depth of the trench groove 19 are about 1 μm and about 5 μm, respectively. For example, the electrode 20 is made of highly doped polysilicon.

  A P-type body region 21 is selectively provided in the channel region 4 of the transition region 2. The bypass region 6 is selectively provided with a P-type body region 22. A P-type bypass region 23 is provided along the side wall and bottom of the trench groove 19. For convenience, the bypass region 23 is referred to as a first bypass region 23, and the bypass region 6 provided along the first main surface of the transition region 2 is referred to as a second bypass region 6 in order to be distinguished from the first bypass region 23. The first bypass region 23 is connected to the second bypass region 6 and the channel region 4 of the transition region 2.

For example, the first bypass region 23 can be formed by forming the trench groove 19 using an oxide film mask for forming a trench groove and then performing oblique ion implantation of boron using the oxide film mask as an ion implantation mask. . At this time, the dose amount of boron ions is, for example, about 2 × 10 ¹³ cm ⁻² , the implantation angle of boron ions with respect to the normal direction of the first main surface is, for example, about ± 7 degrees, and the acceleration voltage is For example, 45 keV is appropriate. Moreover, after ion implantation, for example, thermal diffusion treatment is performed at 1100 ° C. for about 30 minutes.

  The electrode 20 in the trench 19 is connected to the source electrode 17. The source electrode 17 is electrically connected to the channel region 4 and the second bypass region 6 in the transition region 2 through the body regions 21 and 22.

  The configuration of the termination structure region 3 is as follows. The P-type field limiting ring 24 is selectively provided along the first main surface of the drift region 11 so as to go around the semiconductor chip. Field oxide films 25 and 26 are provided between the field limiting ring 24 and the transition region 2 and between the field limiting ring 24 and the cut surfaces 7a and 7b. Interlayer insulating films 27 and 28 are provided on the field oxide films 25 and 26.

  The field plate 29 is electrically connected to the field limiting ring 24 through a P-type body region 30. For example, the field plate 29 is made of metal. For example, the interlayer insulating films 18, 27, and 28 are made of BPSG (Borophospho Silicate Glass). The termination structure described above is formed by a general DMOS process.

The drain region 31, which is an N-type second semiconductor region, is provided along the second main surface of the drift region 11 across the active region 1, the transition region 2, and the termination structure region 3. For example, the concentration and thickness of the drain region 31 are about 2.0 × 10 ¹⁸ cm ⁻³ and 300 μm, respectively. The drain electrode 32 as the second electrode is electrically connected to the drain region 31. For example, the drain electrode 32 is made of metal.

Embodiment 2. FIG.
The second embodiment is a modification of the first embodiment. FIG. 4 is a diagram illustrating a main part of a planar layout on the first main surface side of the semiconductor device of the second embodiment, and is a diagram in which an electrode, an insulating film, and the like formed on the first main surface are omitted. . 5 and FIG. 6 are diagrams showing the configurations of cross sections taken along section lines CC ′ and DD ′ of FIG. 4, respectively. These cutting lines CC ′ and DD ′ correspond to the cutting lines AA ′ and BB ′ in FIG. 1, respectively. As shown in FIGS. 4 to 6, the second embodiment is different from the first embodiment in that the MOS gate structure in the active region 1 is a trench gate structure including a trench groove 41, a gate insulating film 42 and a gate electrode 43. 44.

  The trench 41 is adjacent to the source region 13 and reaches the drift region 11 through the channel region 12 from the first main surface of the semiconductor device. The gate insulating film 42 is provided along the inner peripheral surface of the trench groove 41. The gate electrode 43 is embedded in the trench groove 41 via the gate insulating film 42. The gate electrode 43 is insulated from the source electrode 17 by the interlayer insulating film 45. For example, the interlayer insulating film 45 is made of BPSG and is formed simultaneously with the other interlayer insulating films 27 and 28. Other configurations are the same as those of the first embodiment.

  For example, if the trench groove 41 in the active region 1 and the trench groove 19 in the transition region 2 have the same depth, and the gate insulating film 42 and the gate electrode 43 are made of silicon oxide and highly doped polysilicon, respectively, The trench gate structure 44 in 1 and the trench groove 19 in the transition region 2 and the electrode 20 therein can be formed by the same process. This is preferable because the structure of the transition region 2 can be formed without adding a new process.

  According to the first or second embodiment, since no MOS gate electrode is formed in the trench groove 19 in the transition region 2, no current path is formed in the on state. In addition, since the trench groove 19 in the transition region 2 functions as a current barrier, the current flow in the lateral direction can be limited. Therefore, it is possible to suppress the current from spreading from the active region 1 to the termination structure region 3. Further, at the time of turn-off, since the trench groove 19 in the transition region 2 functions as a potential barrier, the potential at the bottom of the trench groove 19 that rises due to the current flowing into the first bypass region 23 is generated by the current flowing into the channel region 4. The current can be prevented from flowing into the channel region 4 on the active region 1 side until the potential rise at the bottom of the groove 19 is exceeded.

  Therefore, dynamic (switching) tolerance can be improved. In addition, since the dynamic tolerance is improved by the trench groove 19 and the first bypass region 23 in the transition region 2, even if the second bypass region 6 is omitted, the same effect of improving the dynamic tolerance can be obtained. When the second bypass region 6 is omitted, the first bypass region 23 reaches the first main surface along the sidewall of the trench groove 19 on the side of the termination structure region 3 of the trench groove 19 in the transition region 2, and the source electrode 17 is connected.

  Here, as disclosed in Patent Document 2, when a diffusion layer deeper than the trench groove is formed, the function of the trench groove as a potential barrier is lost. Therefore, in that case, since the width of the channel region 4 on the active region 1 side needs to be widened, the width of the transition region 2 is widened, and the area of the active region 1 is correspondingly reduced. There is an inconvenience of inviting a rise.

  Further, according to the first or second embodiment, since the gate electrode is not embedded in the trench groove 19 in the transition region 2, the gate electrode is embedded in the trench groove 19 when the gate electrode is embedded. Since a region necessary for insulation between the gate electrode and the source electrode is unnecessary, the width of the transition region 2 can be reduced. Further, since it is not necessary to increase the MOS gate area, the reliability of the MOS gate is not impaired.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, in the embodiment, the configuration having the combination of the bypass region 6 and the bypass region 22 has been mainly described. However, in any embodiment, only the bypass region 6 or only the bypass region 22 is provided instead of this combination. It is good also as a structure. Moreover, the dimension, density | concentration, etc. which were described in embodiment are examples, and this invention is not limited to those values. The active region 1 and the termination structure region 3 can be freely configured. Furthermore, although each example mentioned above is an example of MOSFET, this invention is applicable also to IGBT. In the case of IGBT, the conductivity type of the second semiconductor region is P-type. Further, in each of the above-described examples, the first conductivity type is N-type and the second conductivity type is P-type. However, the present invention may be configured such that the first conductivity type is P-type and the second conductivity type is N-type. The same holds true.

  As described above, the semiconductor device according to the present invention is useful for a semiconductor device having an insulated gate structure, and is particularly suitable for a power MOSFET and an IGBT.

3 is a diagram showing a planar layout on the first main surface side in the first embodiment. FIG. It is a figure which shows the structure of the cross section in sectional line A-A 'of FIG. It is a figure which shows the structure of the cross section in the cutting line B-B 'of FIG. FIG. 10 is a diagram showing a main part of a planar layout on the first main surface side in the second embodiment. FIG. 5 is a diagram illustrating a cross-sectional configuration along a cutting line C-C ′ in FIG. 4. FIG. 5 is a diagram showing a cross-sectional configuration along a cutting line D-D ′ in FIG. 4.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Active region 2 Transition region 3 Termination structure region 6, 23 Bypass region 7a, 7b Cut surface 11 Drift region 4, 12 Channel region 13 First semiconductor region 14, 42 Gate insulating film 15, 43 Gate electrode 16, 21 Body region 17 First electrode 19, 41 Trench groove 20 Electrode 31 Second semiconductor region 32 Second electrode

Claims (8)

In a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region,
A first conductivity type drift region having a first main surface and a second main surface;
A second conductivity type channel region selectively provided along the first main surface; a first conductivity type first semiconductor region selectively provided in the channel region; the first semiconductor region; A first electrode connected to both of the channel regions; a gate insulating film provided along the channel region between the first semiconductor region and the drift region; and a gate electrode provided along the gate insulating film An active region having
The second conductivity type embedded in the trench groove reaching deeper than the channel region from the first main surface and connected to the first electrode, and the second conductivity type provided along the side wall and bottom of the trench groove A transition region having a bypass region of
A second semiconductor region of the first conductivity type provided along the second main surface of the drift region;
A second electrode connected to the second semiconductor region;
A cutting surface extending from the first main surface to the second main surface along the outer peripheral edge of the termination structure region;
A semiconductor device comprising: In a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region,
A first conductivity type drift region having a first main surface and a second main surface;
A second conductivity type channel region selectively provided along the first main surface; a first conductivity type first semiconductor region selectively provided in the channel region; the first semiconductor region; A first electrode connected to both of the channel regions; a gate insulating film provided along the channel region between the first semiconductor region and the drift region; and a gate electrode provided along the gate insulating film An active region having
The second conductivity type embedded in the trench groove reaching deeper than the channel region from the first main surface and connected to the first electrode, and the second conductivity type provided along the side wall and bottom of the trench groove A transition region having a bypass region of
A second semiconductor region of a second conductivity type provided along the second main surface of the drift region;
A second electrode connected to the second semiconductor region;
A cutting surface extending from the first main surface to the second main surface along the outer peripheral edge of the termination structure region;
A semiconductor device comprising: In a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region,
A first conductivity type drift region having a first main surface and a second main surface;
A second conductivity type channel region selectively provided along the first main surface; a first conductivity type first semiconductor region selectively provided in the channel region; the first semiconductor region; A first electrode connected to both of the channel regions, along the inner peripheral surface of the first trench groove that reaches the drift region through the channel region from the first main surface adjacent to the first semiconductor region An active region having a gate insulating film provided, a gate electrode embedded in the first trench groove through the gate insulating film;
An electrode embedded in the second trench groove reaching deeper than the channel region from the first main surface and connected to the first electrode, and provided along the side wall and the bottom of the second trench groove A transition region having a bypass region of a second conductivity type;
A second semiconductor region of the first conductivity type provided along the second main surface of the drift region;
A second electrode connected to the second semiconductor region;
A cutting surface extending from the first main surface to the second main surface along the outer peripheral edge of the termination structure region;
A semiconductor device comprising: In a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region,
A first conductivity type drift region having a first main surface and a second main surface;
A second conductivity type channel region selectively provided along the first main surface; a first conductivity type first semiconductor region selectively provided in the channel region; the first semiconductor region; A first electrode connected to both of the channel regions, along the inner peripheral surface of the first trench groove that reaches the drift region through the channel region from the first main surface adjacent to the first semiconductor region An active region having a gate insulating film provided, a gate electrode embedded in the first trench groove through the gate insulating film;
An electrode embedded in the second trench groove reaching deeper than the channel region from the first main surface and connected to the first electrode, and provided along the side wall and the bottom of the second trench groove A transition region having a bypass region of a second conductivity type;
A second semiconductor region of a second conductivity type provided along the second main surface of the drift region;
A second electrode connected to the second semiconductor region;
A cutting surface extending from the first main surface to the second main surface along the outer peripheral edge of the termination structure region;
A semiconductor device comprising:   5. The semiconductor device according to claim 3, wherein a depth of the first trench groove and a depth of the second trench groove are the same. 6.   6. The semiconductor device according to claim 1, wherein the impurity profile of the bypass region and the impurity profile of the channel region are the same.   6. The body region of the second conductivity type is selectively provided in the channel region, and the impurity profile of the bypass region and the impurity profile of the body region are the same. The semiconductor device as described in any one. 8. The semiconductor device according to claim 1, wherein the MOS gate structure of the active region is formed linearly.

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