CN111710647A - Process for electroplating thick copper film on two sides of window opening - Google Patents
Process for electroplating thick copper film on two sides of window opening Download PDFInfo
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- CN111710647A CN111710647A CN202010641706.1A CN202010641706A CN111710647A CN 111710647 A CN111710647 A CN 111710647A CN 202010641706 A CN202010641706 A CN 202010641706A CN 111710647 A CN111710647 A CN 111710647A
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- 239000010949 copper Substances 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims abstract description 42
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 38
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 37
- 238000009713 electroplating Methods 0.000 title claims abstract description 14
- 239000010410 layer Substances 0.000 claims abstract description 54
- 238000005530 etching Methods 0.000 claims abstract description 28
- 239000011521 glass Substances 0.000 claims abstract description 20
- 239000012790 adhesive layer Substances 0.000 claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 12
- 238000007747 plating Methods 0.000 claims abstract description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 238000004140 cleaning Methods 0.000 claims abstract description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000010703 silicon Substances 0.000 claims abstract description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 13
- 238000005520 cutting process Methods 0.000 claims description 10
- 239000010936 titanium Substances 0.000 claims description 9
- AVXURJPOCDRRFD-UHFFFAOYSA-N Hydroxylamine Chemical compound ON AVXURJPOCDRRFD-UHFFFAOYSA-N 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 6
- 229920000642 polymer Polymers 0.000 claims description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 239000011241 protective layer Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 239000003960 organic solvent Substances 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
- 238000009832 plasma treatment Methods 0.000 claims description 3
- 239000005022 packaging material Substances 0.000 abstract description 4
- 230000008021 deposition Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 54
- 230000015572 biosynthetic process Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Electroplating Methods And Accessories (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention discloses a process for electroplating thick copper films on two sides of a window, belonging to the field of wafer processing, and comprising the following steps of S1: plating an adhesion layer, a barrier layer and a copper seed layer on the back of the wafer in sequence; s2: bonding the glass carrier plate; s3: grinding and etching the back of the wafer; s4: carrying out a manufacturing process; s5: plating Ti/Ni/Cu; s6: opening a window; s7: performing a yellow light process on the front surface of the wafer; s8: performing a yellow light process on the back surface of the wafer; s9: removing the photoresist layer after plating the thick film on both sides; s10: removing Ti/Ni/Cu on both sides by etching; s11: etching the silicon scribe line with SF6 plasma, stopping on the adhesive layer; s12: carrying out film deposition operation; s13: etching the silicon oxide or the silicon nitride to form a side wall; s14: cleaning and etching; s15: the wafer is attached to the blue film frame; s16: removing the glass carrier plate from the wafer; s17: cleaning the adhesive layer on the wafer; the wafer is bonded with the glass carrier plate to form an ultra-thin wafer, and a glass carrier plate window is formed at the contact point of the front surface of the wafer, so that the problem of electric leakage between thick-film copper and the packaging material is solved.
Description
Technical Field
The invention relates to the field of wafer processing, in particular to a process for electroplating thick copper films on two sides of a window.
Background
In the design and structure of high power, high voltage/current semiconductor devices, it is very important to use the thick film copper heat Sink material (cu eat Sink), otherwise the device will be overheated to cause local damage and generate serious reliability problem, and the requirement of ultra-thin wafer for low resistance and high frequency operation is very important, how to combine the ultra-thin wafer and double-sided plating thick film copper heat Sink wire plus the structure and installation method of the protection of the cut surface sidewall are the core of the present invention. Disadvantages of the prior art: 1. if the thick film copper electroplating is carried out on the back surface of the whole ultrathin wafer, the problem of Crack is generated and warped due to large difference points of stress and thermal expansion coefficients Cu and Si; 2. the front side and the back side are simultaneously electroplated with thick Cu films, if the technology of windowing without a glass substrate cannot be implemented, and if the front side is implemented first, the problem of wafer stress can cause that the back side thick Cu film electroplating cannot be implemented; 3. the thick film Cu has great difficulty in the traditional cutting and plasma cutting process on the ultrathin wafer; 4. the bonding-breaking process of the cut double-sided thick-film Cu on the glass carrier is also very difficult, and the possibility of breaking the ultrathin wafer during cutting or transferring to the Dicing Frame is very high; 5. the current dicing technology cannot protect the sidewalls of the separated dies, and the reliability Problem (leakage current) of the current leakage is difficult to avoid during high power operation of the package and the thick film wire.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a process for plating thick copper films on both sides of a window, which enables a wafer to be bonded with a glass carrier plate and form an ultrathin wafer, forms a glass carrier plate window at the contact point of the front side of the wafer, can plate Ti/Ni/Cu on both sides respectively, can simultaneously form thick film CuECP on the front side and the back side of the wafer, and solves the problem of leakage between thick film copper and a packaging material by forming a spacer on the side wall of a cutting channel by using a low-temperature plasma chemical vapor deposition technology and phase etching.
The purpose of the invention can be realized by the following technical scheme:
a technology for double-sided electroplating of thick copper films for window opening comprises the following steps:
s1: after completing Contact and W-plug on the front surface of the wafer, sequentially plating an adhesion layer, a barrier layer and a copper seed layer on the back surface of the wafer;
s2: bonding the front surface of the wafer on a glass carrier plate, wherein the middle layer is an adhesive layer and a release layer;
s3: grinding and etching the back surface of the wafer to make the thickness of the wafer 30-150 pm;
s4: processing the wafer back side element;
s5: plating an adhesion layer, a barrier layer and a copper seed layer on the back of the wafer;
s6: opening a window in an I/O PAD W-Plug area of the front surface of the wafer corresponding to the glass carrier plate;
s7: performing a yellow light process on the front surface of the wafer, and determining the position of a thick copper mold on the front surface by using the pattern;
s8: performing a yellow light process on the back surface of the wafer, and protecting the cutting path area by using thick film photoresist;
s9: removing the light resistance layer after double-sided electroplating of the thick film Cu ECP;
s10: removing Ti/Ni/Cu on both sides by etching, and stopping etching on the surface of the wafer;
s11: etching silicon scribe lines on the back wafer by using thick film copper as a Hard Mask through SF6 plasma, stopping on the adhesive layer, and cleaning residues and polymers remained on the surface of the wafer after etching by using a hydroxylamine remover;
s12: performing PECVD on the scribe line to deposit a film, etching the back surface of the wafer and the inner side wall of the scribe line to a thickness of
A silicon oxide or silicon nitride protective layer;
s13: using fluorine-containing gas to perform plasma treatment and providing a bias voltage potential to etch silicon oxide or silicon nitride to form a side wall;
s14: cleaning residues and polymers remained on the surface of the wafer after etching by using a hydroxylamine remover;
s15: turning over the chip to make the back of the wafer attached to the blue film frame;
s16: the viscidity of the adhesive layer release layer is dissociated through ultraviolet irradiation or heat treatment or laser mode, and the glass carrier plate is removed from the wafer;
s17: the adhesive layer on the wafer is cleaned with an organic solvent to complete the die with copper heat spreader to complete the die on the dicing frame.
In a preferred embodiment of the present invention, in step S1, the adhesion layer is a titanium layer, the titanium layer has a thickness of 1 to 2 microns, the barrier layer is a nickel layer, and the nickel layer has a thickness of 1 to 2 microns.
As a preferred embodiment of the present invention, in step S4, the process includes a photo lithography process, an Implantation process, and an Annealing process.
The invention has the beneficial effects that:
1. the invention can safely and nondestructively cut the thin wafer with the copper heat dissipation junction structure;
2. the invention uses one-time yellow light and mask pattern process (photomask) to perform Cusink thick film plating and reverse plasma crystal grain cutting.
3. The invention can be used for electroplating the copper heat sink structure on two sides simultaneously, thereby improving the productivity.
4. The invention has the advantages that the two sides are simultaneously electroplated, so that the two sides of the stress in the process are balanced, and the problems of loss such as warping, fragment and the like are avoided
5. The protection of the side wall of the invention avoids current leakage (leakageProblem) of the packaging material and the thick film wire in high-power operation.
6. The invention can be matched with a copper clamping and welding packaging structure, greatly improves the heat dissipation capability and maintains the optimal performance of the element.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of the formation in step S1 of the present invention process;
FIG. 2 is an enlarged view of FIG. 1 at A;
FIG. 3 is a schematic diagram of the formation in step S2 of the present invention process;
FIG. 4 is a schematic diagram of the formation in step S6 of the present invention process;
FIG. 5 is a schematic diagram of the formation in step S8 of the present invention process;
FIG. 6 is a schematic diagram of the formation in step S9 of the present invention process;
FIG. 7 is a schematic diagram of the formation in step S10 of the present invention process;
FIG. 8 is a schematic view of the formation in step S11 of the present invention process;
FIG. 9 is a schematic diagram of the formation in step S14 of the present invention process;
FIG. 10 is an enlarged view of FIG. 9 at B;
FIG. 11 is a schematic view of the formation in step S16 of the process of the present invention;
FIG. 12 is a schematic view of the formation in step S17 of the present invention process.
The reference numbers in the figures illustrate:
1 wafer, 2 ILD layers, 3W-plug, 4 adhesion layers, 5 barrier layers, 6 copper seed layers, 7 glass carrier plates, 8 adhesive layers, 9 thick copper films, 10 photoresist layers, 11 silicon oxide protective layers, 12 silicon nitride film layers and 13 cutting frames
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in the figure, the process for electroplating thick copper films on both sides of the window opening comprises the following steps:
s1: after completing Contact and W-plug on the front surface of the wafer, sequentially plating an adhesion layer, a barrier layer and a copper seed layer on the back surface of the wafer;
s2: bonding the front surface of the wafer on a glass carrier plate, wherein the middle layer is an adhesive layer and a release layer;
s3: grinding and etching the back surface of the wafer to make the thickness of the wafer 30-150 pm;
s4: processing the wafer back side element;
s5: plating an adhesion layer, a barrier layer and a copper seed layer on the back of the wafer;
s6: opening a window in an I/O PAD W-Plug area of the front surface of the wafer corresponding to the glass carrier plate;
s7: performing a yellow light process on the front surface of the wafer, and determining the position of a thick copper mold on the front surface by using the pattern;
s8: performing a yellow light process on the back surface of the wafer, and protecting the cutting path area by using thick film photoresist;
s9: removing the light resistance layer after double-sided electroplating of the thick film Cu ECP;
s10: removing Ti/Ni/Cu on both sides by etching, and stopping etching on the surface of the wafer;
s11: etching silicon scribe lines on the back wafer by using thick film copper as a Hard Mask through SF6 plasma, stopping on the adhesive layer, and cleaning residues and polymers remained on the surface of the wafer after etching by using a hydroxylamine remover;
s12: performing PECVD on the scribe line to deposit a film, etching the back surface of the wafer and the inner side wall of the scribe line to a thickness of
A silicon oxide or silicon nitride protective layer;
s13: using fluorine-containing gas to perform plasma treatment and providing a bias voltage potential to etch silicon oxide or silicon nitride to form a side wall;
s14: cleaning residues and polymers remained on the surface of the wafer after etching by using a hydroxylamine remover;
s15: turning over the chip to make the back of the wafer attached to the blue film frame;
s16: the viscidity of the adhesive layer release layer is dissociated through ultraviolet irradiation or heat treatment or laser mode, and the glass carrier plate is removed from the wafer;
s17: the adhesive layer on the wafer is cleaned with an organic solvent to complete the die with copper heat spreader to complete the die on the dicing frame.
In step S1, the adhesion layer is a titanium layer having a thickness of 1 to 2 microns, the barrier layer is a nickel layer having a thickness of 1 to 2 microns.
In step S4, the process includes photo lithography process, Implantation process and Annealing process.
The scheme enables a wafer to be bonded with a glass carrier plate and form an ultrathin wafer, a glass carrier plate window is formed at a contact point (PAD I/O) on the front surface of the wafer, two surfaces of the wafer can be respectively plated with Ti/Ni/Cu (barrier/seed), wafers on two surfaces (front surface/back surface) can be simultaneously plated with thick film Cu ECP (electroplating), and the problem of leakage (leak) between thick film copper and a packaging material is solved by forming a spacer on the side wall of a cutting channel by utilizing a PECVD (Plasma enhanced chemical vapor deposition) technology at a low temperature (the temperature is less than 250 ℃) and phase (anistropic) etching (Plasma etching).
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed.
Claims (3)
1. A technology for electroplating thick copper films on two sides of a window is characterized by comprising the following steps:
s1: after completing Contact and W-plug on the front surface of the wafer, sequentially plating an adhesion layer, a barrier layer and a copper seed layer on the back surface of the wafer;
s2: bonding the front surface of the wafer on a glass carrier plate, wherein the middle layer is an adhesive layer and a release layer;
s3: grinding and etching the back surface of the wafer to make the thickness of the wafer 30-150 pm;
s4: processing the wafer back side element;
s5: plating an adhesion layer, a barrier layer and a copper seed layer on the back of the wafer;
s6: opening a window in an I/O PAD W-Plug area of the front surface of the wafer corresponding to the glass carrier plate;
s7: performing a yellow light process on the front surface of the wafer, and determining the position of a thick copper mold on the front surface by using the pattern;
s8: performing a yellow light process on the back surface of the wafer, and protecting the cutting path area by using thick film photoresist;
s9: removing the light resistance layer after double-sided electroplating of the thick film Cu ECP;
s10: removing Ti/Ni/Cu on both sides by etching, and stopping etching on the surface of the wafer;
s11: etching silicon scribe lines on the back wafer by using thick film copper as a Hard Mask through SF6 plasma, stopping on the adhesive layer, and cleaning residues and polymers remained on the surface of the wafer after etching by using a hydroxylamine remover;
s12: performing PECVD on the scribe line to deposit a film, etching the back surface of the wafer and the inner side wall of the scribe line to a thickness of
A silicon oxide or silicon nitride protective layer;
s13: using fluorine-containing gas to perform plasma treatment and providing a bias voltage potential to etch silicon oxide or silicon nitride to form a side wall;
s14: cleaning residues and polymers remained on the surface of the wafer after etching by using a hydroxylamine remover;
s15: turning over the chip to make the back of the wafer attached to the blue film frame;
s16: the viscidity of the adhesive layer release layer is dissociated through ultraviolet irradiation or heat treatment or laser mode, and the glass carrier plate is removed from the wafer;
s17: the adhesive layer on the wafer is cleaned with an organic solvent to complete the die with copper heat spreader to complete the die on the dicing frame.
2. The process of claim 1, wherein the thick copper film is electroplated on both sides of the window opening: in step S1, the adhesion layer is a titanium layer having a thickness of 1 to 2 microns, the barrier layer is a nickel layer having a thickness of 1 to 2 microns.
3. The process of claim 1, wherein the thick copper film is electroplated on both sides of the window opening: in step S4, the process includes photo lithography process, Implantation process and Annealing process.
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| CN112234018A (en) * | 2020-10-19 | 2021-01-15 | 绍兴同芯成集成电路有限公司 | Ultrathin large-area tin ball printing process adopting polyimide |
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| US5049244A (en) * | 1989-01-20 | 1991-09-17 | Casio Computer Co., Ltd. | Method of manufacturing double-sided wiring substrate |
| JP2000082695A (en) * | 1998-05-14 | 2000-03-21 | Sony Corp | Plasma etching method and semiconductor device |
| US20050067188A1 (en) * | 2003-09-25 | 2005-03-31 | Tong Hsing Electric Industries Ltd. | Thin film circuit integrating thick film resistors thereon and method of fabricating the same |
| CN102065648A (en) * | 2009-11-17 | 2011-05-18 | 张�林 | Double-sided circuit board and interconnection conduction method thereof |
| US20130149836A1 (en) * | 2011-12-12 | 2013-06-13 | Shanghai Hua Hong Nec Electronics Co., Ltd. | Method of double-sided patterning |
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2020
- 2020-07-06 CN CN202010641706.1A patent/CN111710647B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5049244A (en) * | 1989-01-20 | 1991-09-17 | Casio Computer Co., Ltd. | Method of manufacturing double-sided wiring substrate |
| JP2000082695A (en) * | 1998-05-14 | 2000-03-21 | Sony Corp | Plasma etching method and semiconductor device |
| US20050067188A1 (en) * | 2003-09-25 | 2005-03-31 | Tong Hsing Electric Industries Ltd. | Thin film circuit integrating thick film resistors thereon and method of fabricating the same |
| CN102065648A (en) * | 2009-11-17 | 2011-05-18 | 张�林 | Double-sided circuit board and interconnection conduction method thereof |
| US20130149836A1 (en) * | 2011-12-12 | 2013-06-13 | Shanghai Hua Hong Nec Electronics Co., Ltd. | Method of double-sided patterning |
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| CN112234018A (en) * | 2020-10-19 | 2021-01-15 | 绍兴同芯成集成电路有限公司 | Ultrathin large-area tin ball printing process adopting polyimide |
| CN112234018B (en) * | 2020-10-19 | 2022-03-15 | 绍兴同芯成集成电路有限公司 | Ultrathin large-area tin ball printing process adopting polyimide |
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