CN111710278B

CN111710278B - Display device and driving method thereof

Info

Publication number: CN111710278B
Application number: CN202010612043.0A
Authority: CN
Inventors: 黄志鹏; 詹小静; 吴常志; 薛志远
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2020-06-29
Filing date: 2020-06-29
Publication date: 2022-11-25
Anticipated expiration: 2040-06-29
Also published as: CN111710278A

Abstract

The embodiment of the invention discloses a display device and a driving method thereof, wherein the display device comprises a plurality of driving chips; the number of the data lines electrically connected with at least part of the driving chips is different; the line synchronizing signal period of each driving chip is the same, and the duration of the effective synchronizing pulse stage is the same. The display device provided by the embodiment of the invention has the effect that when the number of the electrically connected lines of different driving chips is different, the periods of the row synchronization signals of the driving chips are the same.

Description

Display device and driving method thereof

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a display device and a driving method of the display device.

Background

At present, display technologies are widely applied to the fields of televisions, mobile phones, advertising information, vehicles and the like. Among display products applied to display devices for displaying advertisement information, display devices for vehicle-mounted display, and the like, large-sized display products are common. In a large-sized display product, because the screen is large, the load is large, and it is often insufficient to drive the display panel through the driving capability of one driving chip for displaying, so that a plurality of driving chips are usually adopted for driving, that is, different driving chips are respectively electrically connected to the data lines in the display panel.

However, when the number of the data lines electrically connected to different driving chips is different, the problem of inconsistent row synchronization signals occurs, and thus, the display effect is affected.

Disclosure of Invention

In view of this, embodiments of the present invention provide a display device and a driving method of the display device, so as to achieve an effect that when the number of lines electrically connected to different driving chips is different, the periods of the row synchronization signals of the driving chips are the same.

In a first aspect, an embodiment of the present invention provides a display device, where the display device includes a plurality of driving chips; the number of the data lines electrically connected with at least part of the driving chips is different; the line synchronizing signal period of each driving chip is the same, and the duration of the effective synchronizing pulse stage is the same.

In a second aspect, an embodiment of the present invention further provides a driving method for a display device, where the display device includes a plurality of driving chips; the number of the data lines electrically connected with at least part of the driving chips is different; the method comprises the following steps:

acquiring a display control signal;

analyzing the display control signal to obtain a line synchronization signal;

the line synchronizing signal period of each driving chip is the same, and the duration of the effective synchronizing pulse stage is the same.

According to the display device and the driving method of the display device provided by the embodiment of the invention, the line synchronizing signal periods of the driving chips are the same, and the duration of the effective synchronizing pulse stage is the same, namely, even if the number of the data lines of the driving chip pairs is different, the line synchronizing signals are kept consistent, so that the problem that the display effect is influenced due to the inconsistent line synchronizing signals in the prior art is solved, and the display effect of the display device is favorably improved. For example, when the display device is applied to an in-vehicle display device, it is advantageous to improve the display effect of the in-vehicle display device.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:

FIG. 1 is a schematic diagram of a display device in the prior art;

fig. 2 is a driving timing diagram of each driving chip in the prior art;

FIG. 3 is a timing diagram of driving the display device of FIG. 1;

fig. 4 is a schematic structural diagram of a display device according to an embodiment of the present invention;

FIG. 5 is a timing diagram of a display device according to an embodiment of the present invention;

FIG. 6 is a schematic structural diagram of another display device according to an embodiment of the present invention;

FIG. 7 is a timing diagram illustrating the driving of another display device according to an embodiment of the present invention;

FIG. 8 is a schematic structural diagram of another display device according to an embodiment of the present invention;

FIG. 9 is a timing diagram illustrating the driving of a display device according to another embodiment of the present invention;

FIG. 10 is a timing diagram illustrating the driving of a display device according to another embodiment of the present invention;

FIG. 11 is a timing diagram illustrating the driving of a display device according to another embodiment of the present invention;

FIG. 12 is a timing chart illustrating the driving of a display device according to another embodiment of the present invention;

fig. 13 is a flowchart of a driving method of a display device according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be described in detail below by way of specific embodiments in conjunction with the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are a part of the embodiments of the present invention, not all embodiments, and all other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without inventive efforts fall within the scope of the present invention.

Fig. 1 is a schematic structural diagram of a display device in the prior art, and fig. 2 is a timing diagram of driving of each driving chip in the prior art; fig. 3 is a driving timing diagram of the display device in fig. 1, and as shown in fig. 1, fig. 2 and fig. 3, a conventional display device 100' includes a plurality of driving chips 10' and a display panel 20', the display panel 20' includes data lines 30' and scan lines 40', and the data lines 30' and the scan lines 40' are arranged in a crossing manner to define a plurality of sub-pixels 50' arranged in an array; in the present embodiment, the number of the data lines 30' electrically connected to some of the driver chips 10' is different, for example, in fig. 1, the plurality of driver chips 10' includes the first driver chip 11', the second driver chip 12' and the third driver chip 13', the number of the data lines 30' electrically connected to the first driver chip 11' is the same, and the number of the data lines 30' electrically connected to the second driver chip 12' and the first driver chip 11' is different, referring to fig. 2, for the driver chips 10' electrically connected to the different number of data lines 30' in the prior art, the row synchronization signal HS ' is different, that is, the duration of the effective synchronization pulse period T2' of the second driver chip 12' electrically connected to the larger number of the data lines 30' is longer than the effective synchronization pulse period T1' of the first driver chip 11' electrically connected to the smaller number of the data lines 30' and the effective synchronization pulse period T3' of the third driver chip 13', and accordingly, the period of the row synchronization signal HS2' electrically connected to the second driver chip 12' electrically connected to the larger number of the data lines 20' is longer than the period of the first driver chip 13' electrically connected to the third driver chip 11' electrically connected to the fewer number of the data lines. The row sync signal HS ' is used to determine the effective row signal interval on the display panel 20', i.e. the driving chip 10' provides the display signal to each row of the sub-pixels 50' by using the scan lines 40' and the data lines 30' according to the row sync signal HS '. The display signal includes a gate-on signal G ' and a data signal DA ', etc., that is, the gate-on signal G ' is provided to the sub-pixels 50' row by using the scan line 40', and the data signal DA ' is provided to the sub-pixels 50' on the row by using the data line 30' to charge the sub-pixels 50' on each row. When the row synchronizing signals HS 'of the plurality of driving chips 10' are different, the timing at which the driving chips 10 'supply the display signals to the sub-pixels 50' of each row is different, i.e., the time of the gate-on signal G 'and the writing time of the data signal DA' are also different (see fig. 2). If the gate-on signal G1' is provided to each row of sub-pixels 50' in the display panel 20' by using the row synchronization signal HS1' of the first driving chip 11' (see fig. 3), that is, the on-state of one row of sub-pixels 50' is determined by the row synchronization signal HS1' of the first driving chip 11', for example, when the second row of sub-pixels 50' in the display panel 20' needs to be charged, the second row of sub-pixels 50' is fully turned on, the sub-pixels 50' corresponding to the first driving chip 11' and the sub-pixels 50' corresponding to the third driving chip 13' have already been charged, while the sub-pixels 50' corresponding to the second driving chip 12' are not charged, that is, the sub-pixels 50' corresponding to the first driving chip 11' and the sub-pixels 50' corresponding to the third driving chip 13' are delayed by the time period M, and when the charging of the sub-pixels 50' corresponding to the first driving chip 11' and the sub-pixels 50' corresponding to the third driving chip 13' has already been charged, the off, the sub-pixels 50' in the first row of the first driving chip 11' are not charged yet, and the sub-pixels 50' in the first row of the second driving chip 12' have not charged, so, the effect of the sub-pixels 50' of the corresponding sub-pixels 20' in the display panel 20' is not reached, that the time period M, that the effect of the sub-pixels 50' is not charged.

In view of the above technical problems, an embodiment of the present invention provides a display device, including a plurality of driving chips; the number of the data lines electrically connected with at least part of the driving chips is different; the line synchronizing signal period of each driving chip is the same, and the duration of the effective synchronizing pulse stage is the same. By adopting the technical scheme, the line synchronizing signal periods of the driving chips are the same, and the duration of the effective synchronizing pulse stage is the same, namely, even if the number of the data lines electrically connected with the different driving chips is different, the line synchronizing signals are kept consistent, so that the problem that the display effect is influenced due to the inconsistent line synchronizing signals in the prior art is solved, and the display effect of the display device is favorably improved. For example, when the display device is applied to an in-vehicle display device, it is advantageous to improve the display effect of the in-vehicle display device.

The above is the core idea of the present invention, and the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention. All other embodiments, which can be obtained by a person skilled in the art based on the embodiments of the present invention without any creative work, belong to the protection scope of the present invention.

Fig. 4 is a schematic structural diagram of a display device according to an embodiment of the present invention, and fig. 5 is a timing diagram of driving the display device according to the embodiment of the present invention, and as shown in fig. 4 and fig. 5, the display device 100 includes a plurality of driving chips 10; the number of the data lines 30 electrically connected to at least a part of the driving chips 10 is different; the periods of the horizontal synchronizing signals HS of the driving chips 10 are the same, and the durations of the effective synchronizing pulse periods T are the same.

Specifically, the display device 100 further includes a display panel 20, and the display panel 20 includes a plurality of sub-pixels 50 arranged in an array. The different driving chips 10 respectively provide the data lines 30 electrically connected thereto with the data signals DA according to the row synchronization signals HS thereof to charge the sub-pixels 50 of each row, i.e., the row synchronization signals HS define an effective row signal interval in which the driving chips 10 provide the data signals DA to the display panel 20, i.e., a high level stage of DA in fig. 5. Because the periods of the row synchronization signals HS of the driving chips 10 are the same, and the durations of the effective synchronization pulse phases T are the same, that is, the effective row signal intervals for providing the data signals for the display panel 20 by the different driving chips 10 are the same, the consistency of the charging time of the sub-pixels 50 corresponding to different driving chips 10 in each row is ensured, and the problem that the display effect of the display device is affected due to the inconsistent charging time of the sub-pixels 50 in each row when the row synchronization signals of the driving chips 10 are different is solved.

For example, fig. 6 is a schematic structural diagram of another display device provided in an embodiment of the present invention, and fig. 7 is a timing diagram of driving the another display device provided in the embodiment of the present invention, as shown in fig. 6 and fig. 7, the display device 100 includes three driver chips 10, which are a first driver chip 11, a second driver chip 12, and a third driver chip 13; the number of the data lines 30 electrically connected to the first driving chip 11 and the third driving chip 13 is the same, and the number of the data lines 30 electrically connected to the first driving chip 11 and the second driving chip 12 is different.

Specifically, although the number of the data lines electrically connected to the first driving chip 11 and the second driving chip 12 is different, the period of the row synchronization signal HS1 of the first driving chip 11, the period of the row synchronization signal HS2 of the second driving chip 12, and the period of the row synchronization signal HS3 of the third driving chip 13 are the same, so that the effective row signal intervals for providing the data signal DA to the sub-pixels 50 in the same row in the display panel 20 by the first driving chip 11, the second driving chip 12, and the third driving chip 13 are the same, thereby ensuring the charging time consistency of the sub-pixels 50 corresponding to each row of the first driving chip 11, the second driving chip 12, and the third driving chip 13, and avoiding the problem that when the row synchronization signals of the first driving chip 11, the second driving chip 12, and the third driving chip 13 are different, the charging time of the sub-pixels 50 in each row is inconsistent, and the display effect of the display device is affected.

Optionally, with reference to fig. 6, in a direction perpendicular to the data lines 30, the first driver chip 11, the second driver chip 12, and the third driver chip 13 are sequentially arranged, and the number of the data lines 30 electrically connected to the second driver chip 12 is greater than the number of the data lines 30 electrically connected to the first driver chip 11. The advantage of this configuration is that, because the number of the data lines 30 electrically connected to the second driver chip 12 is greater, and accordingly, the number of the bonding terminals on the second driver chip 12 is also greater, if the second driver chip 12 electrically connected to the data lines 30 is disposed on one side, the second driver chip 20 that passes through provides corresponding signals for the gate driver circuit (not shown in the figure) on at least one side of the display panel 20 in consideration of the narrow frame of the display panel 20, and thus, the number of the bonding terminals of the second driver chip 12 is further increased, and in the present embodiment, by disposing the second driver chip 12 between the first driver chip 11 and the third driver chip 13, the first driver chip 11 and/or the third driver chip 13 can provide corresponding signals for the gate driver circuit (not shown in the figure) on at least one side of the display panel 20, and the number of the bonding terminals of the second driver chip 12 is reduced.

Optionally, the second driving chip, the first driving chip and the third driving chip are sequentially arranged along a direction perpendicular to the data lines, and the number of the data lines electrically connected to the second driving chip is greater than the number of the data lines electrically connected to the first driving chip. The present embodiment does not limit the arrangement order of the first driver chip, the second driver chip, and the third driver chip.

For example, fig. 8 is a schematic structural diagram of another display device provided in an embodiment of the present invention, fig. 9 is a timing diagram of driving of the display device provided in the embodiment of the present invention, and as shown in fig. 8 and fig. 9, the display device 100 includes two driving chips 10, which are a first driving chip 11 and a second driving chip 12 respectively; the number of the data lines 30 electrically connected to the first driving chip 11 and the second driving chip 12 is different.

Specifically, although the number of the data lines electrically connected to the first driving chip 11 and the second driving chip 12 is different, the period of the row synchronization signal HS1 of the first driving chip 11 is the same as the period of the row synchronization signal HS2 of the second driving chip 12, so that the effective row signal intervals for providing the data signal DA to the sub-pixels 50 in the same row in the display panel 20 by the first driving chip 11 and the second driving chip 12 are the same, thus ensuring the consistency of the charging time of the sub-pixels 50 corresponding to the first driving chip 11 and the second driving chip 12 in each row, and avoiding the problem that when the row synchronization signals of the first driving chip 11 and the second driving chip 12 are different, the charging time of the sub-pixels 50 in each row is inconsistent, and the display effect of the display device is affected.

In fig. 5, 7 and 9, when the valid sync pulse period T corresponding to the line sync signal HS is at a high level, the valid sync pulse period T is defined as valid, but the present application is not limited thereto; alternatively, the active synchronization pulse period T may be defined as active when the pulse is at a low level (not shown).

It should be noted that, fig. 6 only exemplifies that the plurality of driver chips 10 include three driver chips, and fig. 8 only exemplifies that the plurality of driver chips 10 include two driver chips 10, but the present application is not limited thereto, as long as the periods of the row synchronization signals HS corresponding to different driver chips 10 are the same, and the duration of the effective synchronization pulse period T is the same.

In summary, in the display device provided in the embodiment of the present invention, the periods of the row synchronization signals of the driving chips are the same, and the durations of the effective synchronization pulse phases are the same, that is, even if the number of the data lines electrically connected to the different driving chips is different, the row synchronization signals are kept consistent, so that the problem that the display effect is affected due to the inconsistent row synchronization signals in the prior art is solved, and the display effect of the display device is improved. For example, when the display device is applied to an in-vehicle display device, it is advantageous to improve the display effect of the in-vehicle display device.

Fig. 10 is a driving timing diagram of another display device according to an embodiment of the present invention, as shown in fig. 10, the valid gate pulse period VD of the data gate signal DE of each driving chip 10 is within the valid sync pulse period T of the row sync signal HS of the driving chip 10; the gating interval of the data strobe signal DE corresponding to the driving chip 10 with a large number of connected data lines is smaller than the gating interval of the data strobe signal DE corresponding to the driving chip 10 with a small number of connected data lines; wherein, the time difference between the starting time of the effective synchronization pulse stage T of the line synchronization signal HS and the starting time of the effective strobe stage VD of the data strobe signal DE is a first gap HBP; the time difference between the end time of the effective strobe phase VD of the data strobe signal DE and the end time of the effective sync phase T of the row sync signal HS is the second gap HFP; the sum of the first gap HBP and the second gap HFP is the gating gap.

Specifically, when the overall control system, for example, may be a processor, respectively sends total data signals of a row of sub-pixels to each driving chip 10, the driving chip 10 determines an effective data signal area Hactive in the total data signals through an effective strobe period VD of the data strobe signal DE, that is, determines effective data signals in the total data signals, so that each driving chip 10 respectively transmits the effective data signals in the total data signals to the sub-pixels corresponding thereto according to the row synchronization signal HS. Since the effective data signal amount of the driving chips 10 with a large number of electrically connected data lines is large, that is, the period of the effective data signal area Hactive is long, and one period of the row synchronization signal HS is determined by the first gap HBP, the second gap HFP and the effective data signal area Hactive, if the first gap HBP and the second gap HFP are consistent, the period of the row synchronization signal HS of the driving chips 10 with a large number of electrically connected data lines is long, and further the row synchronization signals HS of the driving chips 10 are inconsistent, in this embodiment, under the condition that the length of the period of the effective data signal area Hactive of each driving chip is not changed, the sum of the first gap HBP and the second gap HFP of the driving chips 10 with a large number of electrically connected data lines is smaller than the sum of the first gap HBP and the second gap HFP of the driving chips 10 with a small number of electrically connected data lines, so as to ensure the consistency of the row synchronization signals of the driving chips 10.

Optionally, there are a plurality of different implementations that the sum of the first gap HBP and the second gap HFP of the data strobe signal DE corresponding to the driving chip 10 connected with the large number of data lines 30 is smaller than the sum of the first gap HBP and the second gap HFP of the data strobe signal DE corresponding to the driving chip 10 connected with the small number of data lines 20, and the following description will take three possible implementations as an example.

Optionally, the first gaps of the data strobe signals corresponding to the driving chips are the same; the second gap of the data strobe signal corresponding to the driving chip with a large number of the connecting data lines is smaller than the second gap of the data strobe signal corresponding to the driving chip with a small number of the connecting data lines.

Illustratively, with continued reference to fig. 10, the plurality of driver chips include a first driver chip 11 and a second driver chip 12, and the number of the second driver chip 12 electrically connected to the data lines is greater than the number of the first driver chip 11 electrically connected to the data lines; the first gap HBP1 of the data strobe signal DE1 corresponding to the first driver chip 11 is the same as the first gap HBP2 of the data strobe signal DE2 corresponding to the second driver chip 12; the second gap HFP2, to which the data strobe signals DE2 corresponding to the second driving chips 12 having the larger number of data lines are connected, is smaller than the second gap HFP1, to which the data strobe signals DE1 corresponding to the first driving chips 11 having the smaller number of data lines are connected, so that the sum of the first gap HBP2 and the second gap HFP2, to which the data strobe signals DE2 corresponding to the second driving chips 12 having the larger number of data lines 30 are connected, is smaller than the sum of the first gap HBP1 and the second gap HFP1, to which the data strobe signals DE1 corresponding to the first driving chips 11 having the smaller number of data lines 20 are connected.

Optionally, the second gaps of the data strobe signals corresponding to the driving chips are the same; the first interval of the data strobe signal corresponding to the driving chip with the large number of the connection data lines is smaller than the first interval of the data strobe signal corresponding to the driving chip with the small number of the connection data lines.

For example, fig. 11 is a driving timing diagram of another display device according to an embodiment of the present invention, as shown in fig. 11, the plurality of driving chips include a first driving chip 11 and a second driving chip 12, and the number of data lines electrically connected to the second driving chip 12 is greater than the number of data lines electrically connected to the first driving chip 11; the second gap HFP1 of the data strobe signal DE1 corresponding to the first driving chip 11 is the same as the second gap HFP2 of the data strobe signal DE2 corresponding to the second driving chip 12; the first gap HBP2 for connecting the data strobe signals DE2 corresponding to the second driving chips 12 having the larger number of data lines is smaller than the first gap HBP1 for connecting the data strobe signals DE1 corresponding to the first driving chips 11 having the smaller number of data lines, so that the sum of the first gap HBP2 and the second gap HFP2 for connecting the data strobe signals DE2 corresponding to the second driving chips 12 having the larger number of data lines 30 is smaller than the sum of the first gap HBP1 and the second gap HFP1 for connecting the data strobe signals DE1 corresponding to the first driving chips 11 having the smaller number of data lines 20.

Optionally, the second gap and the first gap of the data strobe signal corresponding to each driving chip are different, but smaller than the first gap of the data strobe signal corresponding to the driving chip with less connecting data lines

For example, fig. 12 is a driving timing diagram of another display device according to an embodiment of the present invention, as shown in fig. 12, the plurality of driving chips include a first driving chip 11 and a second driving chip 12, and the number of data lines electrically connected to the second driving chip 12 is greater than the number of data lines electrically connected to the first driving chip 11; the first gap HBP1 of the data strobe signal DE1 corresponding to the first driver chip 11 is different from the first gap HBP2 of the data strobe signal DE2 corresponding to the second driver chip 12; the second gap HFP2 to which the data strobe signal DE2 corresponding to the second driving chip 12 having the large number of data lines is connected is different from the second gap HFP1 to which the data strobe signal DE1 corresponding to the first driving chip 11 having the small number of data lines is connected, but the sum of the first gap HBP2 and the second gap HFP2 to which the data strobe signal DE2 corresponding to the second driving chip 12 having the large number of data lines 30 is connected is smaller than the sum of the first gap HBP1 and the second gap HFP1 to which the data strobe signal DE1 corresponding to the first driving chip 11 having the small number of data lines 20 is connected.

In addition, fig. 10, 11, and 12 each take an example in which the driver chip includes the first driver chip 11 and the second driver chip 12, but the present application is not limited thereto.

Based on the same inventive concept, the embodiment of the invention also provides a driving method of the display device. Fig. 13 is a flowchart of a driving method of a display device according to an embodiment of the present invention, and as shown in fig. 13, the display device includes a plurality of driving chips; the number of the data lines electrically connected with at least part of the driving chips is different; the method comprises the following steps:

and S110, acquiring a display control signal.

The overall control system may include, for example, a processor, and respectively send display control signals to the plurality of driving chips, where the display control signals include row synchronization signals, so that the driving chips provide display signals to the display panel according to the row synchronization signals, where the display signals include gate-on signals, data signals, and the like.

S120, analyzing the display control signal to obtain a line synchronization signal; the line synchronizing signal period of each driving chip is the same, and the duration of the effective synchronizing pulse stage is the same.

Specifically, although the number of the data lines electrically connected to at least a part of the driving chips is different, the periods of the row synchronization signals of the driving chips are the same, and the durations of the effective synchronization pulse phases are the same, so that the problem that the display effect is influenced due to the fact that the row synchronization signals are inconsistent in the prior art is solved, and the display effect of the display device is improved.

On the basis of the above scheme, optionally, the driving method of the display device further includes:

analyzing the display control signal to obtain a data gating signal; the effective strobe pulse stage of the data strobe signal is positioned in the effective synchronous pulse stage of the line synchronous signal; the gating interval of the data gating signals corresponding to the driving chips which are connected with the data lines in a large number is smaller than the gating interval of the data gating signals corresponding to the driving chips which are connected with the data lines in a small number; the time difference between the starting time of the effective synchronous pulse phase of the line synchronous signal and the starting time of the effective strobe phase of the data strobe signal is a first gap; the time difference between the end time of the effective strobe phase of the data strobe signal and the end time of the effective synchronous pulse phase of the row synchronous signal is a second gap; the sum of the first gap and the second gap is the gating gap.

Specifically, the display control signal includes not only the row synchronization signal, but also the data strobe signal and the total data signal corresponding to each row of sub-pixels, and an effective data signal area in the total data signal is determined by an effective strobe pulse stage of the data strobe signal. Since the amount of the effective data signals of the driving chips 10 with the large number of electrically connected data lines is large, that is, the period of the effective data signal region is long, and one row synchronization signal period is determined by the first gap, the second gap and the effective data signal region, if the first gap and the second gap are kept consistent, the row synchronization signal period of the driving chips with the large number of electrically connected data lines is lengthened, and further the row synchronization signals of the driving chips are inconsistent, in this embodiment, under the condition that the length of the period of the effective data signal region of each driving chip is guaranteed to be unchanged, the consistency of the row synchronization signals of the driving chips is guaranteed by the fact that the sum of the first gap and the second gap of the driving chips with the large number of electrically connected data lines is smaller than the sum of the first gap and the second gap of the driving chips with the small number of electrically connected data lines.

Optionally, the first gaps of the data strobe signals corresponding to the driving chips are the same; the second gap of the data strobe signal corresponding to the driving chip with a large number of connection data lines is smaller than the second gap of the data strobe signal corresponding to the driving chip with a small number of connection data lines.

Specifically, the first gaps of the data strobe signals corresponding to the driving chips are the same; however, the second gap of the data strobe signal corresponding to the driving chip with a large number of connected data lines is smaller than the second gap of the data strobe signal corresponding to the driving chip with a small number of connected data lines, so that the sum of the first gap and the second gap of the data strobe signal corresponding to the driving chip with a large number of connected data lines is smaller than the sum of the first gap and the second gap of the data strobe signal corresponding to the first driving chip with a small number of connected data lines. That is, the time period of the effective data signal area of the driving chip with the large number of electrically connected data lines is longer than the time period of the effective data signal area of the driving chip with the small number of electrically connected data lines, but the sum of the first gap and the second gap of the driving chip with the large number of electrically connected data lines is less than the sum of the first gap and the second gap of the driving chip with the small number of electrically connected data lines, so that the consistency of the row synchronization signals of the driving chips is ensured.

Specifically, the second gaps of the data strobe signals corresponding to the driving chips are the same; however, the first gap of the data strobe signal corresponding to the driving chip with the large number of electrically connected data lines is smaller than the first gap of the data strobe signal corresponding to the driving chip with the small number of electrically connected data lines, so that the sum of the first gap and the second gap of the data strobe signal corresponding to the driving chip with the large number of electrically connected data lines is smaller than the sum of the first gap and the second gap of the data strobe signal corresponding to the first driving chip with the small number of electrically connected data lines. Although the time period of the effective data signal area of the driving chip with the large number of the electrically connected data lines is longer than the time period of the effective data signal area of the driving chip with the small number of the electrically connected data lines, the sum of the first gap and the second gap of the driving chip with the large number of the electrically connected data lines is less than the sum of the first gap and the second gap of the driving chip with the small number of the electrically connected data lines, and thus, the consistency of the row synchronization signals of the driving chips is ensured.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display device is characterized in that the display device comprises a plurality of driving chips; the number of the data lines electrically connected with at least part of the driving chips is different; the line synchronization signal periods of the driving chips are the same, and the duration of the effective synchronization pulse stage is the same;

the effective strobe stage of the data strobe signal of each driving chip is positioned in the effective synchronous pulse stage of the line synchronous signal of the driving chip;

the gating interval of the data gating signals corresponding to the driving chip with a large number of connected data lines is smaller than the gating interval of the data gating signals corresponding to the driving chip with a small number of connected data lines;

wherein, the time difference between the starting time of the effective synchronous pulse phase of the line synchronous signal and the starting time of the effective strobe phase of the data strobe signal is a first gap; the time difference between the end time of the effective strobe phase of the data strobe signal and the end time of the effective synchronization pulse phase of the row synchronization signal is a second gap; the sum of the first gap and the second gap is the gating gap.

2. The display device according to claim 1, wherein the first gaps of the data strobe signals corresponding to the driving chips are the same;

the second gap of the data strobe signal corresponding to the driving chip with a large number of the connecting data lines is smaller than the second gap of the data strobe signal corresponding to the driving chip with a small number of the connecting data lines.

3. The display device according to claim 1, wherein the second gaps of the data strobe signals corresponding to the driving chips are the same;

the first interval of the data strobe signal corresponding to the driving chip with a large number of the connecting data lines is smaller than the first interval of the data strobe signal corresponding to the driving chip with a small number of the connecting data lines.

4. The display device according to claim 1, wherein the display device comprises two driver chips, a first driver chip and a second driver chip; the number of the data lines electrically connected with the first driving chip and the second driving chip is different.

5. The display device according to claim 1, wherein the display device comprises three driver chips, namely a first driver chip, a second driver chip and a third driver chip; the number of the data lines electrically connected with the first driving chip and the third driving chip is the same, and the number of the data lines electrically connected with the first driving chip and the second driving chip is different.

6. The display device according to claim 5, wherein the first driver chip, the second driver chip, and the third driver chip are sequentially arranged in a direction perpendicular to the data lines, and the number of data lines electrically connected to the second driver chip is greater than the number of data lines electrically connected to the first driver chip.

7. A driving method of a display device, wherein the display device comprises a plurality of driving chips; the number of the data lines electrically connected with at least part of the driving chips is different; the method comprises the following steps:

acquiring a display control signal;

analyzing the display control signal to obtain a line synchronization signal;

the line synchronizing signal period of each driving chip is the same, and the duration of the effective synchronizing pulse stage is the same;

the method further comprises the following steps:

analyzing the display control signal to obtain a data gating signal;

wherein the valid strobe phase of the data strobe signal is within the valid sync pulse phase of the row sync signal; the gating interval of the data gating signals corresponding to the driving chips which are connected with a large number of data lines is smaller than the gating interval of the data gating signals corresponding to the driving chips which are connected with a small number of data lines; the time difference between the starting time of the effective synchronous pulse phase of the line synchronous signal and the starting time of the effective strobe pulse phase of the data strobe signal is a first gap; the time difference between the end time of the effective strobe phase of the data strobe signal and the end time of the effective synchronization pulse phase of the row synchronization signal is a second gap; the sum of the first gap and the second gap is the gating gap.

8. The driving method according to claim 7, wherein the first gaps of the data strobe signals corresponding to the driving chips are the same;

and the second gap of the data strobe signal corresponding to the driving chip with a large number of connection data lines is smaller than the second gap of the data strobe signal corresponding to the driving chip with a small number of connection data lines.

9. The driving method according to claim 7, wherein the second gaps of the data strobe signals corresponding to the driving chips are the same;

the first gap of the data strobe signal corresponding to the driving chip with a large number of connection data lines is smaller than the first gap of the data strobe signal corresponding to the driving chip with a small number of connection data lines.